IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

10, OCTOBER 2010 2607

Hybrid PWM Strategy of SVPWM and VSVPWM

for NPC Three-Level Voltage-Source Inverter
Wei-dong Jiang, Shao-wu Du, Liu-chen Chang, Yi Zhang, and Qin Zhao

Abstract—Neutral-point (NP) voltage drift is the main techni-

cal drawback of NP-clamped (NPC) three-level inverters. Tradi-
tional space vector pulsewidth modulation (SVPWM) is incapable
of controlling the NP voltage for high modulation indexes and low
power factors. Virtual SVPWM (VSVPWM) is capable of control-
ling the NP voltage under full modulation indexes and full power
factors. However, this modulation strategy is more complex than
SVPWM, increases the switching frequency, and deteriorates the
output waveforms of the inverter. A novel PWM concept that in-
cludes NP voltage-balancing conditions is proposed. Based on this
concept, a hybrid modulation scheme that uses both SVPWM and
VSVPWM is presented for complete control of the NP voltage in
NPC three-level inverters. The performance of this new modula-
tion approach and its benefits over SVPWM and VSVPWM are
verified by simulation and experiments.
Index Terms—Hybrid pulsewidth modulation (PWM), neutral-
point (NP) clamped (NPC), space vector pulsewidth modulation
(SVPWM), three-level inverter, virtual SVPWM (VSVPWM).

I. INTRODUCTION
ULTILEVEL converter topologies have received much
M attention during the past two decades due to their signifi-
cant advantages in high-power medium- and high-voltage appli-
cations [1], such as in ac motor drives, flexible ac-transmission
systems, electric energy quality management, and grid-inactive
power compensation and absorbability. Compared to two-level
inverters, in multilevel inverters, the voltage blocked by each
semiconductor is reduced. Problems caused by the direct series
interconnection of power-switching devices are thus avoided,
and harmonics of the output voltage are reduced. However, a
larger number of semiconductors are needed, and the modula-
tion strategy to control them becomes more complex.
There are the following three main converter topologies [2]:
Fig. 1. Schematic of NPC three-level inverter and its space vector graph.
neutral-point (NP) clamped (NPC), cascaded H-bridge, and ca- (a) Topology of NPC three-level inverter. (b) Space vector diagram of NPC
pacitor clamped. Among these topologies, the three-level three- three-level inverter.
phase NPC dc–ac converter, as shown in Fig. 1(a), is the most
popular. During NPC three-level inverter operation, the NP volt-
age must be half of the dc voltage. Following two phenomena NP voltage drift increases the voltage stress across the power
exist: 1) the NP voltage oscillates at low frequency, low-order devices, which may damage the devices. Several methods have
harmonics increase, and the output waveforms distort and 2) the been proposed to control the NP voltage [3]–[13].
The first method is to use two separate dc sources [3], [4].
The dc sources are usually provided by a transformer with two
Manuscript received March 16, 2009; revised May 31, 2009; accepted June separated windings through diode full-bridge rectifiers. Such a
5, 2009. Date of current version September 17, 2010. Recommended for publi- dc source is large, less-efficient, and expensive.
cation by Associate Editor D. Xu. The second method is to inject a current into the NP by using
The authors are with the School of Electrical and Automation Engi-
neering, Hefei University of Technology, Hefei 230009, China (e-mail: an additional converter. The main shortcoming of this method
[email protected]; [email protected]; [email protected]; [email protected]; is the additional hardware, which adds to the system cost and
[email protected]). complexity of control [5], [6].
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. The third method is to connect the NP of the inverter and the
Digital Object Identifier 10.1109/TPEL.2010.2041254 NP of the corresponding ac-side system. The drawback of this
0885-8993/$26.00 © 2010 IEEE
2608 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

TABLE I large voltage vectors (LVVs). The classification is shown in

RELATIONSHIP BETWEEN OUTPUT LEVEL AND GATING DEVICE
Table II. From Fig. 1(b), the space vector diagram for an NPC
three-level inverter is divided into six sections. These are labeled
as section A to section F; each section is divided into four
subsections (labeled as subsection A1 to F4).
The reference vector Vref can be expressed as (1), where m
is the modulation index in the linear modulation region (m ∈
[0, 1]), and θ is the azimuth angle of the reference vector, as
method is the existence of zero-sequence current on the ac side, shown in Fig. 2
which may not be acceptable due to heating, magnetic saturation 2
of transformer, or other issues [7]. Vref = (vA + αvB + α2 vC ) = mVdc ej θ = Vx + jVy . (1)
3
In some applications, a back-to-back connection of NPC con-
verters is used, where an active NPC rectifier with the same
topology is required. The cost of this converter is high. This so- If the peak value of the line voltage is mVdc , then, the instan-
lution is especially interesting for motor drive applications with taneous value of the line voltage is given by
regenerative requirement. This method can also balance the NP   π
voltage [8]–[10]. 
 vA B = mVdc cos θ +

 6
The most attractive approach is to modify the inverter switch- 
 
 π
ing pattern according to a specific control strategy to balance vB C = mVdc cos θ − (2)
 2
NP voltages [11]–[13]. Although this approach requires a more 
  


elaborate control algorithm as compared with the previous meth- 
 vC A = mVdc cos θ + 5π .
ods, it provides an economical approach to tackle the main tech- 6
nical issues of the NPC three-level inverter.
The application of traditional modulation techniques such as Using (1) and (2), vA B and vB C can be expressed as follows:
space vector pulsewidth modulation (SVPWM) or sinusoidal  √
carrier-based PWM (SPWM) to this topology causes a low- v =
3 1
Vx − Vy
AB
frequency (three times the fundamental frequency of the output 2 2 (3)

voltage) oscillation of the NP voltage for high modulation in- vB C = V y
dexes and low power factors [14]–[17]. This drawback is inher-
ent for SVPWM or SPWM. A PWM strategy based on a virtual when the θ ∈ [0, π/3], vA B , vB C ≥ 0. To simplify further dis-
SVPWM (VSVPWM) concept, capable of controlling the NP cussions, assume that the sample time TS = 1 is a time unit and
voltage over the linear modulation-index region and for all-load the dc voltage Vdc = 1 is a voltage unit.
power factors, was presented and analyzed [18]–[21].
This paper presents a novel PWM concept that includes NP III. GENERAL PWM MODEL FOR NPC
voltage-balancing conditions. Based on this concept, a hybrid THREE-LEVEL INVERTER
modulation scheme that uses both SVPWM and VSVPWM
is presented for complete control of the NP voltage in NPC If θ ∈ [0, π/3] and assuming that the output level of each
three-level inverters. The performance of this new modulation phase voltage during one sample cycle is not restricted, then
approach and its benefits over SVPWM and VSVPWM are the line-voltage modulation strategy based on the volts–second
verified by simulation and experiments. product is as follows:

(t2,A + 0.5t1,A ) − (t2,B + 0.5t1,B ) = vA B > 0
II. THREE-LEVEL INVERTER TOPOLOGY AND ITS (4)
SPACE VECTOR DIAGRAM (t2,B + 0.5t1,B ) − (t2,C + 0.5t1,C ) = vB C > 0.

The three-level inverter diagram of Fig. 1(a) shows two capac- Here tn ,A means the time of output level n of the phase A.
itors C1 and C2 that serve as a voltage divider. The relationship The sum of time of each level of each phase is given by
between the output level of each phase and the gated-on device
is shown in Table I. t0,x + t1,x + t2,x = 1, x = A, B, C. (5)
The space vector diagram shown in Fig. 1(b) is made up of 27
switching states and 19 voltage vectors. The voltage vector can The combination of (4) and (5) give the general PWM model
be expressed by an ordinal number array, for example, [2 1 0] of an NPC three-level inverter. Assuming that the amplitude
corresponds to the connection of phase A to the positive bus, and direction of the three-phase current does not vary during
phase B to the NP, and phase C to the negative bus. one sample cycle, the NP voltage-balancing condition is that
The voltage vectors can be divided into five types, according the sum of current injected into the neutral must equal zero in
to their amplitude and influence on the NP voltage: zero voltage one sample cycle, i.e.,
vector (ZVV), upper short voltage vectors (USVVs), lower short
voltage vectors (LSVVs), medium voltage vectors (MVVs), and iA t1,A + iB t1,B + iC t1,C = 0. (6)
JIANG et al.: HYBRID PWM STRATEGY OF SVPWM AND VSVPWM FOR NPC THREE-LEVEL VOLTAGE-SOURCE INVERTER 2609

TABLE II
CLASSIFICATION OF SPACE VECTOR OF THREE-LEVEL INVERTER

Fig. 3. Vector synthesis of SVPWM for NPC three-level inverter.

Fig. 2. Reference voltage vector of voltage source inverter.

Describing (4)–(6) in matrix form nearest three vectors based on the volts–second product is as
  follows:
t2,A
t 
   1,A  t1L V1L + t2 V2 + t3 V3 + t1U V1U = Vref
1 0.5 0 −1 −0.5 0 0 0 0  
 t0,A  (8)
0 0 0 1 0.5 0 −1 −0.5 0   t1L + t2 + t3 + t1U = 1.
 t 
   2,B 
1 1 1 0 0 0 0 0 0 
   t1,B 
0 0 0 1 1 1 0 0 0   The integral value of NP current in one sample cycle must be
 t 
   0,B  zero to avoid variations in the NP voltage. In order to achieve
0 0 0 0 0 0 1 1 1 
 t2,C  this goal, the appropriate combination of switching states must
0 iA 0 0 iB 0 0 iC 0 t

 be selected for the small voltage vectors. For example, V1L has a
 1,C 
corresponding small vector V1U that generates the same output
t0,C
voltage vector. The NP current has the same magnitude in either
  case, but its sign reverses depending on which of the two vectors
vA B
v  is selected. Therefore, the NP voltage changes to higher or lower
 BC 
  values by distributing the value of t1L and t1U .
 1 
=
 1
.
 (7) The additional restrictive condition adding for (7), for
  SVPWM by a sequence of the NTV, is that the output level
 
 1  of each phase is only composed of two levels in one sample
cycle. When θ ∈ [0, π/3], vA B , vB C ≥ 0, there are four cases
0
that may occurs, which are as follows.
Equation (7) is the model of the general PWM strategy for Case A: The output levels of phase A are composed of level 2
an NPC three-level inverter with the NP voltage-balancing con- and level 1, the output levels of phase B are composed of
dition. The number of equations is less than the number of un- level 2 and level 1, and the output levels of phase C are com-
knowns; therefore, the solution of (7) is not singular. Other addi- posed of level 1 and level 0. Equation (7) can be simplified as
tional restrictive conditions must be added to the general PWM follows:
model (7) for a specific PWM strategy to obtain a specific solu-
    
tion. By adding different restrictive conditions, different PWM 1 0.5 −1 −0.5 0 0 t2,A vA B
strategies can be acquired. Additional restrictive conditions for 0 0 1 0.5 −0.5  
0   t1,A  v 
   BC 
SVPWM and VSVPWM are presented in the next section.     
1 1 0 0 0 0   t2,B   1 
  = .
0 0 1 1 0 0    1 
IV. SVPWM AND ITS NP VOLTAGE-BALANCING METHOD    t1,B   
    
Fig. 3 shows the space vector diagram of section A for the 0 0 0 0 1 1   t1,C   1 
three-level NPC inverter. If the reference vector is located in 0 iA 0 iB iC 0 t0,C 0
subsection A2, then the modulation law with a sequence of the (9)
2610 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

The activation time of each phase of each level can be ob-

tained from (9), which is as in (10), shown at the bottom of the
page.
Case B: The output levels of phase A are composed of level 2
and level 1, the output levels of phase B are composed of level
1 and level 0, and the output levels of phase C are composed of
level 1 and level 0. Equation (7) can be simplified as follows:

    
1 0.5 −0.5 0 0 0 t2,A vA B
0 0 0.5 0 −0.5 0    vB C  Fig. 4. Vector synthesis of VSVPWM for NPC three-level inverter.
   t1,A   
    
1 1 0 0 0 0   t1,B   1 
  =  . (11)
0 0 1 1 0 0    1 
   t0,B   
     three vectors based on the volts–second product is given by the
0 0 0 0 1 1   t1,C   1 
following:
0 iA iB 0 iC 0 t0,C 0

The activation time of each phase of each level can be obtained t2 V2 + t5 V5 + t3 V3 = Vref
(14)
from (11), as shown in (12), at the bottom of the page. t2 + t5 + t3 = 1.
The other two cases of the output levels of each phase are both
2 and 1, and the output levels of each phase are both 1 and 0.
Because the matrix in (11) is not singular, solutions for (11) are The voltage vectors V3 and V5 have no effect on the NP
not satisfied in the restrictive condition of PWM model. If one voltage. When the voltage vector V1L is activated, the NP current
arranges the output level of each phase from low to high, then is iA , the NP current is iB for V2 , and the NP current is iC for
the specific SVPWM with NP voltage balancing in one sample V4U . By distributing the activation time of V2 to V1L , V2 , and
cycle can be acquired. The reference vector is synthesized by V4U evenly, the sum of the NP currents is zero. Therefore,
using seven steps. VSVPWM is not limited by the modulation index or the load
power factor.
The additional restrictive condition for VSVPWM is that the
V. VSVPWM AND ITS NP VOLTAGE-BALANCING METHOD output levels with the highest phase voltage are 2 and 1, with
2, 1, and 0 for the medium phase voltage, and 1 and 0 for the
The space vector diagram of VSVPWM in section A is shown lowest phase voltage. The VSVPWM also can be acquired from
in Fig. 4. A virtual voltage vector V2 is introduced as follows: general PWM model [see (7)]. For example, if θ ∈ [0, π/3],
vA B , vB C ≥ 0, t, the output levels of phase A are composed of
1 level 2 and level 1, the output levels of phase B are composed
V2 = (V1L + V2 + V4U ). (13)
3 of level 2, level 1, and level 0, and the output levels of phase
C are composed of level 1 and level 0. Considering that iA +
If the reference vector is located in subsection A2, as shown iB + iC = 0, the natural solution for (6) is as follows:
in Fig. 4, the modulation law with a sequence of the nearest
t1,A = t1,B = t1,C . (15)


 iB

 t2,A = (vA B + vB C ) − vA B , t1,A = 1 − t2,A , t0,A = 0

 iC
 iA
t2,B = vB C + vA B , t1,B = 1 − t2,B , t0,B = 0 (10)

 iB

 iA

 t2,C = 0, t1,C = 1 − vB C + vA B , t0,C = 1 − t1,C .
iC


 iC

 t2,A = vA B − vB C , t1,A = 1 − t2,A , t0,A = 0

 iA

 iC
t2,B = 0, t1,B = 1 − vA B + vB C , t0,B = 1 − t1,B (12)

 iA



 i
 t2,C = 0, B
t1,C = −vA B + vB C , t0,C = 1 − t1,C .
ia
JIANG et al.: HYBRID PWM STRATEGY OF SVPWM AND VSVPWM FOR NPC THREE-LEVEL VOLTAGE-SOURCE INVERTER 2611

Fig. 5. Relationship between m, ϕ, and θ NP voltage can be balanced in one sample cycle. (a) ϕ ≥ 0. (b) ϕ ≤ 0.

The VSVPWM model can be acquired by combining (7) and is low. This is because the NP current introduced by the MVV
(15) given by cannot be fully compensated by the NP current introduced by
     SVV. In (10) and (12), every time value must be nonnegative.
1 0.5 −1 −0.5 0 0 0 t2,A vA B
0 0 When the reference vector is located in section A, then the
 1 0.5 0 −0.5 0    
  t1,A   vB C 

modulation index m, power factor angle ϕ, and the azimuth
    
1 1 0 0 0 0 0   
   t2,B   1  of reference vector θ must satisfy the following conditions. The
0 0  
0   t1,B  =  1 
  process of educing the following equations can be found in [15]:
 1 1 1 0 .
     In subsection A2
0 0 0 0 0 1 1 t   1 
   0,B       
0 1 −1 0   
0   t1,C   0 
 1
 2(1 − n)π 
 0 0  m ≤ |cos(ϕ − θ)| n
(−1)  cos + ϕ − ωt 
0 0 0 −1 0 0 1 t0,C 0 n =0
3
 −1
(16) nπ
× sin + ωt . (18a)
The activation times of every level of three phases can be 3
solved from (16) as in (17), shown at the bottom of the page.
In subsection A3
The VSVPWM strategy has the following disadvantages.
 2     2   
1) Judging where the reference vector is located and cal-  2nπ   
m≤  cos + ϕ − θ  2  cos 2nπ + ϕ − θ 
culating the activation time of the voltage vector is  3   3 
complex. n =0 n =0
 −1
2) The switching frequency is 4/3 times that of SVPWM, nπ
3) The rule of synthesizing the reference vector is non nearest × sin + (−1)n θ . (18b)
3
three vectors; therefore, the harmonics are higher than that
of SVPWM at same sample time. In subsection A4
4) Accumulated errors can limit the validity of the VSVPWM      
 4π  1  4(1 − n)π
strategy. 
m ≤  cos 
+ϕ−θ  n
(−1)  cos
3 n =0
3
  −1
VI. HYBRID STRATEGY OF SVPWM AND VSVPWM  π

+ ϕ − θ  sin n
+ (−1) θ . (18c)
A. Hybrid PWM Strategy 3
As discussed previously, SVPWM have more advantages over The results of (18a)–(18c) are shown in Fig. 5. From this
VSVPWM. But the balancing of NP voltage cannot be attained figure, if SVPWM is used, when the load power factor angle
when the modulation index is high and the load power factor is ±10◦ , the modulation index m must be smaller than 0.9,


 t2,A = vA B + vB C , t1,A = 1 − t2,A ,
 t0,A = 0
t2,B = vB C , t1,B = 1 − vA B − vB C , t0,B = vA B (17)


t2,C = 0, t1,C = 1 − vA B − vB C , t0,C = vA B + vB C .
2612 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

Fig. 6. Ratio of SVPWM in hybrid PWM strategy.

considering that the NP voltage can be balanced in every sample

cycle. Modulation index m must be smaller than 0.8 if the load
power factor angle is ±30◦ . In addition, the lower power factor
means that the region, where the NP voltage can be balanced is
smaller. Therefore, the balanced NP voltage cannot be attained
using SVPWM under some condition.
If each activation time calculated in (10) or (12) is nonnega- Fig. 7. Block diagram of algorithm for hybrid PWM strategy.
tive, the SVPWM modulation strategy with NP voltage balanc-
ing in one sample cycle can be selected. Otherwise, VSVPWM
is selected. Therefore, not only the NP voltage can be balanced The amount of charge that should be injected into, or flow
in one sample cycle, but also the switching times and harmonic from, NP is as follows:
content are lower than for the VSVPWM strategy. Consequently,
iA t1,A + iB t1,B + iC t1,C = 2C∆v. (20)
the proposed hybrid strategy has the advantages over SVPWM
and VSVPWM. From (10), by adding a additional time ∆t to t2,A , the time
The ratio of SVPWM used in the hybrid PWM strategy is t1,A = t1,A − ∆t, t1,B = t1,B − ∆t, and t1,C = t1,C + ∆t.
shown in Fig. 6. When m ≤ 0.5, the NP voltage is always Therefore
balanced under SVPWM strategy, regardless of the power factor
angle. Therefore, the hybrid PWM strategy is fully composed of iA (t1,A − ∆t) + iB (t1,B − ∆t) + iC (t1,C + ∆t) = 2C∆v.
SVPWM. As modulation index increases, the ratio of SVPWM (21)
decreases at the same power factor angle. From Fig. 6, it is can Considering iA + iB + iC = 0 and t1,A = t1,B = t1,C
be revealed when the modulation index m ∈ [0.577, 1] and the C∆v
power factor cos ϕ = 0, SVPWM is not active; and VSVPWM ∆t = . (22)
iC
is always activated in each sample cycle. In other condition, the
hybrid PWM strategy is composed of SVPWM and VSVPWM. The activation time of every level of the three phases can be
regulated as follows:
  
B. Improved Hybrid PWM Strategy  t2,A = t2,A + ∆t, t1,A = t1,A − ∆t

t2,B = t2,B + ∆t, t1,B = t1,B − ∆t (23)
Because the level 1 of each phase does not output at the same 
  
time, the NP voltage-balance condition given in (6) is not strictly t1,C = t2,C + ∆t, t0,C = t0,C − ∆t.
satisfied. The effect of accumulative error must be considered.
Similarly, for (12)
Most importantly, there must be a feedback approach so that the
unbalance in capacitor voltage can be alleviated by the selected C∆v
∆t = − . (24)
PWM strategy. iA
The voltage divider capacitors C1 and C2 are connected in
The activation time of every level of the three phases can be
parallel for NP voltage. The capacitor value for NP voltage is
regulated as follows:
2C, assuming that the capacitances of C1 and C2 are equal.
  
 t2,A = t2,A + ∆t, t1,A = t1,A − ∆t

When unbalanced, the NP voltage is given by
t1,B = t1,B + ∆t, t0,B = t0,B − ∆t (25)
VC 2 1 
 
∆v = − Vdc . (19) t1,C = t1,C + ∆t, t0,C = t0,C − ∆t.
Vdc 2
JIANG et al.: HYBRID PWM STRATEGY OF SVPWM AND VSVPWM FOR NPC THREE-LEVEL VOLTAGE-SOURCE INVERTER 2613

Fig. 8. Simulated SVPWM waveforms. (a) Phase voltage. (b) Line voltage. (c) Spectrum of line voltage. (d) Line current. (e) Spectrum of line current. (f) NP
current. (g) NP voltage. (h) Spectrum of NP voltage.
2614 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

Fig. 9. Simulated VSVPWM waveforms. (a) Phase voltage. (b) Line voltage. (c) Spectrum of line voltage. (d) Line current. (e) Spectrum of line current. (f) NP
current. (g) NP voltage. (h) Spectrum of NP voltage.
JIANG et al.: HYBRID PWM STRATEGY OF SVPWM AND VSVPWM FOR NPC THREE-LEVEL VOLTAGE-SOURCE INVERTER 2615

Fig. 10. Simulated hybrid PWM waveforms. (a) Phase voltage. (b) Line voltage. (c) Spectrum of line voltage. (d) Line current. (e) Spectrum of line current.
(f) NP current. (g) NP voltage. (h) Spectrum of NP voltage.
2616 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

For VSVPWM, either current iA or iC can be used as the

balancing current. The additional time can be acquired by the
following:

C∆v C∆v
∆tA = , ∆tC = . (26)
iA iC

If iA is chosen as the balancing current, then the activa-

tion time of every level of the three phases can be written as
follows:
  
 t2,A = t2,A + ∆tC , t1,A = t1,A − ∆tC

t2,B = t2,B + ∆tC , t1,B = t1,B − ∆tC , t0,B = t0,B (27)

 
t1,C = t1,C + ∆tC , t0,C = t0,C − ∆tC .

Similarly, if iC is chosen as the balancing current, then the

activation time of every level of the three phases can be written
as follows:
  
 t2,A = t2,A − ∆tA , t1,A = t1,A + ∆tA

t2,B = t2,B , t1,B = t1,B − ∆tA , t0,B = t0,B + ∆tA (28)

  Fig. 11. Prototype of NPC three-level inverter in laboratory.
t1,C = t1,C − ∆tA , t0,C = t0,C + ∆tA .
TABLE III
MAIN PARAMETER OF SYSTEM
To provide the maximum balancing of the NP voltage, the
phase current with the larger amplitude should be chosen to com-
pensate accumulative errors. The transition between SVPWM
and VSVPWM is the same as given earlier. The diagram of
algorithm for hybrid PWM strategy is shown in Fig. 7.

VII. SIMULATION AND EXPERIMENT RESULTS

A. Simulation Results
MATLAB simulations of the three-level NPC inverter were
conducted to verify the theoretical analysis given in this paper. B. Experimental Implement and Results
Figs. 8–10 show the simulation results of SVPWM with the NP A prototype ac motor drive with a front-end diode-bridge
voltage-balancing control strategy of VSVPWM with the NP rectifier and an NPC three-level inverter was built in the labora-
voltage-balancing control strategy and of the proposed hybrid tory, as shown in Fig. 11. The parameter of system is given in
PWM. The simulation results show the following. Table III. The motor control scheme was standard constant V /f
1) There exists an oscillation on the NP voltage under the control. The control was implemented with a TMS320F2812
SVPWM strategy, whose frequency is three times the out- DSP controller. Two motor currents and two dc-link capaci-
put frequency from Fig. 8. The amplitude of this low- tor voltages were measured to implement the voltage-balancing
frequency ripple is about 4.88 V. There also exists a high- scheme.
frequency oscillation on the NP voltage, whose frequency Comparing the experimental results of the three modulation
is the sample frequency. strategies from Figs. 12–14, the VSVPWM and hybrid PWM
2) From Fig. 9, using the VSVPWM strategy, low-frequency can control the NP voltage without low-frequency oscillations,
oscillations of the NP voltage are eliminated, but the har- but when the inverter is controlled by SVPWM, there exists
monics of the line voltage and current deteriorate. a low-frequency oscillation in the NP voltage. The smoothest
3) From Fig. 10, using the hybrid PWM strategy, the NP current waveform is acquired when SVPWM is used, and the
voltage is similar to that of VSVPWM. The harmonic most inferior current appears when VSVPWM is used. The
content of the line voltage and current is between that performance of the hybrid PWM strategy is between those of
of SVPWM and VSVPWM. This shows that the hybrid SVPWM and VSVPWM. It can be seen from these figures that
PWM strategy has advantages of both the SVPWM and there is good agreement between simulations and experiments.
VSPWM strategies. In addition, complex calculations to From Fig. 14, in some sample cycle, it is similar with SVPWM
identify the subsection in which the reference vector is and the other is similar with VSVPWM; this is in accordance
located are avoided. with the theoretical analysis in Section VI.
JIANG et al.: HYBRID PWM STRATEGY OF SVPWM AND VSVPWM FOR NPC THREE-LEVEL VOLTAGE-SOURCE INVERTER 2617

Fig. 12. Experiment SVPWM waveforms. (a) Trigger pulse of switch device. (b) Phase voltage. (c) Line voltage. (d) Line current. (e) NP current. (f) NP voltage.

Fig. 13. Experimental VSVPWM waveforms. (a) Trigger pulse of switch device. (b) Phase voltage. (c) Line voltage. (d) Line current. (e) NP current. (f) NP
voltage.
2618 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

Fig. 14. Experimental hybrid PWM waveforms. (a) Trigger pulse of switch device. (b) Phase voltage. (c) Line voltage. (d) Line current. (e) NP current. (f) NP
voltage.

VIII. CONCLUSION [4] R. W. Menzies, P. Steimer, and J. K. Steinke, “Five level GTO inverter for
large induction motor drives,” IEEE Ind. Appl. Soc. Annu. Meet. (IAS),
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