CS5509

Single Supply, 16-Bit A/D Converter

Features Description
l Delta-Sigma A/D Converter The CS5509 is a single supply, 16-bit, serial-output
- 16-bit No Missing Codes CMOS A/D converter. The CS5509 uses charge-bal-
anced (delta-sigma) techniques to provide a low cost,
- Linearity Error: ±0.0015%FS high resolution measurement at output word rates up to
l Differential Input 200 samples per second.
- Pin Selectable Unipolar/Bipolar Ranges The on-chip digital filter offers superior line rejection at
- Common Mode Rejection 50 Hz and 60 Hz when the device is operated from a
105 dB @ dc 32.768 kHz clock (output word rate = 20 Hz.).
120 dB @ 50, 60 Hz
The CS5509 has on-chip self-calibration circuitry which
l Either 5 V or 3.3 V Digital Interface can be initiated at any time or temperature to ensure
l On-chip Self-Calibration Circuitry minimum offset and full-scale errors.
l Output Update Rates up to 200/second Low power, high resolution and small package size
l Ultra Low Power: 1.7 mW make the CS5509 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery
powered instruments.

ORDERING INFORMATION
CS5509-AP -40° to +85° C 16-pin Plastic DIP
CS5509-AS -40° to +85° C 16-pin SOIC
I

VREF+ VREF- VA+ DGND VD+

9 10 11 12 13

1
CS
Serial 14
7 SCLK
AIN+ Differential Interface 15
Digital Logic SDATA
4th-Order
Filter 16
8 Delta-Sigma DRDY
AIN- Modulator

3
CAL
Calibration µC 6
BP/UP
Calibration SRAM OSC

2 4 5

CONV XIN XOUT

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1997 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS125F1
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 CS5509

ANALOG CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V,
VREF- = 0V; fCLK = 330kHz; Bipolar Mode; Rsource = 50Ω with a 10nF to GND at AIN; AIN- = 2.5V; unless
otherwise specified.) (Notes 1, 2)
Parameter* Min Typ Max Units
Accuracy
Linearity Error fCLK = 32.768 kHz - 0.0015 0.003 ±%FS
fCLK = 165 kHz - 0.0015 0.003 ±%FS
fCLK = 247.5 kHz - 0.0015 0.003 ±%FS
fCLK = 330 kHz - 0.005 0.0125 ±%FS
Differential Nonlinearity - ±0.25 ±0.5 LSB
Full Scale Error (Note 3) - ±0.25 ±2 LSB
Full Scale Drift (Note 4) - ±0.5 - LSB
Unipolar Offset (Note 3) - ±0.5 ±2 LSB
Unipolar Offset Drift (Note 4) - ±0.5 - LSB
Bipolar Offset (Note 3) - ±0.25 ±1 LSB
Bipolar Offset Drift (Note 4) - ±0.25 - LSB
Noise (Referred to Output) - 0.16 - LSBrms
Analog Input
Analog Input Range: Unipolar - 0 to +2.5 - Volts
Bipolar (Note 5, 6) - ±2.5 - Volts
Common Mode Rejection: dc - 105 - dB
fCLK = 32.768kHz 50,60 Hz (Note 2) 120 - - dB
Input Capacitance - 15 - pF
DC Bias Current (Note 1) - 5 - nA
Power Supplies
DC Power Supply Currents: ITotal - 360 450 µA
IAnalog - 300 - µA
IDigital - 60 - µA
Power Dissipation (Note 7) - 1.7 2.25 mW
Power Supply Rejection - 80 - dB
Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509’s source
impedance requirements. Refer to the text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25°C.
5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.
6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509
will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will
output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will
output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all
0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).
7. All outputs unloaded. All inputs CMOS levels.

* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

2 DS125F1
 CS5509

DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
Modulator Sampling Frequency fs fclk/2 Hz
Output Update Rate (CONV = 1) fout fclk/1622 Hz
Filter Corner Frequency f-3dB fclk/1928 Hz
Settling Time to 1/2 LSB (FS Step) ts 1/fout s

5V DIGITAL CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; GND = 0.)

(Notes 2, 8)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage: XIN VIH 3.5 - - V
All Pins Except XIN VIH 2.0 - - V
Low-Level Input Voltage: XIN VIL - - 1.5 V
All Pins Except XIN VIL - - 0.8 V
High-Level Output Voltage (Note 9) V OH (VD+)-1.0 - - V
Low-Level Output Voltage Iout = 1.6mA VOL - - 0.4 V
Input Leakage Current Iin - ±1 ±10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF
Notes: 8. All measurements are performed under static conditions.
9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA).

3.3V DIGITAL CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; GND =
0.) (Notes 2, 8)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage: XIN VIH 0.7VD+ - - V
All Pins Except XIN VIH 0.6VD+ - - V
Low-Level Input Voltage: XIN VIL - - 0.3VD+ V
All Pins Except XIN VIL - - 0.16VD+ V
High-Level Output Voltage Iout = -400µA VOH (VD+)-0.3 - - V
Low-Level Output Voltage Iout = 400µA VOL - - 0.3 V
Input Leakage Current Iin - ±1 ±10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF

DS125F1 3
 CS5509

5V SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; Input Levels:

Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Master Clock Frequency Internal Oscillator: XIN 30.0 32.768 53.0 kHz
External Clock: fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 10) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL=1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY tbus 82/fclk - - s
falling
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) t con - 1624/f clk - s
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the
power-on reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.

4 DS125F1
 CS5509

3.3V SWITCHING CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Master Clock Frequency Internal Oscillator: XIN 30.0 32.768 53.0 kHz
External Clock: fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 10) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL=1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY tbus 82/fclk - - s
falling
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk - s

DS125F1 5
 CS5509

XIN

XIN/2

CAL
t ccw
CONV
t scl t cal
STATE Standby Calibration Standby

Figure 1. Calibration Timing (Not to Scale)

XIN

XIN/2

CONV
t cpw
DRDY

BP/UP
t bus t buh
t scn t con
STATE Standby Conversion Standby

Figure 2. Conversion Timing (Not to Scale)

6 DS125F1
 CS5509

5V SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; Input Levels: Logic 0
= 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Serial Clock fsclk 0 - 2.5 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time: CS Low to data valid (Note 16) tcsd - 60 200 ns
Maximum Delay Time: SCLK falling to new SDATA bit tdd - 150 310 ns
(Note 17)
Output Float Delay CS High to output Hi-Z (Note 18) tfd1 - 60 150 ns
SCLK falling to Hi-Z tfd2 - 160 300 ns

Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
18. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%, VD+ = 3.3V ± 5%;
Input Levels : Logic 0 = 0V, Logic 1 = VD+; CL = 50pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Serial Clock fsclk 0 - 1.25 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time: CS Low to data valid (Note 16) tcsd - 100 200 ns
Maximum Delay Time: SCLK falling to new SDATA bit tdd - 400 600 ns
(Note 17)
Output Float Delay CS High to output Hi-Z (Note 18) tfd1 - 70 150 ns
SCLK falling to Hi-Z tfd2 - 320 500 ns

DS125F1 7
 CS5509

DRDY

CS
t csd t fd1
SDATA(o) Hi-Z MSB MSB-1 MSB-2
t dd
SCLK(i)

DRDY

CS
t csd
SDATA(o) Hi-Z MSB MSB-1 LSB+2 LSB+1 LSB
t dd t ph t fd2

SCLK(i)
t pl

Figure 3. Timing Relationships (Not to Scale)

8 DS125F1
 CS5509

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Digital VD+ 3.15 5.0 5.5 V
Positive Analog VA+ 4.5 5.0 5.5 V
Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V
Analog Input Voltage: (Note 6)
Unipolar VAIN 0 - (VREF+)-(VREF-) V
Bipolar VAIN -((VREF+)-(VREF-)) - (VREF+)-(VREF-) V

Notes: 19. All voltages with respect to ground.

20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND.

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units
DC Power Supplies: Ground (Note 21) GND -0.3 - (VD+)-0.3 V
Positive Digital (Note 22) VD+ -0.3 - 6.0 V
Positive Analog VA+ -0.3 - 6.0 V
Input Current, Any Pin Except Supplies (Notes 23 & 24) Iin - - ±10 mA
Output Current Iout - - ±25 mA
Power Dissipation (Total) (Note 25) - - 500 mW
Analog Input Voltage AIN and VREF pins VINA -0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature TA -40 - 85 °C
Storage Temperature Tstg -65 - 150 °C
Notes: 21. No pin should go more positive than (VA+)+0.3V.
22. VD+ must always be less than (VA+)+0.3V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
25. Total power dissipation, including all input currents and output currents.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

DS125F1 9
 CS5509

GENERAL DESCRIPTION tion of this command will not occur until the
complete wake-up period elapses. If no com-
The CS5509 is a low power, 16-bit, monolithic mand is given, the device enters the standby
CMOS A/D converter designed specifically for state.
measurement of dc signals. The CS5509 in-
cludes a delta-sigma charge-balance converter, a Calibration
voltage reference, a calibration microcontroller
with SRAM, a digital filter and a serial interface. After the initial application of power, the
CS5509 must enter the calibration state prior to
The CS5509 is optimized to operate from a performing accurate conversions. During calibra-
32.768 kHz crystal but can be driven by an ex- tion, the chip executes a two-step process. The
ternal clock whose frequency is between 30 kHz device first performs an offset calibration and
and 330 kHz. When the digital filter is operated then follows this with a gain calibration. The
with a 32.768 kHz clock, the filter has zeros pre- two calibration steps determine the zero refer-
cisely at 50 and 60 Hz line frequencies and ence point and the full scale reference point of
multiples thereof. the converter’s transfer function. From these
points it calibrates the zero point and a gain
The CS5509 uses a "start convert" command to slope to be used to properly scale the output
start a convolution cycle on the digital filter. digital codes when doing conversions.
Once the filter cycle is completed, the output
port is updated. When operated with a The calibration state is entered whenever the
32.768 kHz clock the ADC converts and updates CAL and CONV pins are high at the same time.
its output port at 20 samples/sec. The output port The state of the CAL and CONV pins at power-
operates in a synchronous externally-clocked in- on are recognized as commands, but will not be
terface format. executed until the end of the 1800 clock cycle
wake-up period.

THEORY OF OPERATION If CAL and CONV become active (high) during

the 1800 clock cycle wake-up time, the con-
Basic Converter Operation verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
The CS5509 A/D converter has three operating time has elapsed, the converter will be in the
states. These are stand-by, calibration, and con- standby mode waiting for instruction and will
version. When power is first applied, an internal enter the calibration cycle immediately if CAL
power-on reset delay of about 10 ms resets all of and CONV become active. The calibration lasts
the logic in the device. The oscillator must then for 3246 clock cycles. Calibration coefficients
begin oscillating before the device can be con- are then retained in the SRAM (static RAM) for
sidered functional. After the power-on reset is use during conversion.
applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This The state of BP/UP is ignored during calibration
allows the delta-sigma modulator and other cir- but should remain stable throughout the calibra-
cuitry (which are operating with very low tion period to minimize noise.
currents) to reach a stable bias condition prior to
entering into either the calibration or conversion When conversions are performed in unipolar
states. During the 1800 cycle wake-up period, mode or in bipolar mode, the converter uses the
the device can accept an input command. Execu- same calibration factors to compute the digital
10 DS125F1
 CS5509

output code. The only difference is that in bipo- Conversion

lar mode the on-chip microcontroller offsets the
computed output word by a code value of The conversion state can be entered at the end of
8000H. This means that the bipolar measure- the calibration cycle, or whenever the converter
ment range is not calibrated from full scale is idle in the standby mode. If CONV is taken
positive to full scale negative. Instead it is cali- high to initiate a calibration cycle ( CAL also
brated from the bipolar zero scale point to full high), and remains high until the calibration cy-
scale positive. The slope factor is then extended cle is completed (CAL is taken low after CONV
below bipolar zero to accommodate the negative transitions high), the converter will begin a con-
input signals. The converter can be used to con- version upon completion of the calibration
vert both unipolar and bipolar signals by period.
changing the BP/UP pin. Recalibration is not re-
quired when switching between unipolar and The BP/UP pin is not a latched input. The
bipolar modes. BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
At the end of the calibration cycle, the on-chip the output word computed by the digital filter is
microcontroller checks the logic state of the offset by 8000H (see Understanding Converter
CONV signal. If the CONV input is low the de- Calibration). BP/UP can be changed after a con-
vice will enter the standby mode where it waits version is started as long as it is stable for 82
for further instruction. If the CONV signal is clock cycles of the conversion period prior to
high at the end of the calibration cycle, the con- DRDY falling. If one wishes to intermix meas-
verter will enter the conversion state and urement of bipolar and unipolar signals on
perform a conversion on the input channel. The various input signals, it is best to switch the
CAL signal can be returned low any time after BP/UP pin immediately after DRDY falls and
calibration is initiated. CONV can also be re- leave BP/UP stable until DRDY falls again.
turned low, but it should never be taken low and
then taken back high until the calibration period The digital filter in the CS5509 has a Finite Im-
has ended and the converter is in the standby pulse Response and is designed to settle to full
state. If CONV is taken low and then high accuracy in one conversion time.
again with CAL high while the converter is cali-
brating, the device will interrupt the current If CONV is left high, the CS5509 will perform
calibration cycle and start a new one. If CAL is continuous conversions. The conversion time
taken low and CONV is taken low and then high will be 1622 clock cycles. If conversion is initi-
during calibration, the calibration cycle will ated from the standby state, there may be up to
continue as the conversion command is disre- two XIN clock cycles of uncertainty as to when
garded. The state of BP/UP is not important conversion actually begins. This is because the
during calibrations. internal logic operates at one half the external
clock rate and the exact phase of the internal
If an "end of calibration" signal is desired, pulse clock may be 180° out of phase relative to the
the CAL signal high while leaving the CONV XIN clock. When a new conversion is initiated
signal high continuously. Once the calibration is from the standby state, it will take up to two
completed, a conversion will be performed. At XIN clock cycles to begin. Actual conversion
the end of the conversion, DRDY will fall to in- will use 1624 clock cycles before DRDY goes
dicate the first valid conversion after the low to indicate that the serial port has been up-
calibration has been completed. dated. See the Serial Interface Logic section of

DS125F1 11
 CS5509

the data sheet for information on reading data Unipolar Input Output Bipolar Input
from the serial port. Voltage Codes Voltage
>(VREF - 1.5 LSB) FFFF >(VREF - 1.5 LSB)
In the event the A/D conversion command FFFF
(CONV going positive) is issued during the con- VREF - 1.5 LSB FFFE VREF - 1.5 LSB
version state, the current conversion will be 8000
terminated and a new conversion will be initi- VREF/2 - 0.5 LSB 7FFF -0.5 LSB
ated. 0001
+0.5 LSB 0000 -VREF +0.5 LSB
Voltage Reference <(+0.5 LSB) 0000 <(-VREF +0.5 LSB)

Note: Table excludes common mode voltage on the

The CS5509 uses a differential voltage reference signal and reference inputs.
input. The positive input is VREF+ and the
negative input is VREF-. The voltage between Table 1. Output Coding
VREF+ and VREF- can range from 1 volt mini- component which is 0.5 volts above the maxi-
mum to 3.6 volts maximum. The gain slope will mum input of 3.0 (3.5 volts peak; 3.0 volts dc
track changes in the reference without recalibra- plus 0.5 volts peak noise) and still accurately
tion, accommodating ratiometric applications. convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise ampli-
Analog Input Range tude stays within the supply voltages.

The analog input range is set by the magnitude The CS5509 converters output data in binary
of the voltage between the VREF+ and VREF- format when converting unipolar signals and in
pins. In unipolar mode the input range will offset binary format when converting bipolar
equal the magnitude of the voltage reference. In signals. Table 1 outlines the output coding for
bipolar mode the input voltage range will equate both unipolar and bipolar measurement modes.
to plus and minus the magnitude of the voltage
reference. While the voltage reference can be as Converter Performance
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs The CS5509 A/D converter has excellent linear-
VREF+ and VREF- stay within the supply volt- ity performance. Calibration minimizes the
ages VA+ and GND. The differential input errors in offset and gain. The CS5509 device
voltage can also have any common mode value has no missing code performance to 16-bits.
as long as the maximum signal magnitude stays Figure 4 illustrates the DNL of the CS5509. The
within the supply voltages. converter achieves Common Mode Rejection
(CMR) at dc of 105 dB typical, and CMR at 50
The A/D converter is intended to measure dc or and 60 Hz of 120 dB typical.
low frequency inputs. It is designed to yield ac-
curate conversions even with noise exceeding The CS5509 can experience some drift as tem-
the input voltage range as long as the spectral perature changes . The CS5509 uses
components of this noise will be filtered out by chopper-stabilized techniques to minimize drift.
the digital filter. For example, with a 3.0 volt Measurement errors due to offset or gain drift
reference in unipolar mode, the converter will can be eliminated at any time by recalibrating
accurately convert an input dc signal up to the converter.
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
12 DS125F1
 CS5509

+1

+1/2
DNL (LSB)

-1/2

-1
0 32,768 65,535
Codes
Figure 4. CS5509 Differential Nonlinearity plot.

Analog Input Impedance Considerations An equation for the maximum acceptable source
resistance is derived.
The analog input of the CS5509 can be modeled
as illustrated in Figure 5. Capacitors (15 pF −1
Rsmax =
each) are used to dynamically sample each of  Ve 
2XIN (15pF + CEXT) ln  
the inputs (AIN+ and AIN-). Every half XIN cy- V + 15pF(100mv) 
cle the switch alternately connects the capacitor  e (15pF + CEXT 
 
to the output of the buffer and then directly to
the AIN pin. Whenever the sample capacitor is This equation assumes that the offset voltage of
switched from the output of the buffer to the the buffer is 100 mV, which is the worst case.
AIN pin, a small packet of charge (a dynamic The value of Ve is the maximum error voltage
demand of current) is required from the input which is acceptable. CEXT is the combination
source to settle the voltage of the sample capaci- of any external or stray capacitance.
tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the For a maximum error voltage (Ve) of 10 µV in
actual input voltage due to the offset voltage of the CS5509 (1/4LSB at 16-bits), the above equa-
the buffer. Timing allows one half of a XIN tion indicates that when operating from a
clock cycle for the voltage on the sample capaci- 32.768 kHz XIN, source resistances up to
tor to settle to its final value. 110 kΩ are acceptable in the absence of external
capacitance (CEXT = 0).

AIN+ The VREF+ and VREF- inputs have nearly the

+ 15 pF same structure as the AIN+ and AIN- inputs.
V os ≤ 100 mV Internal Therefore, the discussion on analog input imped-
-
Bias ance applies to the voltage reference inputs as
Voltage well.
AIN-
15 pF
+
V os ≤ 100 mV
-

Figure 5. Analog Input Model

DS125F1 13
 CS5509

-20 X1 = 32.768kHz Frequency Notch Frequency Minimum

X2 = 330.00kHz (Hz) Depth (Hz) Attenuation
-40 (dB) (dB)
Attenuation (dB)

50 125.6 50±1% 55.5

-60
60 126.7 60±1% 58.4
-80
100 145.7 100±1% 62.2
-100 120 136.0 120±1% 68.4
-120 150 118.4 150±1% 74.9
180 132.9 180±1% 87.9
-140
XIN = 32.768 kHz 200 102.5 200±1% 94.0
-160
X1
240 108.4 240±1% 104.4
0 40 80 120 160 200 240
X2 0 402.83 805.66 1208.5 1611.3 2014.2 2416.9
Frequency (Hz)

Figure 6. Filter Magnitude Plot to 260 Hz Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)

0 180

-20 Flatness 135

Frequency dB
1 -0.010 90
-40 2 -0.041
Phase (Degrees)
Attenuation (dB)

3 -0.093
45
4 -0.166
-60
5 -0.259
0
6 -0.374
-80 7 -0.510
8 -0.667 -45
-100 9 -0.846
10 -1.047 -90
XIN = 32.768 kHz
17 -3.093 XIN = 32.768 kHz
-120 -135

-140 -180
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) Frequency (Hz)

Figure 7. Filter Magnitude Plot to 50 Hz Figure 8. Filter Phase Plot to 50 Hz

Digital Filter Characteristics Figure 6 illustrates the filter attenuation from dc

to 260 Hz. At exactly 50, 60, 100, and 120 Hz
The digital filter in the CS5509 is the combina- the filter provides over 120 dB of rejection. Ta-
tion of a comb filter and a low pass filter. The ble 2 indicates the filter attenuation for each of
comb filter has zeros in its transfer function the potential line interference frequencies when
which are optimally placed to reject line interfer- the converter is operating with a 32.768 kHz
ence frequencies (50 and 60 Hz and their clock. The converter yields excellent attenuation
multiples) when the CS5509 is clocked at of these interference frequencies even if the fun-
32.768 kHz. Figures 6, 7 and 8 illustrate the damental line frequency should vary ± 1% from
magnitude and phase characteristics of the filter.
14 DS125F1
 CS5509

its specified frequency. The -3dB corner fre- Over the industrial temperature range (-40 to
quency of the filter when operating from a +85 °C) the on-chip gate oscillator will oscillate
32.768 kHz clock is 17 Hz. Figure 8 illustrates with other crystals in the range of 30 kHz to 53
that the phase characteristics of the filter are pre- kHz. The chip will operate with external clock
cisely linear phase. frequencies from 30 kHz to 330 kHz over the in-
dustrial temperature range. The 32.768 kHz
If the CS5509 is operated at a clock rate other crystal is normally specified as a time-keeping
than 32.768 kHz, the filter characteristics, in- crystal with tight specifications for both initial
cluding the comb filter zeros, will scale with the frequency and for drift over temperature. To
operating clock frequency. Therefore, optimum maintain excellent frequency stability, these
rejection of line frequency interference will oc- crystals are specified only over limited operating
cur with the CS5509 running at 32.768 kHz. temperature ranges (i.e. -10 °C to +60 °C) by the
manufacturers. Applications of these crystals
Anti-Alias Considerations for Spectral with the CS5509 does not require tight initial
Measurement Applications tolerance or low tempco drift. Therefore, a lower
cost crystal with looser initial tolerance and tem-
Input frequencies greater than one half the out- pco will generally be adequate for use with the
put word rate (CONV = 1) may be aliased by CS5509. Also check with the manufacturer
the converter. To prevent this, input signals about wide temperature range application of
should be limited in frequency to no greater than their standard crystals. Generally, even those
one half the output word rate of the converter crystals specified for limited temperature range
(when will operate over much larger ranges if fre-
CONV =1). Frequencies close to the modulator quency stability over temperature is not a
sample rate (XIN/2) and multiples thereof may requirement. The frequency stability can be as
also be aliased. If the signal source includes bad as ±3000 ppm over the operating tempera-
spectral components above one half the output ture range and still be typically better than the
word rate (when CONV = 1) these components line frequency (50 Hz or 60 Hz) stability over
should be removed by means of low-pass filter- cycle-to-cycle during the course of a day.
ing prior to the A/D input to prevent aliasing.
Spectral components greater than one half the Serial Interface Logic
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the The digital filter in the CS5509 takes 1624 clock
reference voltage to remove these spectral com- cycles to compute an output word once a con-
ponents from the reference voltage is desirable. version begins. At the end of the conversion
cycle, the filter will attempt to update the serial
Crystal Oscillator port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
The CS5509 is designed to be operated using a just prior to a port update it checks to see if the
32.768 kHz "tuning fork" type crystal. One end port is either empty or unselected (CS = 1). If
of the crystal should be connected to the XIN the port is empty or unselected, the digital filter
input. The other end should be attached to will update the port with a new output word.
XOUT. Short lead lengths should be used to When new data is put into the port DRDY will
minimize stray capacitance. go low.

DS125F1 15
 CS5509

Reading Serial Data VD+ or GND pins; VD+ must remain more
positive than the GND pin.
SDATA is the output pin for the serial data.
When CS goes low after new data becomes Figure 9a illustrates the System Connection Dia-
available (DRDY goes low), the SDATA pin gram for the CS5509. Note that all supply pins
comes out of Hi-Z with the MSB data bit pre- are bypassed with 0.1 µF capacitors and that the
sent. SCLK is the input pin for the serial clock. VD+ digital supply is derived from the VA+
If the MSB data bit is on the SDATA pin, the supply. Figure 9b illustrates the CS5509 operat-
first rising edge of SCLK enables the shifting ing from a +5V analog supply and +3.3V digital
mechanism. This allows the falling edges of supply.
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and When using separate supplies for VA+ and
the SCLK signal is high, the first falling edge of VD+, VA+ must be established first. VD+
SCLK will be ignored because the shifting should never become more positive than VA+
mechanism has not become activated. After the under any operating condition. Remember to in-
first rising edge of SCLK, each subsequent fall- vestigate transient power-up conditions, when
ing edge will shift out the serial data. Once the one power supply may have a faster rise time.
LSB is present, the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).

CS can be operated asynchronously to the

DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.

Power Supplies and Grounding

The analog and digital supply pins to the

CS5509 are brought out on separate pins to
minimize noise coupling between the analog and
Schematic & Layout Review Service
digital sections of the chip. In the digital section
Confirm Optimum
of the chip the supply current flows into the
Schematic & Layout
VD+ pin and out of the GND pin. As a CMOS
Before Building Your Board.
device, the CS5509 requires that the supply volt-
age on the VA+ pin always be more positive For Our Free Review Service
than the voltage on any other pin of the device. Call Applications Engineering.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
VA+ voltage must remain more positive than the
16 DS125F1
 CS5509

10Ω

+5V 0.1 µF 0.1 µF

Analog 11 13
Supply VA+ VD+

Optional
Clock 4 14
XIN SCLK Serial
Source Data
5 15
32.768 kHz XOUT SDATA Interface

CS5509

7
Analog AIN+
Signal 8
AIN-
1
CS
2
CONV
3 Control
CAL
+ 9 6 Logic
VREF+
Voltage BP/UP
Reference 10 16
- VREF- DRDY

GND
12

Figure 9a. System Connection Diagram Using a Single Supply

DS125F1 17
 CS5509

Note: VD+ must never be more positive than VA+

+3.3V to +5V
+5V 0.1 µF 0.1 µF Digital
Analog 11 13 Supply
Supply VA+ VD+

Optional
Clock 4 14
XIN SCLK Serial
Source Data
5 15
32.768 kHz XOUT SDATA Interface

CS5509

7
Analog AIN+
Signal 8
AIN-
1
CS
2
CONV
3 Control
CAL
+ 9 6 Logic
VREF+
Voltage BP/UP
Reference 10 16
- VREF- DRDY

GND
12

Figure 9b. System Connection Diagram Using Split Supplies

18 DS125F1
 CS5509

PIN DESCRIPTIONS*

CHIP SELECT CS 1 16 DRDY DATA READY

CONVERT CONV 2 15 SDATA SERIAL DATA OUTPUT
CALIBRATE CAL 3 14 SCLK SERIAL CLOCK INPUT
CRYSTAL IN XIN 4 13 VD+ POSITIVE DIGITAL POWER
CRYSTAL OUT XOUT 5 12 GND GROUND
BIPOLAR/UNIPOLAR BP/UP 6 11 VA+ POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT AIN+ 7 10 VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN- 8 9 VREF+ VOLTAGE REFERENCE INPUT

*Pinout applies to both PDIP and SOIC

Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 1.
This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 16.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 15.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 14.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.

DS125F1 19
 CS5509

Control Input Pins

CAL - Calibrate, Pin 3.
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 2.

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If
CONV is held high (CAL low) the converter will do continuous conversions.

BP/UP - Bipolar/Unipolar, Pin 6.

The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Inputs, Pins 7, 8.
Analog differential inputs to the delta-sigma modulator.

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10.

A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections

VA+ - Positive Analog Power, Pin 11.
Positive analog supply voltage. Nominally +5 volts.

VD+ - Positive Digital Power, Pin 13.

Positive digital supply voltage. Nominally +5 volts or +3.3 volts.

GND - Ground, Pin 12.

Ground.

20 DS125F1
 CS5509

SPECIFICATION DEFINITIONS

Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.

Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.

Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

DS125F1 21
 CS5509

APPENDIX

The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.

Fox Electronics Taiwan X’tal Corp.

5570 Enterprise Parkway 5F. No. 16, Sec 2, Chung Yang S. RD.
Fort Meyers, FL 33905 Reitou, Taipei, Taiwan R. O. C.
(813) 693-0099 Tel: 02-894-1202
Fax: 02-895-6207
Micro Crystal Division / SMH
702 West Algonquin Road Interquip Limited
Arlington Heights, IL 60005 24/F Million Fortune Industrial Centre
(708) 806-1485 34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
SaRonix Fax: 4137053
4010 Transport Street
Palo Alto, California 94303 S& T Enterprises, Ltd.
(415) 856-6900 Rm 404 Blk B
Sea View Estate
Statek North Point, Hong Kong
512 North Main Tel: 5784921
Orange, California 92668 Fax: 8073126
(714) 639-7810
Mr. Darren Mcleod
IQD Ltd. Hy-Q International Pty. Ltd.
North Street 12 Rosella Road,
Crewkerne FRANKSON, 3199
Somerset TA18 7AK Victoria, Australia
England Tel: 61-3-783 9611
01460 77155 Fax: 61-3-783 9703

Mr. Pierre Hersberger

Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57

22 DS125F1
 CDB5509

Evaluation Board for the CS5509 A/D Converter

Features Description
l Operation with on-board 32.768 kHz crystal The CDB5509 is a circuit board designed to provide
or off-board clock source quick evaluation of the CS5509 A/D converter.
l DIP Switch Selectable: The board provides buffered digital signals, an on-board
- BP/UP mode precision voltage reference, options for using an external
l On-board precision voltage reference clock, and a momentary switch to initiate calibration.

l Access to all digital control pins ORDERING INFORMATION

CDB5509 Evaluation Board
I

B
H
U
CS5509 E
F
A
F
D
E
E
R
R
S
AIN+

AIN-
CLKIN
VREF

+5V GND

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1998 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS125DB1
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 23
 CDB5509

Introduction
Most applications will not require the buffer ICs
The CDB5509 evaluation board provides a quick for proper operation.
means of testing the CS5509 A/D converter. The
CS5509 converter requires a minimal amount of To put the board in operation, select either bipo-
external circuitry. The evaluation board comes lar or unipolar mode with DIP switch S2. Then
configured with the A/D converter chip operat- press the CAL pushbutton after the board is
ing from a 32.768 kHz crystal and with an powered up. This initiates calibration of the con-
off-chip precision 2.5 volt reference. The board verter which is required before measurements
provides access to all of the digital interface pins can be taken. With CONV high (S2-3 open) the
of the CS5509 chip. converter will convert continuously. Figure 3 il-
lustrates the CAB5509 adapter board. The
CAB5509 translates a CS5505 pinout to a
Evaluation Board Overview CS5509 pinout.

The board provides a complete means of making Figures 4 and 5 illustrate the evaluation board
the CS5509 A/D converter chip function. The layout while Figure 6 illustrates the component
user must provide a means of taking the output placement (silkscreen) of the evaluation board.
data from the board in serial format and using it
in his system.

Figure 1 illustrates the schematic for the board.

The board comes configured for the A/D con-
verter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a cir-
cuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a 50Ω
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.

The board comes with the A/D converter VREF+

and VREF- pins hard-wired to the 2.5 volt
bandgap voltage reference IC on the board.

All of the control pins of the CS5509 are avail-

able at the J1 header connector. Buffer ICs U2
and U3 are used to buffer the converter for inter-
face to off-board circuits. The buffers are used
on the evaluation board only because the exact
loading and off-board circuitry is unknown.

24 DS125DB1
DS125DB1

R22 +5
+5
+ +5
10 C16
10 µF
DRDY
VD+ CAL
R9 SCLK
+5V +5 +5
C7 C10 C11 SDATA
10 R11
0.1 µF 0.01 µF
+ C2 C5 AGND 0.1 µF 100k
D1
6.8V 10 µF 0.1 µF 11 13 R10 20k
J2

GND DGND VA+ VD+ CAL

3
CAL
C17 VD+ R17
TP10 VD+ CONV
R27 1
2 0.1 µF 3 47k
1A 1K 9 CONV U2A
VREF+ 2
R26 C19 TP9 CS
1K 10nF 1 4 5
1B 10
VREF- CS U2B
C20 VD+ R18
10nF TP8 R19 A0
2 6 2A
+5 6 7 100k 47k
LT1019 U2C
C9 -2.5 V 5 R8 C8 0.1 µF U1 VD+
25k 2B TP7 R20 A1
0.1µF 4 CS5509 100k
10 9
U2D
3A
+ TP11 DRDY
External
16 11 12
VREF 3B DRDY U2E
- TP12
R23
SDATA
100k
15 14 15
SDATA U2F
R24 8 SCLKO
TP13
100k
14 5 6
SCLK U3B 0.1 µF
VD+
R25 4
100k SCLKI
VD+ 14 2 C18
U3A
3 R1
R16 100k BP/UP
TP14 1
6 11 12 100k
TP6 BP/UP U3D
402 7
AIN+ AIN+ 13 J1
R4
R31 R21 7 VD+
100k TP15 U2 74HC4050
402 C15 8 U3C U3 74HC125
AIN- AIN- 8 9 S2
47k
R13 0.01 µF A1
R12 10
100k
A0
R3 XIN XOUT GND
CONV
50 4 5 12
Y1 BP/UP
CLKIN 32.768

CDB5509
R2 kHz
Note: Buffers not required for general applications.
200

Figure 1. ADC Connections

25
 CDB5509

CS 1 16 DRDY
CONV 2 15 SDATA
CAL 3 14 SCLK
XIN 4 13 VD+
XOUT 5 12 GND
BP/UP 6 11 VA+
AIN+ 7 10 VREF-
AIN- 8 9 VREF+

Figure 2. CS5509 Pin Layout

(Top View)
1 24
1 16

8 9

12 13

Figure 3. CAB5509 Adapter Board

26 DS125DB1
 CDB5509

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

DS125DB1 27
 CDB5509

Figure 5. Bottom Trace Layer (NOT TO SCALE)

28 DS125DB1
 CDB5509

A A

CDB5509

Figure 6. Silk Screen Layer (NOT TO SCALE)

DS125DB1 29