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Questions From 10 Question Papers: Module 1: Number Systems and Codes

The document contains questions from 10 question papers covering 6 modules: 1) Number Systems and Codes 2) Logic Gates and Combinational Logic Circuits 3) Different Types of Memory 4) Sequential Logic Circuits 5) Programmable Logic Devices 6) VHSIC Hardware Description Language (VHDL) The questions range from basic concepts to more complex circuit designs including arithmetic circuits, decoders, multiplexers, flip-flops, counters, and VHDL code implementations.

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vidhya seeman
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406 views4 pages

Questions From 10 Question Papers: Module 1: Number Systems and Codes

The document contains questions from 10 question papers covering 6 modules: 1) Number Systems and Codes 2) Logic Gates and Combinational Logic Circuits 3) Different Types of Memory 4) Sequential Logic Circuits 5) Programmable Logic Devices 6) VHSIC Hardware Description Language (VHDL) The questions range from basic concepts to more complex circuit designs including arithmetic circuits, decoders, multiplexers, flip-flops, counters, and VHDL code implementations.

Uploaded by

vidhya seeman
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Questions from 10 question papers

Module 1: Number Systems and Codes

1. Perform operation using 2’s compliment method for decimal numbers:

i) 28-42 ii) 52-(-18)

2. Explain the following decimals in gray code form

a. (42)10 b. (17)10
3. Write (27)16 into its BCD code and Octal Code
4. Convert (118)10 in to BCD, Hexadecimal and Octal
5. Write (32)10 into its BCD and Ex-3 code
6. Write (AB) H into its BCD and Octal code

Module 2: Logic Gates and Combinational Logic Circuits

1. Compare TTL and CMOS logic families.


2. Give advantages and disadvantages of CMOS family.
3. Define Noise margin, Propagation delay, Power dissipation, Fan out, Fan in,
Figures of Merit.
4. State basic theorems of Boolean algebra.
5. State and prove De Morgan’s theorem.
6. Prove that NAND and NOR are Universal gates.
7. Implement Y = A +B C using only NOR gates.
8. Using Boolean Algebra prove :
a. AB+ BC + A C= AB+ A C
b. [ ⟨ C +C D ⟩ ⟨ C+C D ⟩ ] [ AB+ A B+( A XOR B) ]=C
c. A BC + A B C + ABC + AB C=AB + BC +CA
9. Minimize the following expression using Quine Mc-cluskey technique.
F(a,b,c,d) = ∑m(0,1,2,3,5,7,9,11)
10.Minimize the following expression using Quine Mc-cluskey technique.
F(a,b,c,d) = ∑m(0,2,5,7,8,10,12,15)
11.Minimize the following expression using Quine Mc-cluskey technique.
F(p,q,r,s) = ∑m(0,1,2,3,5,7,8,9,11,14)
12.Minimize the following expression using Quine Mc-cluskey technique.
F(p,q,r,s) = ∑m(0,1,3,7,8,9,15) + d(2,10,11)
13.Minimize the following expression using Quine Mc-cluskey technique.
F(p,q,r,s) = ∑m(1,2,5,7,9,15) + d(0,3,11)
14.Using Boolean Algebra prove :
d. AB+ BC + A C= AB+ A C
e. [ ⟨ C +C D ⟩ ⟨ C+C D ⟩ ] [ AB+ A B+( A XOR B) ]=C
15.Implement the following Boolean function using 8:1 multiplexer
F(A,B,C,D) = ∑m(0,1,4,5,6,8,10,12,13)
16.Implement the following Boolean function using 8:1 multiplexer
F(A,B,C,D) = ΠM(0,3,5,6,8,9,10,12,14)
17.Implement the following equation using single 4:1 MUX and few logic
gates: F(a,b,c,d) = ∑m(0,2,5,6,7,9,12,15)
18.Implement the following equation using single 4:1 MUX and few logic
gates: F(a,b,c,d) = ∑m(0,1,2,4,5,6,8,9,10,12,13,15)
19.Implement the following equation using single 4:1 MUX and few logic
gates: F(p,q,r,s) = ΠM(0,2,5,6,7,9,12,15)
20.Design a 4:1 multiplexer using only NAND gates.
21.Implement Full adder using 8:1 MUX.
22.Design a full adder using 3:8 Decoder.
23.Design full adder using half adders and logic gates.
24.Explain carry look ahead adder. What is its advantage over a simple adder?
25.Draw a neat circuit of BCD adder using IC 7483 and explain.
26.Implement full subtractor using two half subtractors
27.Design 2 bit comparator and implement using logic gates.
28.Design a 4 bit Binary to Grey code convertor.
29.Design a 4 bit Grey to Binary code convertor
30.State truth table of 3 bit Gray to Binary conversion and then design it using
3:8 decoder and additional gates.
31.Design an even parity generator with 3 data bits.
Module 3: Different Types of Memory

1. Explain or compare SRAM and DRAM.


2. Compare EPROM and FLASH memories

Module 4: Sequential Logic Circuits

1. Explain or compare Mealy and Moore machine.


2. Design a Mealy type sequence detector circuit to detect a sequence 1011
using D type flip flops.
3. Design a Mealy type sequence detector circuit to detect a sequence 1101
using T type flip flops.
4. Explain Master – Slave JK flip flop.
5. Convert JK flip flop to T flip flop.
6. Convert JK flip flop to D flip flop.
7. Convert T flip flop to D flip flop.
8. Convert SR flip flop to D flip flop.
9. Convert D flip flop T flip flop and SR flip flop to JK flip flop.
10.Compare synchronous counter with asynchronous counter.
11.Design ripple counter using JK flip flop for the state:
7→6→5→4→3→7
12.Design synchronous counter to count the sequence:
0 → 1 → 2 → 3 → 4 →5 → 0.
13.Design synchronous counter using D flip flops for getting the following
sequence: 0 → 3 → 1 → 5 → 6 → 0. Take care of lockout condition.
14.Design synchronous counter using T flip flops for getting the following
sequence: 0 → 2 → 4 → 6 → 0. Take care of lockout condition.
15.Design synchronous counter using T flip flops for getting the following
sequence: 1 → 2 → 3 → 4 → 5→ 6 →7→1.
16.Explain working of 3 – bit asynchronous counter with proper timing
diagram.
17.Explain Johnson’s Counter. Design for initial state 0110. From initial state
explain and draw all possible states.
18.Explain the working of 3 bit asynchronous counter with proper timing
diagram.
19.Compare combinational and sequential circuits.
20.What is shift register? Explain any one type of shift register. Give its
applications.
21.What is shift register? Explain any two modes of shift register.
22.What is universal shift register? Explain its various modes of operation.
23.Explain the working of Bidirectional Shift register with proper timing
diagram

Module 5: Programmable Logic Devices

1. Explain CPLD and FPGA.


2. Draw the block diagram of internal architecture of XC9500 family CPLD.
3. Draw the block diagram of internal architecture of XC4000 family FPGA.
4. Draw internal logic diagram of PLA.
5. Compare PLA with PAL.

Module 6: VHSIC Hardware Description Language (VHDL)

1. Write VHDL code for full adder


2. Write VHDL code for full Subtractor.
3. Write VHDL code for 3 bit up counter.
4. Write the VHDL code for 3-bit up-down counter with negative edge
triggered clock and active low Preset and Clear terminals.
5. Write the VHDL code for 2-bit up-down counter with posittive edge
triggered clock.
6. Write a VHDL program to design a 3:8 decoder.
7. Write a VHDL program to design 1:8 Demux using Data flow modeling.

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