A 6.38 fJ/conversion 0.6V 0.

43ȝW 100 kS/s 10-bit Successive Approximation ADC

Meng-Lieh Sheu and Cheng-Han Wu

Department of Electronics Engineering, National Chi-Nan University

#301, University Road, Puli
Nantou, 54561 Taiwan, R.O.C.
886+49+2910960 *4881, [email protected]

Abstract switch [5], as shown in Fig. 2, is used to supply the gate voltage of Ms
to 2·VDD+Vin. The simulated SNDR is 75.54dB which is well
This work presents a 10-bit successive approximation ADC for low enough for 10 bits resolution.
voltage and low power applications. The chip operating voltage is 0.6
V with single-ended rail-to-rail swing input signal. Binary-weighted B. Digital-to-analog converter
multilayer sandwich capacitor array is used in the digital to analog The DAC is constructed by binary-weighted capacitor array, as
converter employed in the ADC to reduce the overall capacitance shown in Fig. 3. A multi-layer sandwich capacitor [6], which can
value and power consumption effectively. The proposed ADC is efficiently reject the effect of parasitic capacitance, is employed to
designed with 0.18 ȝm CMOS process. The simulation results at 0.6 form the unit capacitance of about 2.44 fF with an area of 3.07 ȝm ×
V supply voltage, 100 kS/s sampling rate, and 1.38 kHz rail-to-rail 3.07 ȝm, as shown in Fig. 4. The total capacitance is reduced to
swing input, an SNDR of 60.4 dB is achieved with 0.43 ȝW power around 2.5 pF. The SAR switches the capacitor array through the
consumption. The FOM is 6.38 fJ per conversion step. inverters to connect the capacitor bottom plate to either VDD or GND.
Hence, the switching energy of capacitor is reduced by decreasing the
Key words: SAR ADC, rail-to-rail, low voltage, low power total capacitance.

Introduction C. Comparator
The comparator compares the Vdac with a reference voltage of
The demand of analog to digital converters (ADCs) with low power VDD/2, as shown in Fig. 5 [7]. Transistor pair M5 and M6 as a latch
consumption and low voltage operation has increased drastically due improves the operation speed. Transistors M4 and M7 reset Vout to
to the needs in implantable and wearable applications. Successive low as clk is low. Transistors M8-M11 form inverters for output
approximation register (SAR) ADCs with medium-speed/resolution buffering.
and lower power consumption become the competitive choice in
these applications [1]. D. SAR/Latch and Clock/Reset
Intuitively, lowering the operation voltage is the simple way to The non-redundant successive approximation register, as shown in
achieve low power consumption, but it will confront the inevitable Fig. 6, is adopted to reduce the number of registers as well as the
problem of low signal swing in analog circuit design. The primary power consumption [5]. As a conversion is finished, the converted
power consumption of SAR ADCs is contributed from the comparator, results in SAR will be transferred to the output Latch for exporting.
DAC, and SAR control logic. Many research works have focused on The clock/reset circuit and its simulated waveforms are shown in Fig.
the reduction of switching energy loss in DAC [2-4]. Among these 7.
works, decreasing the unit capacitance and thus the total capacitance
of the DAC capacitor array can efficiently reduce the power Simulation Results
consumption and chip area.
In this paper we present a low voltage and low power rail-to-rail The 10-bit SAR ADC is designed with 1P6M 0.18 ȝm CMOS
input 10-bit SAR ADC chip. The chip is designed in TSMC 0.18 ȝm process. The simulated results are summarized in Table I. The
1P6M CMOS process. The chip operates in 0.6 V power supply and differential nonlinearity (DNL) and integral nonlinearity (INL) of the
1.2 MHz clock frequency. The simulated signal-to-noise-distortion SAR ADC are -0.38/+0.37 LSB and -0.41/+0.38 LSB at 100 kS/s
ratio (SNDR) is 60.4 dB at 100 kS/s sampling rate with power sampling rate and 0.6 V power supply voltage, respectively. The
consumption of 0.43 ȝW. The figure of merit (FOM) is 6.38 fJ per SNDR and ENOB are 60.40 dB and 9.74 bits for 1.38 kHz input,
conversion step, which is very good compared to those existing works respectively. The power consumption less than 0.43ȝW results a
implemented in 0.18 ȝm process. FOM of 6.38 pJ/conversion-step. Table II compares the proposed
SAR-ADC with some other works. Our work has lower power
ADC Architecture consumption and smaller FOM.

The proposed ADC architecture, as shown in Fig. 1, comprises of Summary

track-and-hold (T/H), digital-to-analog convertor, comparator, SAR,
latch and reset circuits. The input accepts single-ended rail-to-rail In this paper, a 10-bit SAR ADC fabricated in 0.18 ȝm CMOS
signal without the need of rail-to-rail operation comparator, hence it process for low power and low voltage applications is presented. The
can achieve 10-bit resolution under low voltage operation. Besides, measured SNDR of the ADC is 52.95 dB at 200 kS/s sampling rate
the MOS switches in DAC capacitor array can be realized simply by and 1 kHz input frequency. An FOM of 22.4 fJ/conversion is
digital inverter. achieved with power consumption of 1.624 ȝW at 0.7 V power supply
voltage. The active core of proposed SAR ADC occupies an area of
A. Bootstrapped track-and-hold 201 ȝm × 180 ȝm. Compared with some recent works in 0.18 ȝm
Since the operation voltage is 0.6 V in this work, to lower the CMOS process, our work has the minimum core area with
conducting resistance of the sampling transistor, Ms, and achieve the competitive power consumption and FOM
rail-to-rail input sampling, a track-and-hold circuit with bootstrap
 Table I Chip Summary.

Fig. 1 Proposed 10-bit SAR ADC

Table II Comparison with other works.

Fig. 2 Bootstrapped track and hold

Fig. 3 Binary-weighted capacitor array DAC

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