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SLMD Example

This document contains SystemC code that was generated from Verilog code using a Verilog to SystemC conversion tool. It includes code for modules that implement multiplexers (muxes) with 2 or 4 inputs. Testbenches are also generated to simulate the mux modules. The code defines the mux modules with input and output ports, and instantiates the modules in a main function with signals connected to the ports for simulation.

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ghazella
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© © All Rights Reserved
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54 views6 pages

SLMD Example

This document contains SystemC code that was generated from Verilog code using a Verilog to SystemC conversion tool. It includes code for modules that implement multiplexers (muxes) with 2 or 4 inputs. Testbenches are also generated to simulate the mux modules. The code defines the mux modules with input and output ports, and instantiates the modules in a main function with signals connected to the ports for simulation.

Uploaded by

ghazella
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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#include "mux_4to1_gates.

hxx"
int sc_main(int argc , char *argv[] )
{
sc_signal< sc_logic >t_a;
sc_signal< sc_logic >t_b;
sc_signal< sc_logic >t_c;
......................................
......................................
......................................
sc_signal< sc_lv< 2 > >t_sel;
sc_signal< sc_logic >t_y;
mux_4to1_gates inst_mux_4to1_gates("mux_4to1_gates" );
inst_mux_4to1_gates.a( t_a);
inst_mux_4to1_gates.b( t_b);
......................................
......................................
......................................
inst_mux_4to1_gates.d( t_d);
inst_mux_4to1_gates.sel( t_sel);
inst_mux_4to1_gates.y( t_y);
sc_start(1000,SC_NS);
return 0;
}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:08 PM
//
//
#include "systemc.h"
#include "mux_4to1_gates.hxx"
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:08 PM
//
//
#include "systemc.h"
SC_MODULE(mux_2to1_gates)
{
......................................
......................................
......................................
sc_in< sc_logic > mux_2to1_gates_dummy_port_2;
sc_in< sc_logic > mux_2to1_gates_dummy_port_3;
sc_inout< sc_logic > mux_2to1_gates_dummy_port_4;
SC_CTOR( mux_2to1_gates )
{
......................................
......................................
......................................
};
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:08 PM
//
//
#include "systemc.h"
#include "mux_2to1_gates.hxx"
SC_MODULE(mux_4to1_gates)
{
......................................
......................................
......................................
sc_in< sc_logic > b;
sc_in< sc_logic > c;
sc_in< sc_logic > d;
sc_in< sc_lv< 2 > > sel;
sc_out< sc_logic > y;
......................................
......................................
......................................
sc_signal< sc_logic > mux_2;
mux_2to1_gates U_mux1;
sc_signal< sc_logic > U_mux1_mux_2to1_gates_dummy_port_1;
sc_signal< sc_logic > U_mux1_mux_2to1_gates_dummy_port_2;
sc_signal< sc_logic > U_mux1_mux_2to1_gates_dummy_port_3;
......................................
......................................
......................................
void assign_U_mux1_ports_1613424566()
{
while(true)
{
U_mux1_mux_2to1_gates_dummy_port_1 = ( sc_logic ) ( a.read() );
......................................
......................................
......................................
U_mux1_mux_2to1_gates_dummy_port_3 = ( sc_logic ) ( sel.read()[0] );
sc_logic tmp_var_1202653598 = (sc_logic)mux_1.read();
tmp_var_1202653598 = ( sc_logic )U_mux1_mux_2to1_gates_dummy_port_4.read();
mux_1 = tmp_var_1202653598;
wait();
......................................
......................................
......................................
}
mux_2to1_gates U_mux2;
sc_signal< sc_logic > U_mux2_mux_2to1_gates_dummy_port_1;
sc_signal< sc_logic > U_mux2_mux_2to1_gates_dummy_port_2;
sc_signal< sc_logic > U_mux2_mux_2to1_gates_dummy_port_3;
......................................
......................................
......................................
void assign_U_mux2_ports_1880052106()
{

#include "mux_2to1_gates.hxx"
int sc_main(int argc , char *argv[] )
{
sc_signal< sc_logic >t_a;
sc_signal< sc_logic >t_b;
sc_signal< sc_logic >t_sel;
......................................
......................................
......................................
mux_2to1_gates inst_mux_2to1_gates("mux_2to1_gates" );
inst_mux_2to1_gates.a( t_a);
inst_mux_2to1_gates.b( t_b);
inst_mux_2to1_gates.sel( t_sel);
inst_mux_2to1_gates.y( t_y);
......................................
......................................
......................................
return 0;
}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:16 PM
//
//
#include "systemc.h"
SC_MODULE(mux_2to1_gates)
{
......................................
......................................
......................................
sc_in< sc_logic > b;
sc_in< sc_logic > sel;
sc_out< sc_logic > y;
sc_signal< sc_logic > inv_sel;
sc_signal< sc_logic > asel;
......................................
......................................
......................................
SC_CTOR( mux_2to1_gates )
{
nullnullnullnull }
};
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:16 PM
//
//
#include "systemc.h"
#include "mux_2to1_gates.hxx"

#include "mux_2to1_gates_tb.hxx"
int sc_main(int argc , char *argv[] )
{
mux_2to1_gates_tb inst_mux_2to1_gates_tb("mux_2to1_gates_tb" );
sc_start(1000,SC_NS);
return 0;
}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:19 PM
//
//
#include "systemc.h"
#include "mux_2to1_gates.hxx"
SC_MODULE(mux_2to1_gates_tb)
{
......................................
......................................
......................................
sc_signal< sc_logic > b;
sc_signal< sc_logic > sel;
sc_signal< sc_logic > y;
void initial_stmt_at_line_52_1845137754();
mux_2to1_gates uut;
......................................
......................................
......................................
sc_signal< sc_logic > uut_b;
sc_signal< sc_logic > uut_sel;
sc_signal< sc_logic > uut_y;
void assign_uut_ports_2013613908()
{
......................................
......................................
......................................
{
uut_a = ( sc_logic ) ( a.read() );
uut_b = ( sc_logic ) ( b.read() );
uut_sel = ( sc_logic ) ( sel.read() );
uut_y = ( sc_logic ) ( y.read() );
......................................
......................................
......................................
}
}
SC_CTOR( mux_2to1_gates_tb ) : uut("mux_2to1_gates" )
{
uut.a(uut_a);
......................................
......................................
......................................
uut.sel(uut_sel);
uut.y(uut_y);
SC_THREAD(assign_uut_ports_2013613908);
sensitive<< a;
sensitive<< b;
......................................
......................................
......................................
sensitive<< y;
SC_THREAD( initial_stmt_at_line_52_1845137754 );
}
};
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// //
// This SystemC file has been generated by the verilog2sc //
// tool. //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//
//
//
// Generated by : apache on 6/15/20 9:19 PM
//
//
#include "systemc.h"
SC_MODULE(mux_2to1_gates)
{
......................................
......................................
......................................
sc_inout< sc_logic > b;
sc_inout< sc_logic > sel;
sc_inout< sc_logic > y;
SC_CTOR( mux_2to1_gates )
{
......................................
......................................
......................................
};

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