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Alpha Mpu Project: General Information

The document describes the instruction fetch unit of the Alpha 21264 processor. It discusses the key components of the fetch unit including a 64KB two-way instruction cache that can supply four instructions per cycle, next-fetch and set predictors that eliminate bubbles, and a tournament branch predictor that selects between local and global history to minimize mispredictions. The fetch unit is able to speculatively fetch up to 20 branch predictions to maintain a continuous instruction stream.

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74 views5 pages

Alpha Mpu Project: General Information

The document describes the instruction fetch unit of the Alpha 21264 processor. It discusses the key components of the fetch unit including a 64KB two-way instruction cache that can supply four instructions per cycle, next-fetch and set predictors that eliminate bubbles, and a tournament branch predictor that selects between local and global history to minimize mispredictions. The fetch unit is able to speculatively fetch up to 20 branch predictions to maintain a continuous instruction stream.

Uploaded by

prathap13
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Alpha Mpu Project

Title: Instruction Fetch unit

Author: Prathap

Date: 8/1/11

1. INTRODUCTION:
2. General information
[Ev6] 3rd Generation Cpu
600 MHz operation in 0.35u CMOS
RISC Architecture
30+ Performance levels
3. Architectural Techniques:
Out-of-order and speculative execution
4-way integer issue
2-way floating-point issue
Sophisticated tournament branch prediction
High-bandwidth memory system
4. Goal:
Performance leadership through unique combination of advance
circuit and architectural techniques.

 In the first turn we are looking in to the Architectural Techniques of Alpha


21264 processor.
 Stages of Micro-Architectural Techniques
Stage 0  Fetch unit ( 4 inst/cycle from inst. Cache)
Stage 1  Bifurcates & assigns
Stage 2  Rename(map) , allocates inst.virtual register to physical
registers
Stage 3  Issue, out-of-order
Stage 4  Execution
2. FETCH UNIT:
The block diagram describes the highlighted Fetch unit:

 Enablers
 The 64 KB two-way associative instruction cache supplies
Four instructions every cycle
 The next-fetch and set predictors provide the fast cache access
times of a direct-mapped cache and eliminate bubbles in
nonsequential control flows
 The instruction fetcher speculates through up to 20 branch predictions
to supply a continuous stream of instructions
 The tournament branch predictor dynamically selects between Local
and Global history to minimize mispredicts.

 Instruction stream:
The general overall explanation can be understand from following
diagram
 Fetch stage:
The fetch depends on two co-relations either local or global correlation.

The tournament Branch prediction dynamically chooses between global or


local history to predict the direction of a given Branch.

 Tournament Branch predictor:


 Instruction Fetch logic:
 Up to four aligned instructions are fetched from the Icache, in program
order.
 The branch prediction tables are also accessed in this cycle( instruction fetch
cycle or Stage 0).
 The branch predictor uses tables and a branch history algorithm to predict a
branch instruction target address for one branch.
 Branch prediction and line prediction bits accompany the four instructions.
 In the slot stage(stage1), the branch predictor compares the next Icache
index that it generates to the index that was generated by the line predictor.
 If there is a mismatch, the branch predictor wins and results in one
bubble(cycle delay).
 The line predictor takes precedence over the branch predictor during
memory format calls or jump.

 ICACHE:
 Large 64 k byte, two-way set associative instruction cache.
 Each fetch block of four instructions includes a line and set prediction.
 Prediction indicates where to fetch the next block of instructions from,
including which set should be used.
 Remove the bubble if the branch is predicted to be taken by the branch
predictor.
 On cache fills, the line predictor value at each fetch line is initialized with
the index of the next sequential fetch line, and later retrained by the
branch predictor if necessary.
 The line predictor does not train on every mispredict.
 The mispredict cost is typically a single cycle bubble.
 Line predictor is also trained for jumps that use direct register addressing.
 Things still to be explored:
 Training algorithms
 Saturated calculation

 Things identified to do:


 To write detail specification of Fetching unit for systemc
 By next week , finish specification.
 Start the coding in systemc.

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