College of Engineering, Science and Technology (CEST)

EEE743 CONTROL
SYSTEMS
Final Examination
Tuesday 17th June, 2014 1400 - 1710 hours Venue: B314

INSTRUCTIONS TO CANDIDATES
1. Candidates are reminded that they should have no books, notes, paper or other
material in their possession unless their use is specifically permitted by “Instructions
to Candidates” set out below.
2. Reading time is of 10 minutes duration.

3. Examination time is of 3 hours duration.

4. This paper consists of 8 questions printed on 8 pages.

5. Attempt all 7 questions. Each question may carry a different mark.

6. A set of Laplace Transforms Table is attached.

7. The datasheet for the 74LS153 Multiplexer is on page 3.

8. Write your candidate number at the top of each attached sheet.

9. Start each question on a new page.

10. Non-Programmable Calculators may be used.

11. Mobile phones are not allowed inside the examination venue.
 EEE743 Examination Paper

QUESTION 1: FIRST ORDER RC & RL NETWORKS [TOTAL: 14 MARKS]

(a) The 1st Order RC circuit in Figure 1 has zero initial conditions. The switch S1 is closed
at time t = 0.

t=0
R
S1 8R

+
V 40V C
1/16F
-

Figure 1: 1st Order RC network

(i) Determine the solution, q(t), by applying Kirchoff’s Voltage Law (KVL) and
using conventional Calculus. Identify the Steady State and the Transient
State. [5 marks]

(ii) Resolve for q(t) using Laplace Transforms. [4 marks]

(iii) Derive the expression for the instantaneous current, i(t). [2 marks]

5
(iv) Given the step response of a 1st Order System, C (s ) = , use the
s (s + 2 )
method of Poles & Zeros to determine time-domain response. [3 marks]

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 EEE743 Examination Paper

QUESTION 2: SECOND ORDER SYSTEMS & SERIES RLC NETWORK [TOTAL: 15 MARKS]

(a) Given an Underdamped system, find the following if the Transfer Function is

36
G(s) = 2
s + 9s + 36

(i) Peak time (Tp) [4 marks]

(ii) Percentage Overshoot [3 marks]

(iii) Settling time (Ts) [2 marks]

(b) Refer to the Series RLC circuit shown in Figure 2. The output is taken across the
capacitor, C. Use Laplace Transforms to derive the solution of q(t). Assume zero initial
conditions. [6 marks]

t =0 L

2H

+
Vi 24V R 18
- Vo(t)

1/28 F

Figure 2: Series RLC circuit

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 EEE743 Examination Paper

QUESTION 3 : ROOT LOCUS [TOTAL: 12 MARKS]

Consider the system shown in Figure 3.

Figure 3: A 2nd Order System

(a) Derive the Characteristic Equation in quadratic form. [3 marks]

(b) Sketch the Root Locus. [Hint: Obtain roots for k = 0, 4, 8, 12, 16, 20] [5 marks]

(c) Find the value(s) of k that make the system overdamped, but will keep the system
stable. [4 marks]

QUESTION 4: LAPLACE TRANSFORMS; UNIT STEP FUNCTION [TOTAL: 12 MARKS]

(a) Determine the s-domain equivalents of the following functions using the given table of
Laplace Transform.

(i) f (t ) = −7 cos 4t + 3e 2t − 5t 3 [2 marks]

(ii) f (t ) = 2e 3t sin 5t [2 marks]

(t − 5)3 , t > 5

(iii) f (t ) =   = u (t − 5)(t − 5)
3

 0, t < 5
[2 marks]

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 EEE743 Examination Paper

(b) Sketch the functions,

(i) f (t ) = 4[u (t ) − u (t − 3)] [2 marks]

 π
(ii) f (t ) = u  t −  cost , 0 ≤ t ≤ 2π
 2 [2marks]

(iii) f (t ) = u (t ).t 2 , f (t + 2) = f (t ); 0 ≤ t ≤ 6
[2marks]

QUESTION 5 : SIGNAL CONDITIONING [TOTAL: 12 MARKS]

(a) Consider a 4-bit DAC using an op-amp summing amplifier with binary-weighted
resistors as shown in Figure 4.

R1
1k
D Rf
MSB R2 1k
2k
C
Digital inputs: R3 +
0V or 5V 4k Vo
B
R4
8k
A
LSB
[5 marks]
Figure 4: 4-bit DAC

Determine the step size (resolution) and find the output voltages for all the
combinations of the input code, from DCBA = 0000 to 1111. Tabulate your results as
shown in Table 1:

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 EEE743 Examination Paper

D C B A Vout (v)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 1: DAC Table

(b) Describe concisely how the ADC illustrated in Figure 5 operates. [5 marks]

Figure 5: ADC

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 EEE743 Examination Paper

(c) Refer to Table 1, showing the Function Table for the Full Adder (Binary Adder).
Design a circuit using the 74LS153 Multiplexer to implement the Sum (S) and the
Carry Out (Cout). Both outputs S and Cout are to be present at any time. (Note:
Datasheet for 74LS153 is provided).

Table 2: Binary Adder

A B K S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

[5 marks]

QUESTION 6 [FOURIER SERIES, NOISE, BANDWIDTH] [TOTAL: 20 MARKS]

(a) Analyse the current pulse train shown.

(i) Determine the amplitude and frequency of the fundamental and harmonic
content through the first seven harmonics. The pulse train represents the
20, 0 ≤ t < 2
(t ) = 
function, ii(t) ; i (t + 4) = i(t )
 0, 2 ≤ t < 4

20A

t(s)
0 2 4 6 8 10

[5 marks]

(ii) Predict the amplitude and the frequency for the term when n = 13. [2 marks]

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 EEE743 Examination Paper

(b) A communication equipment with a gain of 120 and a bandwidth of 2 MHz has an input
resistance of 8 kΩ. It is operating at a temperature of 27 °C and receives an input audio
signal of 6 uVrms. Given Boltzmann’s constant is 1.38 x 10-23 J/K, calculate the following

(i) White [Johnson] Noise Power [2 marks]

(ii) RMS input noise level [2 marks]

(iii) Audio output level [2 marks]

(iv) RMS output noise level [2 marks]

(b) The bandwidth, B, of the PSTN is 4 kHz.

(i) Assume a noiseless environment and use the Nyquist (Hartley) equation,
C = 2 B log 2 M , to resolve for the Maximum Data Transfer Rate (Capacity).
There are 16 signalling levels. [2 marks]

(ii) If the S/N ratio is 50 dB, determine the maximum information rate, C,
 S
predicted by Shannon’s law, C = B log 2 1 +  . [3 marks]
 N

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 EEE743 Examination Paper

QUESTION 7 OPERATIONAL AMPLIFIERS – ANALOGUE COMPUTERS [TOTAL: 10 MARKS]

Design an Analogue Computer using Operational amplifiers to solve the second order
differential equation, v ′′ = 5v′ − v + 4 cos10t . Use integrators whose time constant RC = 1.
Assume the initial conditions v’(0) = 0 and v”(0) = 2 V. Provide a block diagrammatic
representation of the circuit first. State any assumptions you make. Do note the General
Add-Subtract circuit shown in
Figure 6, and the parameters that need to be evaluated.

[10 marks]

Figure 6: General Add-Subtract circuit

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 EEE743 Examination Paper

QUESTION 8: PARALLEL RLC NETWORK [TOTAL: 12 MARKS]

(a) Analyse the Parallel RLC network shown.

iR iL iC
is(t)
R 8 L 2H C + 5F Vo(t)

Figure 7: Parallel RLC network

(i) Analyse the network and derive the mathematical model in the s-domain. Assume
zero initial conditions. [4 marks]

(ii) Construct the block diagram of the network, then reduce it to its simplest Closed-loop
form using the block reduction technique. [4 marks]

(iii) Find the Closed-loop Transfer Function. Represent this via a block diagram. [4 marks]

[THE END]

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