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    HW 5 Updated

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    This document outlines 3 homework problems for an electrical engineering course. Problem 1 involves designing and simulating a NMOS domino logic circuit. Problem 2 involves constructing and simulating a dynamic NMOS gate circuit. Problem 3 involves analyzing signal propagation in high-speed interconnects, including calculating characteristic impedance, time delay, and simulating transmission line effects.

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    HW 5 Updated

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    ottopor
    39 views1 page
    This document outlines 3 homework problems for an electrical engineering course. Problem 1 involves designing and simulating a NMOS domino logic circuit. Problem 2 involves constructing and simulating a dynamic NMOS gate circuit. Problem 3 involves analyzing signal propagation in high-speed interconnects, including calculating characteristic impedance, time delay, and simulating transmission line effects.

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    This document outlines 3 homework problems for an electrical engineering course. Problem 1 involves designing and simulating a NMOS domino logic circuit. Problem 2 involves constructing and simulating a dynamic NMOS gate circuit. Problem 3 involves analyzing signal propagation in high-speed interconnects, including calculating characteristic impedance, time delay, and simulating transmission line effects.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    39 views1 page

    HW 5 Updated

    Uploaded by

    ottopor
    This document outlines 3 homework problems for an electrical engineering course. Problem 1 involves designing and simulating a NMOS domino logic circuit. Problem 2 involves constructing and simulating a dynamic NMOS gate circuit. Problem 3 involves analyzing signal propagation in high-speed interconnects, including calculating characteristic impedance, time delay, and simulating transmission line effects.

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    © All Rights Reserved
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    Download as docx, pdf, or txt
    of 1

    Homework #5

    EE457

    Due Date: April 18, 2016


    140 points maximum. Each part is worth 10 pts.

    Problem 1 (25 points)


    a) Using Electric, design a NMOS domino logic circuit for F=AB+CD + AC using 2-
    input OR and AND gates. Do not simplify.
    b) Layout in Electric. Run DRC check.
    c) Make clock signal to cover the D input during the evaluate mode.
    d) Do IRSim analysis of the layout. Put A=0, B=0, C=1 and D shown below.

    0 5ns 10ns 20ns 25ns 35ns 40ns time


    Timing Diagram for D Input

    Problem 2: (50 points)

    Construct a dynamic NMOS gate for the function f =x⋅y +x⋅( z +w ). Do not simplify.
    a) Draw a circuit schematic in Electric.
    b) Provide a layout of the circuit using Electric. Use clock signal of 2GHz for LTSPICE.
    c) Put Cload=5pF for the output capacitor and run LTSPICE with x=1, z=1 and w=1. The signal y
    has clock pulse of 500MHz. Only print out 3 cycles.
    d) Now try Cload = 1fF and run the same LTSPICE as in part c). Did you observe any differences in
    your output waveform? Only print out 3 cycles.
    e) Use IRSIM and provide the output waveform by creating your own input signals.

    Problem 3: (25 points)

    Assume that you are a design engineer and at a leading semiconductor company. You are requested to
    analyze high-speed signals on a newly developed chip on a silicon substrate. Assume that all fabrication is
    done through a conventional CMOS batch process. You are to analyze a signal interconnect length of 750
    um with width of 75 um and thickness of 10um. The interconnect is made of aluminum. Calculate the
    following:

    1) Find R, L and C if the oxide layer is 50 angstroms. Calculate characteristic impedance.


    2) Find time of flight delay on a silicon substrate.
    3) Assume a digital pulse goes through the 1000um long copper interconnect with 5GHz and rise
    and fall time of 1ps. Determine if the transmission line effect should be considered. Provide
    reasons.
    4) Using LTSPICE, provide simulation of a lossy distributed line (RLC) with 10 stages. Provide
    output pulse waveforms with 50 Ohm load. Use input pulse waveform of 5GHz with 5 volts. Use
    per unit values of 2ohms/um, 1pH/um and 5fF/um. Provide only 3 cycles of the waveform.
    5) Now run the same simulation as in part 4) with 20 Ohm load and provide the output waveforms
    for 3 cycles. What did you observe?

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