Off-Line PWM Controllers with Integrated Power MOSFET

STR3A100 Series

General Descriptions Package

The STR3A100 series are power ICs for switching
power supplies, incorporating a MOSFET and a current DIP8
mode PWM controller IC.
The low standby power is accomplished by the
automatic switching between the PWM operation in
normal operation and the burst-oscillation under light
load conditions. The product achieves high
cost-performance power supply systems with few Not to Scale
external components.

Lineup
Features  Electrical Characteristics
 Low Thermal Resistance Package VDSS(MIN) OVP
 Current Mode Type PWM Control Products fOSC(AVG)
(max.) /TSD
 Soft Start Function STR3A1×× 67 kHz 650 V
Latched
 No Load Power Consumption < 15mW shutdown
 Auto Standby Function Auto
STR3A1××D 67 kHz 650 V
Normal Operation ----------------------------- PWM Mode restart
Standby ---------------------------- Burst Oscillation Mode Auto
STR3A1××HD 100 kHz 700 V
restart
 Random Switching Function
 Slope Compensation Function
 MOSFET ON Resistance and Output Power, POUT*
 Leading Edge Blanking Function POUT POUT
 Bias Assist Function RDS(ON) (Adapter) (Open frame)
Products
 Protections (max.) AC85 AC85
AC230V AC230V
・Two Types of Overcurrent Protection (OCP); ~265V ~265V
Pulse-by-Pulse, built-in compensation circuit to fOSC(AVG) = 67 kHz
minimize OCP point variation on AC input voltage STR3A151
・Overload Protection (OLP); auto-restart 4.0 Ω 29.5 W 19.5 W 37 W 23 W
STR3A151D
・Overvoltage Protection (OVP); latched shutdown or
auto-restart STR3A152
3.0 Ω 33 W 23.5 W 45 W 29 W
・Thermal Shutdown Protection (TSD); latched STR3A152D
shutdown or auto-restart STR3A153
1.9 Ω 37 W 27.5 W 53 W 35 W
STR3A153D
Typical Application Circuit STR3A154
1.4 Ω 41 W 31 W 60 W 40 W
STR3A154D
L51
BR1 D51 VOUT
T1
VAC STR3A155
R54 1.1 Ω 45 W 35 W 65 W 44 W
C1
C5 R1
PC1 R51 STR3A155D
P
C51 R55
D1 S R52 C53 fOSC(AVG) = 100 kHz
C52 R53 STR3A161HD 4.2 Ω 25 W 20 W 36 W 24 W
U2
3.2 Ω
8 7 6 5

D/ST D/ST D/ST

NC D/ST
D2 R2
R56
STR3A162HD 28 W 23 W 40 W 28 W
C4 U1
STR3A100
C2 D
GND STR3A163HD 2.2 Ω 32 W 25.5 W 46 W 33.5 W
S/OCP VCC GND FB/OLP * The output power is based on the thermal ratings, and the peak
1 2 3 4 output power can be 120 to 140 % of the value stated here. At low
output voltage, small core and short ON Duty, the output power
ROCP C3 may be less than the value stated here.
PC1 CY

Applications
 Low power AC/DC adapter
 White goods
 Auxiliary power supply
 Other SMPS

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STR3A100 Series

CONTENTS
General Descriptions ----------------------------------------------------------------------- 1
1. Absolute Maximum Ratings --------------------------------------------------------- 3
2. Electrical Characteristics ------------------------------------------------------------ 4
3. Performance Curves ------------------------------------------------------------------ 6
3.1 Derating Curves --------------------------------------------------------------- 6
3.2 MOSFET Safe Operating Area Curves ---------------------------------- 6
3.3 Ambient Temperature versus Power Dissipation Curves ------------ 8
3.4 Transient Thermal Resistance Curves ----------------------------------- 8
4. Functional Block Diagram ---------------------------------------------------------- 10
5. Pin Configuration Definitions ------------------------------------------------------ 10
6. Typical Application Circuit -------------------------------------------------------- 11
7. Package Outline ----------------------------------------------------------------------- 12
8. Marking Diagram -------------------------------------------------------------------- 12
9. Operational Description ------------------------------------------------------------- 13
9.1 Startup Operation ----------------------------------------------------------- 13
9.2 Undervoltage Lockout (UVLO) ------------------------------------------- 13
9.3 Bias Assist Function --------------------------------------------------------- 13
9.4 Soft Start Function ---------------------------------------------------------- 14
9.5 Constant Output Voltage Control ---------------------------------------- 14
9.6 Leading Edge Blanking Function ---------------------------------------- 15
9.7 Random Switching Function ---------------------------------------------- 15
9.8 Automatic Standby Mode Function-------------------------------------- 15
9.9 Overcurrent Protection Function (OCP) ------------------------------- 15
9.10 Overload Protection Function (OLP) ----------------------------------- 16
9.11 Overvoltage Protection (OVP) -------------------------------------------- 17
9.12 Thermal Shutdown Function (TSD) ------------------------------------- 17
10. Design Notes --------------------------------------------------------------------------- 18
10.1 External Components ------------------------------------------------------- 18
10.2 PCB Trace Layout and Component Placement ----------------------- 19
11. Pattern Layout Example ------------------------------------------------------------ 21
12. Reference Design of Power Supply ----------------------------------------------- 22
OPERATING PRECAUTIONS -------------------------------------------------------- 24
IMPORTANT NOTES ------------------------------------------------------------------- 25

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1. Absolute Maximum Ratings

 The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
 Unless otherwise specified TA = 25 °C, 5 pin = 6 pin = 7 pin = 8 pin

Parameter Symbol Test Conditions Pins Rating Units Notes

3A151 / 51D
3.6 / 61HD
3A152 / 52D
4 / 62HD
4.8 3A163HD
Drain Peak Current(1) IDPEAK Single pulse 8–1 A
5.2 3A153 / 53D
6.4 3A154 / 54D
7.2 3A155 / 55D
ILPEAK = 2.13 A 53 3A151 / 51D
ILPEAK = 2.19 A 56 3A152 / 52D
ILPEAK = 2.46 A 72 3A153 / 53D
ILPEAK = 2.66 A 83 3A154 / 54D
Avalanche Energy(2)(3) EAS 8–1 mJ
ILPEAK = 3.05 A 110 3A155 / 55D
ILPEAK = 1.43 A 23.8 3A161HD
ILPEAK = 1.58 A 29 3A162HD
ILPEAK = 1.88 A 41 3A163HD
S/OCP Pin Voltage VS/OCP 1−3 − 2 to 6 V
VCC Pin Voltage VCC 2−3 32 V
FB/OLP Pin Voltage VFB 4−3 − 0.3 to 14 V
FB/OLP Pin Sink Current IFB 4−3 1.0 mA
3A151 / 51D / 52
1.68 / 52D / 61HD
MOSFET Power / 62HD
(5)
PD1 8–1 W 3A153 / 53D / 54
Dissipation(4) 1.76 / 54D / 63HD
1.81 3A155 / 55D
Control Part Power
PD2 2–3 1.3 W VCC×ICC
Dissipation
Operating Ambient
TOP ― − 40 to 115 °C
Temperature
Storage Temperature Tstg ― − 40 to 125 °C
Junction Temperature Tch ― 150 °C

(1)
Refer to Figure 3-1 SOA Temperature Derating Coefficient Curve
(2)
Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve
(3)
Single pulse, VDD = 99 V, L = 20 mH
(4)
Refer to Section 3.3 Ta-PD1 Curve
(5)
When embedding this hybrid IC onto the printed circuit board (cupper area in a 15 mm × 15 mm)

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2. Electrical Characteristics
 The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
 Unless otherwise specified, TA = 25 °C, VCC = 18 V, 5 pin = 6 pin = 7 pin = 8 pin, VFB = 3 V, VD/ST = 10 V
Test
Parameter Symbol Pins Min. Typ. Max. Units Notes
Conditions
Power Supply Startup Operation
Operation Start Voltage VCC(ON) 2−3 13.8 15.3 16.8 V
(1)
Operation Stop Voltage VCC(OFF) 2−3 7.3 8.1 8.9 V
Circuit Current in Operation ICC(ON) VCC= 12V 2−3 − − 2.5 mA
Startup Circuit Operation
VST(ON) 8−3 − 40 − V
Voltage
Startup Current ISTARTUP VCC= 13.5V 2−3 − 3.9 − 2.5 − 1.1 mA
Startup Current Biasing
VCC(BIAS) 2−3 8.5 9.5 10.5 V
Threshold Voltage
PWM Operation
3A15×
Average PWM Switching 60 67 74 3A15×D
fOSC(AVG) 8−3 kHz
Frequency 90 100 110 3A16×HD
3A15×
PWM Frequency Modulation − 5 − 3A15×D
Δf 8−3 kHz
Deviation
− 8 − 3A16×HD
3A15×
65 74 83 % 3A15×D
Maximum ON Duty DMAX 8−3
77 83 89 % 3A16×HD

Protection Function
3A15×
− 350 − 3A15×D
Leading Edge Blanking Time tBW − ns
− 280 − 3A16×HD
3A15×
OCP Compensation − 17 −
DPC − mV/μs 3A15×D
Coefficient
− 27 − 3A16×HD

OCP Compensation ON Duty DDPC − − 36 − %

OCP Threshold Voltage at
VOCP(L) 1−3 0.69 0.78 0.87 V
Zero ON Duty
OCP Threshold Voltage at
VOCP(H) 1−3 0.79 0.88 0.97 V
36% ON Duty
Maximum Feedback Current IFB(MAX) 4−3 − 110 − 70 − 35 µA
Minimum Feedback Current IFB(MIN) 4−3 − 30 − 15 −7 µA
3A151 / 51D
/ 52 / 52D / 53
FB/OLP pin Oscillation Stop 1.09 1.21 1.33 / 53D / 61HD
VFB(OFF) VCC=32V 4−3 V / 62HD / 63HD
Threshold Voltage
3A154 / 54D
0.85 0.98 1.09 / 55 / 55D
OLP Threshold Voltage VFB(OLP) VCC= 32V 4−3 7.3 8.1 8.9 V
OLP Operation Current ICC(OLP) VCC= 12V 2−3 − 230 − µA
OLP Delay Time tOLP − 54 70 86 ms

(1)
VCC(BIAS) > VCC(OFF) always.

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Test
Parameter Symbol Pins Min. Typ. Max. Units Notes
Conditions
FB/OLP Pin Clamp Voltage VFB(CLAMP) 4−3 11.0 12.8 14.0 V
OVP Threshold Voltage VCC(OVP) 2−3 27.5 29.5 31.5 V
Thermal Shutdown Operating
Tj(TSD) − 135 − − °C
Temperature
MOSFET
3A15×
Drain-to-Source Breakdown 650 − − 3A15×D
VDSS 8–1 V
Voltage 700 − − 3A16×HD
Drain Leakage Current IDSS 8–1 − − 300 μA
− − 4.2 3A161HD

− − 4.0 3A151 / 51D

− − 3.2 3A162HD

− − 3.0 3A152 / 52D

On Resistance RDS(ON) IDS = 0.4A 8−1 Ω
− − 2.2 3A163HD
− − 1.9 3A153 / 53D

− − 1.4 3A154 / 54D

− − 1.1 3A155 / 55D

Switching Time tf 8–1 − − 250 ns

Thermal Resistance
Channel to Frame θch-F − − − 16 °C/W
3A151 / 51D
/ 52 / 52D / 53
Channel to Case Thermal − − 18 / 53D / 61HD
θch-C − °C/W
Resistance(2) / 62HD / 63HD
3A154 / 54D
− − 17 / 55 / 55D

(2)
θch-C is thermal resistance between channel and case. Case temperature (T C) is measured at the center of the case top
surface.

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3. Performance Curves
3.1 Derating Curves
100 100

EAS Temperature Derating Coefficient (%)

Temperature Derating Coefficient (%)

80 80
Safe Operating Area

60 60

40 40

20 20

0 0
0 25 50 75 100 125 150 25 50 75 100 125 150

Channel Temperature, Tch (°C) Channel Temperature, Tch (°C)

Figure 3-1 SOA Temperature Derating Coefficient Curve Figure 3-2 Avalanche Energy Derating Coefficient Curve

3.2 MOSFET Safe Operating Area Curves

 When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1.
 The broken line in the safe operating area curve is the drain current curve limited by on-resistance.
 Unless otherwise specified, TA = 25 °C, Single pulse

 STR3A151 / 51D  STR3A152 / 52D

10 10
0.1ms
0.1ms
Drain Current, ID (A)

Drain Current, ID (A)

1 1

1ms 1ms

0.1 0.1

0.01 0.01
1 10 100 1000 1 10 100 1000

Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

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 STR3A153 / 53D  STR3A154 / 54D

10 10
0.1ms 0.1ms

Drain Current, ID (A)

Drain Current, ID (A)

1 1
1ms 1ms

0.1 0.1

0.01 0.01
1 10 100 1000 1 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

 STR3A155 / 55D  STR3A161HD

10 10
0.1ms
0.1ms
Drain Current, ID (A)

Drain Current, ID (A)

1 1
1ms
1ms

0.1 0.1

0.01 0.01
1 10 100 1000 1 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

 STR3A162HD  STR3A163HD
10 10
0.1ms
0.1ms
Drain Current, ID (A)
Drain Current, ID (A)

1 1

1ms 1ms

0.1 0.1

0.01
0.01
1 10 100 1000
1 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

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3.3 Ambient Temperature versus Power Dissipation Curves

 STR3A151 / 51D / 52 / 52D / 61HD / 62HD  STR3A153 / 53D / 54 / 54D / 63HD
2.0 2.0
1.8 PD1 = 1.68 W 1.8 PD1 = 1.76 W
Power Dissipation, PD1 (W)

Power Dissipation, PD1 (W)

1.6 1.6
1.4 1.4
1.2 1.2
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Ambient Temperature, TA (°C ) Ambient Temperature, TA (°C )

 STR3A155 / 55D
2.0
1.8 PD1=1.81W
Power Dissipation, PD1 (W)

1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 25 50 75 100 125 150
Ambient Temperature, TA (°C )

3.4 Transient Thermal Resistance Curves

 STR3A151 / 51D / 61HD
10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01
1µ 10µ 100µ 1m 10m 100m
Time (s)

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 STR3A152 / 52D / 62HD

100
Transient Thermal Resistance

10
θch-c (°C/W)

0.1

0.01
1µ 10µ 100µ 1m 10m 100m
Time (s)

 STR3A153 / 53D / 63HD

10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01
1µ 10µ 100µ 1m 10m 100m
Time (s)

 STR3A154 / 54D
10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01

0.001
1µ 10µ 100µ 1m 10m 100m
Time (s)

 STR3A155 / 55D
10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01
1µ 10µ 100µ 1m 10m 100m
Time (s)

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STR3A100 Series

4. Functional Block Diagram

VCC D/ST
2 5~8

FB/OLP 1
4 S/OCP
GND 3

5. Pin Configuration Definitions

Pin Name Descriptions

S/OCP 1 D/ST MOSFET source and overcurrent protection
8 1 S/OCP
(OCP) signal input
D/ST Power supply voltage input for control part and
VCC 2 7 2 VCC
overvoltage protection (OVP) signal input
GND 3 6 D/ST 3 GND Ground
Constant voltage control signal input and over
4 FB /OLP
FB/OLP 4 5 D/ST load protection (OLP) signal input
5
6
D/ST MOSFET drain and startup current input
7
8

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6. Typical Application Circuit

 The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation.
 In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the
D/ST pin and the S/OCP pin.

CRD clamp snubber L51

BR1 D51 VOUT
T1
VAC

R54
C5 R1
PC1 R51
C1
P
C51 R55
D1 S R52 C53

C52 R53

8 7 6 5 U2
R56
D2 R2
D/ST D/ST D/ST
NC D/ST
C4 U1
GND
STR3A100 D
C2
C（RC）
Damper snubber S/OCP VCC GND FB/OLP

1 2 3 4

ROCP C3

PC1 CY

Figure 6-1 Typical application circuit

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7. Package Outline
 DIP8

NOTES:
1) Dimension is in millimeters
2) Pb-free. Device composition compliant with the RoHS directive

8. Marking Diagram

3A1×××
Part Number
YMD
Lot Number
Y = Last Digit of Year (0-9)
1
M = Month (1-9,O,N or D)
D =Period of days (1 to 3)
1 : 1st to 10th
2 : 11th to 20th
3 : 21st to 31st
Sanken Control Number

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9. Operational Description 9.2 Undervoltage Lockout (UVLO)

 All of the parameter values used in these descriptions Figure 9-2 shows the relationship of VCC pin voltage
are typical values, unless they are specified as and circuit current ICC. When VCC pin voltage decreases
minimum or maximum. to VCC(OFF) = 8.1 V, the control circuit stops operation by
 With regard to current direction, "+" indicates sink UVLO (Undervoltage Lockout) circuit, and reverts to
current (toward the IC) and "–" indicates source the state before startup.
current (from the IC).
Circuit current, ICC
9.1 Startup Operation ICC（ON）
Figure 9-1 shows the circuit around VCC pin.
The IC incorporates the startup circuit. The circuit is
connected to D/ST pin. When D/ST pin voltage reaches Stop Start
to Startup Circuit Operation Voltage VST(ON) = 40 V, the
startup circuit starts operation.
During the startup process, the constant current,
ISTARTUP = − 2.5 mA, charges C2 at VCC pin. When
VCC pin voltage increases to VCC(ON) = 15.3 V, the
control circuit starts switching operation. VCC（OFF） VCC（ON） VCC pin
voltage
During the IC operation, the voltage rectified the
auxiliary winding voltage, VD, of Figure 9-1 becomes a
power source to the VCC pin. After switching operation Figure 9-2 Relationship between
begins, the startup circuit turns off automatically so that VCC pin voltage and ICC
its current consumption becomes zero.
The approximate value of auxiliary winding voltage is
about 18V, taking account of the winding turns of D
9.3 Bias Assist Function
winding so that VCC pin voltage becomes Equation (1) Figure 9-3 shows VCC pin voltage behavior during
within the specification of input and output voltage the startup period.
variation of power supply. After VCC pin voltage increases to VCC(ON) = 15.3 V
at startup, the IC starts the operation. Then circuit
VCC( BIAS) (max .)  VCC  VCC(OVP ) (min .) current increases and VCC pin voltage decreases. At the
same time, the auxiliary winding voltage VD increases in
⇒10.5(V)  VCC  27.0(V) proportion to output voltage. These are all balanced to
(1) produce VCC pin voltage.
The startup time of IC is determined by C2 capacitor
value. The approximate startup time t START is calculated VCC pin Startup success
as follows: voltage IC starts operation
Target operating
VCC( ON )－VCC( INT ) VCC(ON) voltage
t START  C2 × (2) VCC(BIAS) Increase with rising of
I STRATUP output voltage
Bias assist period
VCC(OFF)
where,
tSTART : Startup time of IC (s)
VCC(INT) : Initial voltage on VCC pin (V) Startup failure
Time
BR1 T1

VAC
Figure 9-3 VCC pin voltage during startup period
C1 P
The surge voltage is induced at output winding at
5-8 turning off a power MOSFET. When the output load is
D/ST light at startup, the surge voltage causes the unexpected
U1 D2 R2
VCC
2 feedback control. This results the lowering of the output
power and VCC pin voltage. When the VCC pin voltage
C2 VD D decreases to VCC(OFF) = 8.1 V, the IC stops switching
3 operation and a startup failure occurs. In order to prevent
GND
this, the Bias Assist function is activated when the VCC
Figure 9-1 VCC pin peripheral circuit pin voltage decreases to the startup current threshold

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biasing voltage, VCC(BIAS) = 9.5 V. While the Bias Assist

function is activated, any decrease of the VCC pin 9.5 Constant Output Voltage Control
voltage is counteracted by providing the startup current, The IC achieves the constant voltage control of the
ISTARTUP, from the startup circuit. Thus, the VCC pin power supply output by using the current-mode control
voltage is kept almost constant. method, which enhances the response speed and
By the Bias Assist function, the value of C2 is provides the stable operation.
allowed to be small and the startup time becomes shorter. The FB/OLP pin voltage is internally added the slope
Also, because the increase of VCC pin voltage becomes compensation at the feedback control (refer to Section
faster when the output runs with excess voltage, the 4.Functional Block Diagram), and the target voltage,
response time of the OVP function becomes shorter. VSC, is generated. The IC compares the voltage, V ROCP,
It is necessary to check and adjust the startup process of a current detection resistor with the target voltage,
based on actual operation in the application, so that poor VSC, by the internal FB comparator, and controls the
starting conditions may be avoided. peak value of VROCP so that it gets close to VSC, as
shown in Figure 9-5 and Figure 9-6.
9.4 Soft Start Function
Figure 9-4 shows the behavior of VCC pin voltage U1
and drain current during the startup period.
The IC activates the soft start circuitry during the S/OCP GND FB/OLP
startup period. Soft start time is fixed to around 7 ms.
during the soft start period, over current threshold is 1 3 4
increased step-wisely (5 steps). This function reduces
the voltage and the current stress of MOSFET and PC1
secondary side rectifier diode. VROCP ROCP IFB
C3
Since the Leading Edge Blanking Function (refer to
Section 9.6) is deactivated during the soft start period,
there is the case that ON time is less than the leading
edge blanking time, tBW = 350 ns.
After the soft start period, D/ST pin current, ID, is Figure 9-5 FB/OLP pin peripheral circuit
limited by the overcurrent protection (OCP), until the
output voltage increases to the target operating voltage. Target voltage including
This period is given as tLIM. Slope Compensation
In case tLIM is longer than the OLP Delay Time, tOLP,
the output power is limited by the OLP protection - VSC
operation (OLP).
Thus, it is necessary to adjust the value of output + VROCP
capacitor and the turn ratio of auxiliary winding D so
that the tLIM is less than tOLP = 54 ms (min.). Voltage on both
FB Comparator
sides of ROCP
Startup of SMPS
VCC pin Startup of IC
voltage Normal opertion Drain current,
tSTART ID
VCC(ON)

VCC(OFF) Figure 9-6 Drain current, ID, and FB comparator

operation in steady operation
Time

Soft start period  Light load conditions

approximately 7 ms (fixed) When load conditions become lighter, the output
D/ST pin
current, ID Limited by OCP operation voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
tLIM < tOLP (min.) FB/OLP pin voltage decreases. Thus, VSC decreases,
Time and the peak value of VROCP is controlled to be low,
and the peak drain current of I D decreases.
This control prevents the output voltage from
Figure 9-4 VCC and ID behavior during startup increasing.

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 Heavy load conditions 9.7 Random Switching Function

When load conditions become greater, the IC
performs the inverse operation to that described above. The IC modulates its switching frequency randomly
Thus, VSC increases and the peak drain current of ID by superposing the modulating frequency on fOSC(AVG) in
increases. normal operation. This function reduces the conduction
This control prevents the output voltage from noise compared to others without this function, and
decreasing. simplifies noise filtering of the input lines of power
supply.
In the current mode control method, when the drain
current waveform becomes trapezoidal in continuous
operating mode, even if the peak current level set by the 9.8 Automatic Standby Mode Function
target voltage is constant, the on-time fluctuates based Automatic standby mode is activated automatically
on the initial value of the drain current. when the drain current, ID, reduces under light load
This results in the on-time fluctuating in multiples of conditions, at which ID is less than 20 % to 25 %
the fundamental operating frequency as shown in Figure (STR3A154, 54D, 55 and 55D are 15 to 20 %) of the
9-7. This is called the subharmonics phenomenon. maximum drain current (it is in the OCP state). The
In order to avoid this, the IC incorporates the Slope operation mode becomes burst oscillation, as shown in
Compensation function. Because the target voltage is Figure 9-8. Burst oscillation mode reduces switching
added a down-slope compensation signal, which reduces losses and improves power supply efficiency because of
the peak drain current as the on-duty gets wider relative periodic non-switching intervals.
to the FB/OLP pin signal to compensate V SC, the Generally, to improve efficiency under light load
subharmonics phenomenon is suppressed. conditions, the frequency of the burst oscillation mode
Even if subharmonic oscillations occur when the IC becomes just a few kilohertz. Because the IC suppresses
has some excess supply being out of feedback control, the peak drain current well during burst oscillation mode,
such as during startup and load shorted, this does not audible noises can be reduced.
affect performance of normal operation. If the VCC pin voltage decreases to VCC(BIAS) = 9.5 V
during the transition to the burst oscillation mode, the
Target voltage Bias Assist function is activated and stabilizes the
without Slope Compensation Standby mode operation, because ISTARTUP is
provided to the VCC pin so that the VCC pin voltage
does not decrease to VCC(OFF).
However, if the Bias Assist function is always
activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
tON1 tON2 example, by adjusting the turns ratio of the auxiliary
winding and secondary winding and/or reducing the
T T T value of R2 in Figure 10-2 (refer to Section 10.1
Peripheral Components for a detail of R2).
Figure 9-7 Drain current, ID, waveform
in subharmonic oscillation Output current, Burst oscillation
IOUT

9.6 Leading Edge Blanking Function

The IC uses the peak-current-mode control method Below several kHz
for the constant voltage control of output.
In peak-current-mode control method, there is a case Drain current,
that the power MOSFET turns off due to unexpected ID
response of FB comparator or overcurrent protection Normal Standby Normal
circuit (OCP) to the steep surge current in turning on a operation operation operation
power MOSFET.
In order to prevent this response to the surge voltage
Figure 9-8 Auto Standby mode timing
in turning-on the power MOSFET, the Leading Edge
Blanking, tBW = 350 ns (STR3A16×HD for tBW = 280
ns) is built-in. During tBW, the OCP threshold voltage 9.9 Overcurrent Protection Function (OCP)
becomes about 1.7 V which is higher than the normal
OCP threshold voltage (refer to Section 9.9). Overcurrent Protection Function (OCP) detects each
drain peak current level of a power MOSFET on
pulse-by-pulse basis, and limits the output power when

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the current level reaches to OCP threshold voltage. OCP state, the IC incorporates a built-in Input
During Leading Edge Blanking Time, the OCP Compensation function.
threshold voltage becomes about 1.7 V which is higher The Input Compensation Function is the function of
than the normal OCP threshold voltage as shown in correction of OCP threshold voltage depending with AC
Figure 9-9. Changing to this threshold voltage prevents input voltage, as shown in Figure 9-11.
the IC from responding to the surge voltage in When AC input voltage is low (ON Duty is broad),
turning-on the power MOSFET. This function operates the OCP threshold voltage is controlled to become high.
as protection at the condition such as output windings The difference of peak drain current become small
shorted or unusual withstand voltage of secondary-side compared with the case where the AC input voltage is
rectifier diodes. high (ON Duty is narrow).
When power MOSFET turns on, the surge voltage The compensation signal depends on ON Duty. The
width of S/OCP pin should be less than tBW, as shown in relation between the ON Duty and the OCP threshold
Figure 9-9. In order to prevent surge voltage, pay extra voltage after compensation VOCP' is expressed as
attention to ROCP trace layout (refer to Section 10.2). Equation (3). When ON Duty is broader than 36 %, the
In addition, if a C (RC) damper snubber of Figure VOCP' becomes a constant value VOCP(H) = 0.88 V
9-10 is used, reduce the capacitor value of damper
snubber. 1.0

OCP Threshold Voltage after

tBW
VOCP(H)
compensation, VOCP'
About 1.7V
VOCP’ VOCP(L)

DDPC=36% DMAX=74%
Surge pulse voltage width at turning on 0.5
0 50 100
ON Duty (%)
Figure 9-9 S/OCP pin voltage

Figure 9-11 Relationship between ON Duty and Drain

C（RC） Current Limit after compensation
Damper snubber
T1

C1
D51 VOCP '  VOCP ( L)  DPC  ONTime
C51
ONDuty
5~8  VOCP ( L )  DPC 
f OSC ( AVG ) (3)
D/ST

U1 C（RC）
S/OCP Damper snubber
where,
1 VOCP(L): OCP Threshold Voltage at Zero ON Duty
ROCP
DPC: OCP Compensation Coefficient
ONTime: On-time of power MOSFET
ONDuty: On duty of power MOSFET
fOSC(AVG): Average PWM Switching Frequency
Figure 9-10 Damper snubber

9.10 Overload Protection Function (OLP)

< Input Compensation Function >
ICs with PWM control usually have some propagation Figure 9-12 shows the FB/OLP pin peripheral circuit,
delay time. The steeper the slope of the actual drain and Figure 9-13shows each waveform for OLP
current at a high AC input voltage is, the larger the operation.
detection voltage of actual drain peak current is, When the peak drain current of ID is limited by OCP
compared to VOCP. Thus, the peak current has some operation, the output voltage, VOUT, decreases and the
variation depending on the AC input voltage in OCP feedback current from the secondary photo-coupler
state. becomes zero. Thus, the feedback current, IFB, charges
In order to reduce the variation of peak current in C3 connected to the FB/OLP pin and the FB/OLP pin

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voltage increases. When the FB/OLP pin voltage auxiliary winding of transformer, the overvoltage
increases to VFB(OLP) = 8.1 V or more for the OLP delay conditions such as output voltage detection circuit open
time, tOLP = 70 ms or more, the OLP function is can be detected because the VCC pin voltage is
activated, the IC stops switching operation. proportional to output voltage. The approximate value of
During OLP operation, Bias Assist Function is output voltage VOUT(OVP) in OVP condition is calculated
disabled. Thus, VCC pin voltage decreases to VCC(OFF), by using Equation (4).
the control circuit stops operation. After that, the IC
reverts to the initial state by UVLO circuit, and the IC VOUT ( NORMAL )
starts operation when VCC pin voltage increases to VOUT(OVP)   29.5 (V) (4)
VCC( NORMAL )
VCC(ON) by startup current. Thus the intermittent
operation by UVLO is repeated in OLP state.
This intermittent operation reduces the stress of parts where,
such as power MOSFET and secondary side rectifier VOUT(NORMAL): Output voltage in normal operation
diode. In addition, this operation reduces power VCC(NORMAL): VCC pin voltage in normal operation
consumption because the switching period in this
intermittent operation is short compared with oscillation  Latched Shutdown type: STR3A1××
stop period. When the abnormal condition is removed, When the OVP function is activated, the IC stops
the IC returns to normal operation automatically. switching operation at the latched state. In order to
keep the latched state, when VCC pin voltage
decreases to VCC(BIAS), the bias assist function is
U1 activated and VCC pin voltage is kept to over the
GND FB/OLP VCC VCC(OFF).
Releasing the latched state is done by turning off the
3 4 2 input voltage and by dropping the VCC pin voltage
D2 R2 below VCC(OFF).
PC1
 Auto Restart Type: STR3A1××D
C3 C2 When the OVP function is activated, the IC stops
D switching operation. During OVP operation, the Bias
Assist function is disabled, the intermittent operation
by UVLO is repeated like OLP state (refer to Section
Figure 9-12 FB/OLP pin peripheral circuit 9.10). When the fault condition is removed, the IC
returns to normal operation automatically (refer to
Figure 9-14).
Non-switching interval
VCC pin voltage VCC pin voltage
VCC(ON)
VCC(OVP)
VCC(OFF)
VCC(ON)

FB/OLP pin voltage VCC(OFF)

tOLP tOLP
VFB(OLP)

Drain current,
ID
Drain current,
ID

Figure 9-14 OVP operational waveforms

Figure 9-13 OLP operational waveforms
9.12 Thermal Shutdown Function (TSD)
9.11 Overvoltage Protection (OVP) When the temperature of control circuit increases to
Tj(TSD) = 135 °C (min.) or more, Thermal Shutdown
When a voltage between VCC pin and GND terminal function (TSD) is activated. The IC has two operation
increases to VCC(OVP) = 29.5 V or more, OVP function is types of TSD function. One is latched shutdown, the
activated. The IC has two operation types of OVP other is auto restart.
function. One is latched shutdown. The other is auto
restart.
 Latched Shutdown type: STR3A1××
In case the VCC pin voltage is provided by using
When the TSD function is activated, the IC stops

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switching operation at the latched state. In order to  VCC Pin Peripheral Circuit
keep the latched state, when VCC pin voltage The value of C2 in Figure 10-1 is generally
decreases to VCC(BIAS), the bias assist function is recommended to be 10µ to 47μF (refer to Section 9.1
activated and VCC pin voltage is kept to over the Startup Operation, because the startup time is
VCC(OFF). determined by the value of C2)
Releasing the latched state is done by turning off the In actual power supply circuits, there are cases in
input voltage and by dropping the VCC pin voltage which the VCC pin voltage fluctuates in proportion to
below VCC(OFF). the output current, IOUT (see Figure 10-2), and the
Overvoltage Protection function (OVP) on the VCC
 Auto Restart Type: STR3A1××D pin may be activated. This happens because C2 is
When the TSD function is activated, the IC stops charged to a peak voltage on the auxiliary winding D,
switching operation. During TSD operation, the Bias which is caused by the transient surge voltage coupled
Assist function is disabled, the intermittent operation from the primary winding when the power MOSFET
by UVLO is repeated like OLP state (refer to Section turns off.
9.10). When the fault condition is removed and the For alleviating C2 peak charging, it is effective to add
temperature decreases to less than Tj(TSD), the IC some value R2, of several tenths of ohms to several
returns to normal operation automatically. ohms, in series with D2 (see Figure 10-1). The
optimal value of R2 should be determined using a
transformer matching what will be used in the actual
10. Design Notes application, because the variation of the auxiliary
winding voltage is affected by the transformer
structural design.
10.1 External Components
Take care to use properly rated, including derating as VCC pin voltage Without R2
necessary and proper type of components.

CRD clamp snuber

BR1
T1
VAC

C1
C5 R1
P
With R2
D1
Output current, IOUT
8 7 6 5 D2 R2

C4 D/ST D/ST D/ST

NC D/ST
Figure 10-2 Variation of VCC pin voltage and power
U1 D
C2
C（RC） STR3A100
Damper snubber
S/OCP VCC GND FB/OLP  FB/OLP Pin Peripheral Circuit
1 2 3 4 Figure 10-1 performs high frequency noise rejection
and phase compensation, and should be connected
ROCP C3 close to these pins. The value of C3 is recommended
PC1 to be about 2200 pF to 0.01µF, and should be selected
based on actual operation in the application.
Figure 10-1 The IC peripheral circuit
 Snubber Circuit
In case the serge voltage of VDS is large, the circuit
 Output Electrolytic Capacitor should be added as follows (see Figure 10-1);
Apply proper derating to ripple current, voltage, and ・ A clamp snubber circuit of a capacitor-resistor-
temperature rise. Use of high ripple current and low diode (CRD) combination should be added on the
impedance types, designed for switch mode power primary winding P.
supplies, is recommended. ・ A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be
 S/OCP Pin Peripheral Circuit added between the D/ST pin and the S/OCP pin.
In Figure 10-1, ROCP is the resistor for the current In case the damper snubber circuit is added, this
detection. A high frequency switching current flows components should be connected near D/ST pin
to ROCP, and may cause poor operation if a high and S/OCP pin.
inductance resistor is used. Choose a low inductance
and high surge-tolerant type.  Phase Compensation
Figure 10-3 shows the secondary side detection circuit

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with the standard shunt regulator IC (U51). auxiliary winding D.

C52 and R53 are for phase compensation. The value
of C52 and R53 are recommended to be around P1、P2 ： Primary main winding
0.047μF to 0.47μF and 4.7 kΩ to 470 kΩ, respectively. Margin tape D ： Primary auxiliary winding
They should be selected based on actual operation in S1 ： Secondary Stabilized
output winding

Bobbin
the application. P1 S1 P2 S2 D S2 ： Secondary output winding

Margin tape
L51
T1 D51 VOUT
Winding structural example (a)

R54 Margin tape

PC1 R51

Bobbin
R55 P1 S1 D S2 S1 P2
C51
S R52 C53 Margin tape

C52 R53 Winding structural example (b)

U51 Figure 10-4 Winding structural examples

R56
GND

▫ Winding structural example (a): Separating the

auxiliary winding D from the primary windings P1
Figure 10-3 Peripheral circuit of secondary side shunt
and P2.
regulator (U51)
where: P1 and P2 are windings divided the primary
winding into two.
 Transformer ▫ Winding structural example (b): Placing the
Apply proper design margin to core temperature rise auxiliary winding D within the secondary-side
by core loss and copper loss. stabilized output winding, S1, in order to improve
Because the switching currents contain high the coupling of those windings.
frequency currents, the skin effect may become a where: S1 is a stabilized output winding of
consideration. secondary-side windings, controlled to constant
Choose a suitable wire gauge in consideration of the voltage.
RMS current and a current density of about 3 to
4A/mm2.
If measures to further reduce temperature are still 10.2 PCB Trace Layout and Component
necessary, the following should be considered to Placement
increase the total surface area of the wiring:
Since the PCB circuit trace design and the component
▫ Increase the number of wires in parallel. layout significantly affects operation, EMI noise, and
▫ Use litz wires. power dissipation, the high frequency PCB trace should
▫ Thicken the wire gauge. be low impedance with small loop and wide trace.
Fluctuation of the VCC pin voltage by IOUT worsens In addition, the ground traces affect radiated EMI noise,
in the following cases, requiring a transformer and wide, short traces should be taken into account.
designer to pay close attention to the placement of Figure 10-5 shows the circuit design example.
the auxiliary winding D:
(1) Main Circuit Trace Layout: S/OCP pin to ROCP to C1
▫ Poor coupling between the primary and secondary to T1 (winding P) to D/ST pin
windings (this causes high surge voltage and is seen This is the main trace containing switching currents,
in a design with low output voltage and high output and thus it should be as wide trace and small loop as
current) possible.
▫ Poor coupling between the auxiliary winding D and If C1 and the IC are distant from each other, placing
the secondary stabilized output winding where the a capacitor such as film capacitor (about 0.1 μF and
output line voltage is controlled constant by the with proper voltage rating) close to the transformer
output voltage feedback (this is susceptible to surge or the IC is recommended to reduce impedance of
voltage) the high frequency current loop.
In order to reduce the influence of surge voltage on
the VCC pin, Figure 10-4 shows winding structural (2) Control Ground Trace Layout
examples that are considered the placement of the Since the operation of IC may be affected from the

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STR3A100 Series

large current of the main trace that flows in control as close to FB/OLP pin as possible. The trace
ground trace, the control ground trace should be between the components and FB/OLP pin should be
separated from main trace and connected at a single as short as possible.
point grounding of point A in Figure 10-5 as close
to the ROCP pin as possible. (6) Secondary Rectifier Smoothing Circuit Trace
Layout: T1 (winding S) to D51 to C51
(3) VCC Trace Layout: GND pin to C2 (negative) to T1 This is the trace of the rectifier smoothing loop,
(winding D) to R2 to D2 to C2 (positive) to VCC pin carrying the switching current, and thus it should be
This is the trace for supplying power to the IC, and as wide trace and small loop as possible. If this trace
thus it should be as small loop as possible. If C2 and is thin and long, inductance resulting from the loop
the IC are distant from each other, placing a may increase surge voltage at turning off the power
capacitor such as film capacitor Cf (about 0.1 μF to MOSFET. Proper rectifier smoothing trace layout
1.0 μF) close to the VCC pin and the GND pin is helps to increase margin against the power MOSFET
recommended. breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(4) ROCP Trace Layout
ROCP should be placed as close as possible to the (7) Thermal Considerations
S/OCP pin. The connection between the power Because the power MOSFET has a positive thermal
ground of the main trace and the IC ground should coefficient of RDS(ON), consider it in thermal design.
be at a single point ground (point A in Figure Since the copper area under the IC and the D/ST pin
10-5) which is close to the base of ROCP. trace act as a heatsink, its traces should be as wide as
possible.
(5) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
(1) Main trace should be wide (6) Main trace of secondary side should
trace and small loop be wide trace and small loop
D51
T1

C5 R1
C1
P
(7)Trace of D/ST pin should beDST C51
wide for heat release
D1 S

8 7 6 5
D2 R2
D/ST D/ST NC
D/ST D/ST
C4 U1
STR3A100
C2 D
S/OCP VCC GND FB/OLP

1 2 3 4
(3) Loop of the power
supply should be small

ROCP
PC1
(5)The components connected to
C3 FB/OLP pin should be as close
to FB/OLP pin as possible

A CY

(4)ROCP Should be as close to S/OCP pin as (2) Control GND trace should be connected at a
possible. single point as close to the ROCP as possible

Figure 10-5 Peripheral circuit example around the IC

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STR3A100 Series

11. Pattern Layout Example

The following show the PCB pattern layout example and the schematic of circuit using STR3A100 series. Only the
parts in the schematic are used. Other parts in PCB are leaved open.

Figure 11-1 PCB circuit trace layout example

F1
1
L1 L51 CN51
C10 D1 D2 TH1 T1 D51
C2
C1 R5 VOUT1
D4 D3 R54
C11 C4 R1 R51
C56 R62
3 C3
J1 P1 R55
R4 R52 C53
C51 PC1
R57
D5 S1
R53 C52 JW52

U51
8 7 6 5 R56

D/ST D/ST NC
D/ST D/ST GND

C8 U1 JW51 R60
STR3A100 JW53
R58 L52 R59
D6 R2 D52
S/OCP VCC GND FB/OLP
OUT2
1 2 3 4
C5 D
C57 R63 C54 C55 R61

C7 GND
R3 C6 PC1
C9 CN52

Figure 11-2 Circuit schematic for PCB circuit trace layout

The above circuit symbols correspond to these of Figure 11-1.

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12. Reference Design of Power Supply

As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and
the transformer specification.
 Power supply specification
IC STR3A153
Input voltage AC85V to AC265V
Maximum output power 40.4 W (peak)
Output 1 8 V / 0.5 A
Output 2 14 V / 2.3 A (2.6 A peak)

 Circuit schematic
Refer to Figure 11-2
 Bill of materials
Recommended Recommended
Symbol Part type Ratings(1) Symbol Part type Ratings(1)
Sanken Parts Sanken Parts
F1 Fuse AC 250 V, 3 A L51 Inductor Short
(2)
L1 CM inductor 3.3 mH L52 Inductor Short
(2)
TH1 NTC thermistor Short D51 Schottky 90 V, 1.5 A EK19
D1 General 600 V, 1 A EM01A D52 Schottky 150V, 10A FMEN-210B
(2)
D2 General 600 V, 1 A EM01A C51 Electrolytic 470 μF, 25 V
(2)
D3 General 600 V, 1 A EM01A C52 Ceramic 0.1 μF, 50 V
(2)
D4 General 600 V, 1 A EM01A C53 Electrolytic Open
D5 Fast recovery 1000 V, 0.5 A EG01C C54 Electrolytic
(2)
D6 Fast recovery 200 V, 1 A AL01Z C55 Electrolytic Open
(2) (2)
C1 Film, X2 0.047 μF, 275 V C56 Ceramic Open
(2) (2)
C2 Electrolytic Open C57 Ceramic Open
C3 Electrolytic 10 μF, 400 V R51 General Open
C4 Ceramic 1000 pF, 2 kV R52 General 1.5 kΩ
(2)
C5 Electrolytic 22 μF, 50 V R53 General 100 kΩ
(2)
C6 Ceramic 0.01 μF R54 General, 1% Open
(2)
C7 Ceramic Open R55 General, 1% Open
(2)
C8 Ceramic 15 pF / 2 kV R56 General, 1% 10 kΩ
C9 Ceramic, Y1 2200 pF, 250 V R57 General Open
(2)
C10 Ceramic Open R58 General 2.2 kΩ
(2) (2)
C11 Ceramic Open R59 General 6.8 kΩ
(3)
R1 Metal oxide 150 kΩ, 2 W R60 General, 1% 39 kΩ
(2)
R2 General 10 Ω R61 General Open
(2) (2)
R3 General 0.47 Ω, 1/2 W R62 General Open
(2) (2)
R4 General Short R63 General Open
(3)
R5 Metal oxide Open JW51 Short
PC1 Photo-coupler PC123 or equiv JW52 Short
U1 IC － STR3A153 JW53 Short
See VREF = 2.5 V
T1 Transformer the specification
U51 Shunt regulator
TL431 or equiv
(1)
Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2)
It is necessary to be adjusted based on actual operation in the application.
(3)
Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use
combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.

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STR3A100 Series

 Transformer specification
▫ Primary inductance, LP ：518 μH
▫ Core size ：EER-28
▫ Al-value ：245 nH/N2 (Center gap of about 0.56 mm)
▫ Winding specification

Winding Symbol Number of turns (T) Wire diameter (mm) Construction

Single-layer,
Primary winding P1 18 φ 0.23 × 2
solenoid winding
Single-layer,
Primary winding P2 28 φ 0.30
solenoid winding
Auxiliary winding D 12 φ 0.30 × 2 Solenoid winding
Output 1 winding S1-1 6 φ 0.4 × 2 Solenoid winding
Output 1 winding S1-2 6 φ 0.4 × 2 Solenoid winding
Output 2 winding S2-1 4 φ 0.4 × 2 Solenoid winding
Output 2 winding S2-2 4 φ 0.4 × 2 Solenoid winding

2mm 4mm

VDC
P2 8V
P1
S1-1 S1-2
Margin tape
Margin tape

S2-2 S1-2 P1
Pin side

D
Drain
S2-1 S1-1 14V
P2 VCC
S2-1 S2-2
Bobbin D
GND
Core GND

Cross-section view ●: Start at this pin

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STR3A100 Series

OPERATING PRECAUTIONS
In the case that you use Sanken products or design your products by using Sanken products, the reliability largely
depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation
range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to
assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric
current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused
due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum
values must be taken into consideration. In addition, it should be noted that since power devices or IC’s including power
devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly.

Because reliability can be affected adversely by improper storage environments and handling methods, please
observe the following cautions.
Cautions for Storage
 Ensure that storage conditions comply with the standard temperature (5 to 35°C) and the standard relative humidity
(around 40 to 75%); avoid storage locations that experience extreme changes in temperature or humidity.
 Avoid locations where dust or harmful gases are present and avoid direct sunlight.
 Reinspect for rust on leads and solderability of the products that have been stored for a long time.
Cautions for Testing and Handling
When tests are carried out during inspection testing and other standard test periods, protect the products from power
surges from the testing device, shorts between the product pins, and wrong connections. Ensure all test parameters are
within the ratings specified by Sanken for the products.
Remarks About Using Silicone Grease with a Heatsink
 When silicone grease is used in mounting the products on a heatsink, it shall be applied evenly and thinly. If more
silicone grease than required is applied, it may produce excess stress.
 Volatile-type silicone greases may crack after long periods of time, resulting in reduced heat radiation effect.
Silicone greases with low consistency (hard grease) may cause cracks in the mold resin when screwing the
products to a heatsink.
Our recommended silicone greases for heat radiation purposes, which will not cause any adverse effect on the
product life, are indicated below:
Type Suppliers
G746 Shin-Etsu Chemical Co., Ltd.
YG6260 Momentive Performance Materials Inc.
SC102 Dow Corning Toray Co., Ltd.
Soldering
 When soldering the products, please be sure to minimize the working time, within the following limits:
• 260 ± 5 °C 10 ± 1 s (Flow, 2 times)
• 380 ± 10 °C 3.5 ± 0.5 s (Soldering iron, 1 time)
 Soldering should be at a distance of at least 1.5 mm from the body of the products.
Electrostatic Discharge
 When handling the products, the operator must be grounded. Grounded wrist straps worn should have at least 1MΩ
of resistance from the operator to ground to prevent shock hazard, and it should be placed near the operator.
 Workbenches where the products are handled should be grounded and be provided with conductive table and floor
mats.
 When using measuring equipment such as a curve tracer, the equipment should be grounded.
 When soldering the products, the head of soldering irons or the solder bath must be grounded in order to prevent
leak voltages generated by them from being applied to the products.
 The products should always be stored and transported in Sanken shipping containers or conductive containers, or
be wrapped in aluminum foil.

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IMPORTANT NOTES
 The contents in this document are subject to changes, for improvement and other purposes, without notice.
Make sure that this is the latest revision of the document before use.
 Application and operation examples described in this document are quoted for the sole purpose of reference
for the use of the products herein and Sanken can assume no responsibility for any infringement of
industrial property rights, intellectual property rights or any other rights of Sanken or any third party which
may result from its use. Unless otherwise agreed in writing by Sanken, Sanken makes no warranties of any
kind, whether express or implied, as to the products, including product merchantability, and fitness for a
particular purpose and special environment, and the information, including its accuracy, usefulness, and
reliability, included in this document.
 Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure
and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested
to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to the society due to device failure or malfunction.
 Sanken products listed in this document are designed and intended for the use as components in general
purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication
equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required
(transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime
alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general
purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to
discuss, prior to the use of the products herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high
reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is
strictly prohibited.
 When using the products specified herein by either (i) combining other products or materials therewith or
(ii) physically, chemically or otherwise processing or treating the products, please duly consider all
possible risks that may result from all such uses in advance and proceed therewith at your own
responsibility.
 Anti radioactive ray design is not considered for the products listed herein.
 Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation
out of Sanken’s distribution network.
 The contents in this document must not be transcribed or copied without Sanken’s written consent.

STR3A100 - DS Rev.1.31 SANKEN ELECTRIC CO.,LTD. 25

Jan. 28, 2014