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EXPERIMENT 5 Verilog

This document describes an experiment to implement 2-to-1, 4-to-1, and 8-to-1 multiplexers in Verilog using different modeling styles. It provides background on multiplexers and their logic functions. Codes for the multiplexers are developed using data flow, gate level, and behavioral modeling. Simulations and reports on the RTL schematic, technology schematic, and area are generated to analyze and compare the multiplexer designs. The experiment aims to verify different Verilog modeling styles for multiplexer implementation.

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283 views7 pages

EXPERIMENT 5 Verilog

This document describes an experiment to implement 2-to-1, 4-to-1, and 8-to-1 multiplexers in Verilog using different modeling styles. It provides background on multiplexers and their logic functions. Codes for the multiplexers are developed using data flow, gate level, and behavioral modeling. Simulations and reports on the RTL schematic, technology schematic, and area are generated to analyze and compare the multiplexer designs. The experiment aims to verify different Verilog modeling styles for multiplexer implementation.

Uploaded by

uday
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT

5
Aim:- Verilog Implementation of 2 to 1, 4 to 1 and 8 to 1 multiplexers using different
modelling style.
Important Concepts/Theory: -
The multiplexer, shortened to “MUX”, is a combinational logic circuit designed to switch
one of several input lines through to a single common output line by the application of a
control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.

2x1 Multiplexer:
I0

I1
2x1

Fig. 1: 2x1 Mux Logic Diagram


Fig. 2: 2x1 Mux Symbol
Table 1: Truth Table for 2x1 Mux

Logic Function:

Y = D0S’+D1S

4x1 Multiplexer:
I0
I1 Y

I2
4x1

I3
S0

S1
Table 2: Truth Table for 4x1 Mux
Fig. 3: 4x1 Mux Logic Diagram Fig. 4: 4x1 Mux Symbol
Logic Function:

Y = D0S1’S0’+D1S1’S0 + DS1S0’ +D3S1S0

8x1 Multiplexer:
I0
I1
I2 I1
I3
Y
I4
8x1 Mux
I5

I6
S2
I7 S1
S0

Fig. 5: 8x1 Mux Logic Diagram Fig. 6: 8x1 Mux Symbol

Table 3: Truth Table for 8x1 Mux

Logic Function:

Y = D0S2’S1’S0’+ D1S2’S1’S0 + D2S2’S1S0’ +


D3S2’S1S0 + D4S2S1’S0’+ D5S2S1’S0’+
D6S2S1S0’ + D7S2S1S0’
Design Analysis:
Codes:
1. 2x1 Mux (Data Flow Modelling):

2. 4x1 Mux (Gate Level Modelling):

3. 8x1 Mux (Behavioral Modelling):


Results/ Discussion:-

Simulation (waveforms):

1. 2x1 Mux:

Fig. 7: 2x1 Mux


2. 4x1 Mux:

Fig. 8: 4x1 Mux


3. 8x1 Mux:

Fig. 9: 8x1 Mux

Report Results:

RTL Schematic:

1. 2x1 Mux:
Fig. 10: 2x1 Mux
2. 4x1 Mux:

3. 8x1 Mux: Fig. 11: 4x1 Mux

Fig. 12: 8x1 Mux

Tech Schematic :

1. 2x1 Mux:

2. 4x1 Mux: Fig. 13: 2x1 Mux


Fig. 14: 4x1 Mux

3. 8x1 Mux:

Area Report:
1. 2x1 Mux: Fig. 15: 8x1 Mux

2. 4x1 Mux:
3. 8x1 Mux:

Conclusion:
Verilog HDL code for 2 to 1, 4 to 1 and 8 to 1 multiplexers using different modelling style
has been implemented and their simulation with signals has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6

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