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MP Assignment 1

a) CPI = (0.3 * 6) + (0.5 * 4) + (0.2 * 3) / 1 = 4.4 b) Native MIPS = Clock rate / (CPI * Execution time in seconds) = 200MHz / (4.4 * 11) = 4.55 million instructions per second So the native MIPS processor speed is 4.55 MIPS. 3-2. Explain the following flags in status register: - Zero flag (Z) - Carry flag (C) - Sign flag (S) - Overflow flag (V) Zero flag (Z): The zero flag is set if

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156 views9 pages

MP Assignment 1

a) CPI = (0.3 * 6) + (0.5 * 4) + (0.2 * 3) / 1 = 4.4 b) Native MIPS = Clock rate / (CPI * Execution time in seconds) = 200MHz / (4.4 * 11) = 4.55 million instructions per second So the native MIPS processor speed is 4.55 MIPS. 3-2. Explain the following flags in status register: - Zero flag (Z) - Carry flag (C) - Sign flag (S) - Overflow flag (V) Zero flag (Z): The zero flag is set if

Uploaded by

Fatima Sheikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Military college of signals

Microprocessor systems

Assignment #1
Submitted to :

Ma’am Aimen Akif

Submitted by:

Momina Javed

Fatima Sheikh

(BETE 55D)

Dated:4/6/2020
Architecture
1-1. Discuss the difference between thread and process

THREAD:

A thread computer science is short for a thread of execution. Threads are a way for
a program to divide (termed "split") itself into two or more simultaneously (or pseudo-
simultaneously) running tasks.

PROCESS:

A process is an instance of a program running in a computer. It is close in meaning


to task, a term used in some operating systems.

DIFFERENCE:

THREAD PROCESS
1. A thread cannot live on its own. It There must be one thread in a process.
must live within a process.
2. It has direct access to the data It has its own copy of the data segment
segment of its process. of the parent process.
3. Threads are controlled by Process is controlled by the operating
programmer in a program. system
4. Threads run in shared memory Processes run in separate memory
spaces. spaces.
5. Threads are dependent. Processes are independent.

1-2. Differentiate between Multithreading and hyperthreading

MULTITHREADING:
A technique by which a single set of code can be used by several processors at different
stages of execution.

HYPERTHREADING:

A high-performance computing architecture that simulates some degree of overlap in


executing two or more independent sets of instructions.
MULTITHREADING HYPERTHREADING
1. A mechanism that allows multiple A technology that allows a single
threads to exit within the context of processor to operate like two separate
a process such that they execute processors to the operating system and
independently but share their the application programs that use it.
process resources.
2. A process is divided into multiple A physical processor is divided into
threads two virtual or logical processors
3. Multithreading refers to the Hyper threading refers to a very
general task of running more than technology created by Intel, which
one thread of execution within an allows a single processor core to
operating system. interleave multiple threads of
execution more efficiently.
4. Multi-threading is making a Hyper threading is Intel’s name for
program use multiplethreadsto making 2 threads per core in a
complete a task. processor.

1-3. Explain the limitations of multithreading which are addressed by


multiprocessor architecture.

ANS:

LIMITATIONS:

1)Multiple threads can interfere with each other when sharing hardware resources such
as caches or translation lookaside buffers(TLBs). As a result, execution times of a single
thread are not improved and can be degraded, even when only one thread is executing,
due to lower frequencies or additional pipeline stages that are necessary to
accommodate thread-switching hardware.

2) Multithreading can only be achieved if the code of the running program has been
optimized for it.

3) It will be unable to process multiple threads simultaneously if they require the same
functional part of the processor.

Multiprocessor or Multicore is an architecture where a single chip contains multiple


processors (each with its own set of registers and processing resources). It is also called
Chip Multiprocessor (CMP) or multicore processor. This resolves the above mentioned
limitations of multithreading i.e. now the code need not be optimized for simultaneous
processing and two threads requiring same functional part of processor can be execuded
simultaneously.

1-4. Differentiate between bus cycle, machine cycle, instruction cycle.

.
DIFFERENCE:

BUS CYCLE MACHINE CYCLE INSTRUCTION CYCLE


1.The bus cycle is the cycle The machine cycle is the The instruction cycle is how
or time required to make a amount of cycles needed to do many of these machine
single read or write either a fetch, read or write cycles are needed to
transaction between the operation. complete an instruction
CPU and an external device
such as external memory
2.The system bus connects A machine cycle consists of the The instruction
the CPU, memory, and the steps that a cycle (also known as the
input/output devices. It computer's processor executes fetch–decode–execute cycl
carries data, address, and whenever it receives a machine e or simply the fetch-
control information. language instruction. It is the execute cycle) is
most basic CPU operation, and the cycle which the central
modern CPUs are able to processing unit (CPU)
perform millions of machine follows from boot-up until
cycles per second. the computer has shut down
in order to
process instructions.
3.Hardware components Its components includes: The instruction
(wire, optical fiber, etc.) and Memory Unit and Central cycle (also known as the
software, including Processing Unit fetch–decode–execute cycl
communication protocols. e or simply the fetch-
execute cycle) is
the cycle which the central

Questions from Historical Background of Microprocessors

2-1. List the aspects of microprocessor which have been improved along with
technological advancements.

The following aspects of microprocessor have been increased along with technological
advancements:-

 Clock speed
 Transistors
 Data width
 Million Instructions Per Second (MIPS) / Kilo instructions per second (KIPS)
 Instructions set (multiplication, division, complex instructions such as roots,
logic gates included in instructions)
 Main memory.

2-2. Which microprocessor introduced the concept of cache? Explain the purpose
of cache.

Intel (80486), introduced in 1989 introduced the concept of cache L1. L1 cache (also
called primary cache) is built directly into the microprocessor, a location referred to as
“on-die”.

An 8 KB on-chip (level 1) SRAMcache stores the most recently used instructions and
data.

Purpose of cache:-

In computing, a cache is a hardware or software component that stores data so that


future requests for that data can be served faster; the data stored in a cache might be the
result of an earlier computation or a copy of data stored elsewhere.

The purpose of cache memory is to store program instructions and data that are used
repeatedly in the operation of programs or information that the CPU is likely to need
next. The computer processor can access this information quickly from the cache rather
than having to get it from computer's main memory.

The basic purpose of cache memory is to store program instructions that are frequently
re-referenced by software during operation.

2-3.Determine the relationship between processor word size and number of


supportable instructions? Is it linear?

The relationship between processor word size and number of supportable instructions is
linear. If the processor word size is 16 bits, then number of supportable instructions will
also be 16 bits.

2-4. The Pentium Pro, Pentium II, Pentium III, Pentium 4, and Core2 processors
all are based on P6 core architecture of intel processors but they have different
performance. Explain the reason for each.

The reason for different performance is clock speed which is the speed at which a
microprocessor executes instructions.

Clock speed of Pentium Pro processor : 200 MHz

Clock speed of Pentium 2 processor : 300 MHz


Clock speed of Pentium 3 processor : 500 MHz

Clock speed of Pentium 4 processor : 1 GHz

Clock speed of Core2 processor : 3.6 GHz

Questions for Registers contents and Flag Status

3-1 You are given a task to design a new processor. The clock of the processor runs
at 200 MHz. The following table gives instruction frequencies for Pearl
microprocessor, as well as how many cycles the instructions take, for the different
classes of instructions. Assume that (unlike many of today's computers) the
processor only executes one instruction at a time. (8)

Instruction Type Frequency Cycles


Loads & Stores 30% 6 cycles
Arithmetic 50% 4 cycles
Instructions
All Others 20% 3 cycles

a. Calculate the CPI for Pearl microprocessor.


b. The CPU execution time on the Pearl is exactly 11 seconds. What is the
``native MIPS'' processor speed for the benchmark in millions of
instructions per second?

The formula for calculating MIPS is:

MIPS = Clock rate/(CPI * 106)

c. The hardware expert says that if you double the number of registers, the
cycle time must be increased by 20%. What would the new clock speed be
(in MHz)?
d. The compiler expert says that if you double the number of registers, then
the compiler will generate code that requires only half the number of
Loads & Stores. What would the new CPI be on the Pearl?

Solution :

a) CPI=30x6+50x4+20x3

100

=4.4

b) MIPS = Clock rate/(CPI * 106)


=200x106/4.4x106
=45.45
c) f=200MHz
t=1/200M
=5x10-9 s
After 20% increase =1x10-9 s
Adding it to the original =6x10-9s
f=1/t
=0.167x109
=
167M Hz.

d) CPI=(15x6+50x4+20x3)/85
=4.12

3-2 : CS=1000H, DS=2000H, SS=3000H, ES=4000H, IP=1232H, SP=114FH,


SI=0004H, DI=0020H, BX=45EFH, BP=FF00H. For the contents of the
registers shown above, determine the following:-
i. Physical address of next instruction to be fetched
ii. Physical address of location pointed by Destination Index
iii. Physical address of top of stack
iv. Physical address of location pointed by BX
i. Physical address of next instruction to be fetched
CS 10000H
IP 1232H
PA 11232H
ii. Physical address of location pointed by Destination Index
DS 20000H
DI 0020H
PA 20020H
iii. Physical address of top of stack
SS 30000H
SP 114FH
PA 3114FH
iv. Physical address of location pointed by BX.
DS 20000H
BX 45EFH
PA 245EFH
3-3. For CS = 1000H, DS = 2010H, SS = 3020H, ES = 4030H, determine the offset
address needed to access following physical addresses:

i. 1FF35H within Code Segment


ii. 3DD43H within Stack Segment
iii. 45FF0H within Extra Segment
iv. 23232H within Data Segment
v. i. 1FF35H within Code Segment
vi. PA 1FF35H
vii. CS 10000H
viii. IP FF35H
ix. ii. 3DD43H within Stack Segment
x. PA 3DD43H
xi. SS 30200H
xii. DB43H
xiii. iii. 45FF0H within Extra Segment
xiv. PA 45FF0H
xv. ES 40300H
xvi. 5CF0H
xvii. iv. 23232H within Data Segment.
xviii. PA 23232H
xix. DS 20100H
xx. 3132H

3-4. Show status of all conditional flags (also called status flags) for addition of
these two unsigned 16-bit numbers: 10011101110101 and 100101011010101.

010011101110101 + 100101011010101 = 111001001001010

Carry Flag : 0(no carry out of MSB)

Auxiliary Carry Flag : 0(no carry out of fourth bit)

Sign Flag :1(MSB is one)

Zero Flag : 0

Parity Flag : 0
Overflow Flag : 0
3-5. Show status of all conditional flags (also called status flags) for addition of
these two signed 16-bit numbers: 10011101110101 and 100101011010101 .

100101011010101 +10011101110101 = 1011001001001010

Carry Flag :1 (carry out of MSB)

Auxiliary Carry Flag :0(no carry out of 4th bit)

Sign Flag : 1(answer is negative)

Zero Flag : 0(answer is not zero)

Parity Flag :0(no. of ones in lower byte is odd)

Overflow Flag : 1(15th bit is 0)

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