198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6

6.1 Introduction

The design considerations for a simple inverter circuit were presented in the previous
chapter. In this chapter, the design of the inverter will be extended to address the synthesis
of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina-
tional logic (or non-regenerative) circuits that have the property that at any point in time,
the output of the circuit is related to its current input signals by some Boolean expression
(assuming that the transients through the logic gates have settled). No intentional connec-
tion between outputs and inputs is present.
In another class of circuits, known as sequential or regenerative circuits —to be dis-
cussed in a later chapter—, the output is not only a function of the current input data, but
also of previous values of the input signals (Figure 6.1). This is accomplished by connect-
ing one or more outputs intentionally back to some inputs. Consequently, the circuit
“remembers” past events and has a sense of history. A sequential circuit includes a combi-
national logic portion and a module that holds the state. Example circuits are registers,
counters, oscillators, and memory.

Combinational In Combinational Out

In Logic Out Logic
Circuit Circuit

State
(a) Combinational (b) Sequential

Figure 6.1 High level classification of logic circuits.

There are numerous circuit styles to implement a given logic function. As with the
inverter, the common design metrics by which a gate is evaluated include area, speed,
energy and power. Depending on the application, the emphasis will be on different metrics
(e.g., in high performance processor, the switching speed of digital circuits is the primary
metric while in a battery operated circuit it is the energy dissipation). In addition to these
metrics, robustness to noise is also a very important consideration. We will see that certain
logic styles (e.g., Dynamic logic) can significantly improve performance, but can be more
sensitive to noise. Recently, power dissipation has also become a very important require-
ment and significant emphasis is placed on understanding the sources of power and
approaches to deal with power.

6.2 Static CMOS Design

The most widely used logic style is static complementary CMOS. The static CMOS style
is really an extension of the static CMOS inverter to multiple inputs. In review, the pri-
mary advantage of the CMOS structure is robustness (i.e, low sensitivity to noise), good
performance, and low power consumption (with no static power consumption). As we will
Section 6.2 Static CMOS Design 199

see, most of those properties are carried over to large fan-in logic gates implemented using
the same circuit topology.
The complementary CMOS circuit style falls under a broad class of logic circuits
called static circuits in which at every point in time (except during the switching tran-
sients), each gate output is connected to either VDD or Vss via a low-resistance path. Also,
the outputs of the gates assume at all times the value of the Boolean function implemented
by the circuit (ignoring, once again, the transient effects during switching periods). This is
in contrast to the dynamic circuit class, that relies on temporary storage of signal values on
the capacitance of high-impedance circuit nodes. The latter approach has the advantage
that the resulting gate is simpler and faster. On the other hand, its design and operation are
more involved than those of its static counterpart, due to an increased sensitivity to noise.
In this section, we sequentially address the design of various static circuit flavors
including complementary CMOS, ratioed logic (pseudo-NMOS and DCVSL), and pass-
transistor logic. The issues of scaling to lower power supply voltages and threshold volt-
ages will also be dealt with.

6.2.1 Complementary CMOS

A static CMOS gate is a combination of two networks, called the pull-up network (PUN)
and the pull-down network (PDN) (Figure 6.2). The figure shows a generic N input logic
gate where all inputs are distributed to both the pull-up and pull-down networks. The func-
tion of the PUN is to provide a connection between the output and VDD anytime the output
of the logic gate is meant to be 1 (based on the inputs). Similarly, the function of the PDN
is to connect the output to VSS when the output of the logic gate is meant to be 0. The PUN
and PDN networks are constructed in a mutually exclusive fashion such that one and only
one of the networks is conducting in steady state. In this way, once the transients have set-
tled, a path always exists between VDD and the output F, realizing a high output (“one”),
or, alternatively, between VSS and F for a low output (“zero”). This is equivalent to stating
that the output node is always a low-impedance node in steady state.
In constructing the PDN and PUN networks, the following observations should be
kept in mind:
VDD

In1
In2 pull-up: make a connection from VDD to F when
PUN
F(In1,In2, ... Inn) = 1
InN

F (In1,In2, ... Inn)

In1
In2
pull-down: make a connection from VDD to Vss when
PDN F(In1,In2, ... Inn) = 0
InN

VSS

Figure 6.2 Complementary logic gate as a combination of a PUN (pull-up network) and a
PDN (pull-down network).
200 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6

• A transistor can be thought of as a switch controlled by its gate signal. An NMOS

switch is on when the controlling signal is high and is off when the controlling signal
is low. A PMOS transistor acts as an inverse switch that is on when the controlling
signal is low and off when the controlling signal is high.
• The PDN is constructed using NMOS devices, while PMOS transistors are used in
the PUN. The primary reason for this choice is that NMOS transistors produce
“strong zeros,” and PMOS devices generate “strong ones”. To illustrate this, con-
sider the examples shown in Figure 6.3. In Figure 6.3a, the output capacitance is ini-
tially charged to VDD. Two possible discharge scenario’s are shown. An NMOS
device pulls the output all the way down to GND, while a PMOS lowers the output
no further than |VTp| — the PMOS turns off at that point, and stops contributing dis-
charge current. NMOS transistors are hence the preferred devices in the PDN. Simi-
larly, two alternative approaches to charging up a capacitor are shown in Figure
6.3b, with the output load initially at GND. A PMOS switch succeeds in charging
the output all the way to VDD, while the NMOS device fails to raise the output above
VDD-VTn. This explains why PMOS transistors are preferentially used in a PUN.

Out VDD→ 0 Out VDD→ |VTp|

VDD CL CL

(a) pulling down a node using NMOS and PMOS switches

VDD 0→ VDD- VTn 0 → VDD

Out
Out
CL
CL
(b) pulling down a node using NMOS and PMOS switches
Figure 6.3 Simple examples illustrate why an NMOS should be used as a pull-
down transistor, while a PMOS should be used as a pull-up device.

• A set of construction rules can be derived to construct logic functions (Figure 6.4).
NMOS devices connected in series corresponds to an AND function. With all the
inputs high, the series combination conducts and the value at one end of the chain is
transfered to the other end. Similarly, NMOS transistors connected in parallel repre-
sent an OR function. A conducting path exists between the output and input terminal
if at least one of the inpurs is high. Using similar arguments, construction rules for
PMOS networks can be formulated. A series connection of PMOS conducts if both
Section 6.2 Static CMOS Design 201

B A
Series Combination Parallel Combination
A B
Conducts if A · B Conducts if A + B

(a) series (b) parallel

Figure 6.4 NMOS logic rules — series devices implement an AND, and parallel devices
implement an OR.

inputs are low, representing a NOR function (A.B = A+B), while PMOS transistors
in parallel implement a NAND (A+B = A·B.
• Using De Morgan’s theorems ((A + B) = A·B and A·B = A + B), it can be shown that
the pull-up and pull-down networks of a complementary CMOS structure are dual
networks. This means that a parallel connection of transistors in the pull-up network
corresponds to a series connection of the corresponding devices in the pull-down
network, and vice versa. Therefore, to construct a CMOS gate, one of the networks
(e.g., PDN) is implemented using combinations of series and parallel devices. The
other network (i.e., PUN) is obtained using duality principle by walking the hierar-
chy, replacing series subnets with parallel subnets, and parallel subnets with series
subnets. The complete CMOS gate is constructed by combining the PDN with the
PUN.
• The complementary gate is naturally inverting, implementing only functions such as
NAND, NOR, and XNOR. The realization of a non-inverting Boolean function
(such as AND OR, or XOR) in a single stage is not possible, and requires the addi-
tion of an extra inverter stage.
• The number of transistors required to implement an N-input logic gate is 2N.

Example 6.1 Two input NAND Gate

Figure 6.5 shows a two-input NAND gate (F = A·B). The PDN network consists of two
NMOS devices in series that conduct when both A and B are high. The PUN is the dual net-
work, and consists of two parallel PMOS transistors. This means that F is 1 if A = 0 or B = 0,
which is equivalent to F = A·B. The truth table for the simple two input NAND gate is given
in Table 6.1. It can be verified that the output F is always connected to either VDD or GND,
but never to both at the same time.

Example 6.2 Synthesis of complex CMOS Gate

Using complementary CMOS logic, consider the synthesis of a complex CMOS gate whose
function is F = D + A· (B +C). The first step in the synthesis of the logic gate is to derive the
pull-down network as shown in Figure 6.6a by using the fact that NMOS devices in series
implements the AND function and parallel device implements the OR function. The next step
is to use duality to derive the PUN in a hierarchical fashion. The PDN network is broken into
smaller networks (i.e., subset of the PDN) called sub-nets that simplify the derivation of the
PUN. In Figure 6.6b, the subnets (SN) for the pull-down network are identified At the top
level, SN1 and SN2 are in parallel so in the dual network, they will be in series. Since SN1
202 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6

VDD
Table 6.1Truth Table for 2 input NAND
A B
A B F

F 0 0 1
0 1 1
A
1 0 1
1 1 0
B

Figure 6.5 Two-input NAND gate in complementary static CMOS style.

consists of a single transistor, it maps directly to the pull-up network. On the other hand, we
need to recursively apply the duality rules to SN2. Inside SN2, we have SN3 and SN4 in
series so in the PUN they will appear in parallel. Finally, inside SN3, the devices are in paral-
lel so they will appear in series in the PUN. The complete gate is shown in Figure 6.6c. The
reader can verify that for every possible input cobmination, there always exists a path to
either VDD or GND.

VDD VDD

SN1 F SN4 A
F B
SN2
A A
D D SN3
B C B C D

F
A
(a) pull-down network (b) Deriving the pull-up network
hierarchically by identifying D
subnets B C

Figure 6.6 Complex complementary CMOS gate.

(c) complete gate

Static Properties of Complementary CMOS Gates

Complementary CMOS gates inherit all the nice properties of the basic CMOS inverter,
discussed earlier.They exhibit rail to rail swing with VOH = VDD and VOL = GND. The cir-
cuits also have no static power dissipation, since the circuits are designed such that the
pull-down and pull-up networks are mutually exclusive. The analysis of the DC voltage
transfer characteristics and the noise margins is more complicated then for the inverter, as
these parameters depend upon the data input patterns applied to gate.
Consider the static two-input NAND gate shown in Figure 6.7. Three possible input
combinations switch the output of the gate from high-to-low: (a) A = B = 0 → 1, (b) A= 1,
204 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6

connect all the inputs together. This unfortunately does not represent the worst-case static
behavior. The data dependencies should be carefully modeled.

Propagation Delay of Complementary CMOS Gates

The computation of propagation delay proceeds in a fashion similar to the static inverter.
For the purpose of delay analysis, each transistor is modeled as a resistor in series with an
ideal switch. The value of the resistance is dependent on the power supply voltage and an
equivalent large signal resistance, scaled by the ratio of device width over length, must be
used. The logic is transformed into an equivalent RC network that includes the effect of
internal node capacitances. Figure 6.8 shows the two-input NAND gate and its equivalent
RC switch level model. Note that the internal node capacitance Cint —attributable to the
source/drain regions and the gate overlap capacitance of M2/M1— is included. While com-
plicating the analysis, the capacitance of the internal nodes can have quite an impact in
some networks such as large fan-in gates.
VDD
VDD
RP RP
A B
M3 M4 A B
F
F RN
CL
A M2 B

RN
Cint
B M1
A

(a) Two-input NAND (b) RC equivalent model

Figure 6.8 Equivalent RC model for a NAND gate.

We will initially ignore the effect of the internal capacitance (for a first pass). The
most important observation is that delay is also dependent on the input patterns. Consider
for instance the low-to-high transition. Three possible input scenarios can be identified for
charging the output to VDD. If both inputs are driven low, the two PMOS devices are on.
The delay in this case is 0.69 × (Rp/2) × CL, since the two resistors are in parallel. This is
not the worst-case low-to-high transition, which occurs when only one device turns on,
and is given by 0.69 × Rp × CL. For the pull-down path, the output is discharged only if
both A and B are switched high, and the delay is given by 0.69 × (2RN) × CL to a first
order. In other words, adding devices in series slows down the circuit, and devices must be
made wider to avoid a performance penalty. When sizing the transistors in a gate with
multiple fan-in’s, we should pick the combination of inputs that triggers the worst-case
conditions.
For example, for a NAND gate to have the same pull-down delay delay (tphl) as a
minimum sized inverter (NMOS: 0.375µm/0.25µm and PMOS: 1.125µm/0.25µm), the
212 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6

Figure 6.16 Logic restructuring

can reduce the gate fan-in.

Power Consumption in CMOS Logic Gates

The sources of power consumption for the complementary CMOS inverter was dis-
cussed in detail. Many of issues apply directly to complex CMOS gates. The power dissi-
pation is a strong function of transistor sizing (which affects physical capacitance), input
and output rise/fall times (which affects the short-circuit power), device thresholds and
temperature (which affect leakage power) and switching activity. The switching power of
a CMOS gate is given by α0→1 CL VDD2 f and this section will focus of on the switching
activity (α0→1) of a logic gate. There are two components to switching activity: a static
component (which does not take into account the timing behavior) and a dynamic (or
glitching) component (which takes into account the timing behavior of the circuit). The
major factors that affect activity is listed below.
Logic Function —The amount of transition activity is a strong function of the logic
function being implemented. In static CMOS gates, the static transition probability
assuming independent inputs is the probability that the output will be in the zero state in
one cycle multiplied by the probability that the output will be in the one state in the next
cycle:

α0 → 1 = p 0 • p1 = p0 • ( 1 – p0 ) (6.7)

where p 0 is the probability that the output is in the zero state and p1 is the probability that
the output will is in the one state. Assuming that the inputs are independent and uniformly
distributed, any N-input static gate will have a transition probability that corresponds to:

N 0 •  2 – N 0
N
N0 N1
α 0 → 1 = ------- • ------- = -------------------------------------- (6.8)
N N 2N
2 2 2
where N0 is the number of zero entries and N1 is the number of one entries in the truth
table for the output of the N-input function. To illustrate, consider a static 2-input NOR
gate whose truth table is shown in Table 6.3. Assume that only one input transition is pos-
sible during a clock cycle and that the inputs to the NOR gate have a uniform input distri-
bution (i.e., the four possible states for inputs A and B (00, 01, 10, 11) are equally likely).
Table 6.3 Truth table of a 2 input NOR gate.

A B Out

0 0 1

0 1 0