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Bahria University, Lahore Campus: Department of Computer Sciences

The document outlines a digital logic design lab on constructing a half adder circuit using basic logic gates. The objective is to build a half adder using an KL-33004 module and observe the output of each gate. The lab consists of two tasks - the first is to build the half adder circuit and the second is to construct the given circuit and observe the outputs.

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Abdul Basit
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70 views5 pages

Bahria University, Lahore Campus: Department of Computer Sciences

The document outlines a digital logic design lab on constructing a half adder circuit using basic logic gates. The objective is to build a half adder using an KL-33004 module and observe the output of each gate. The lab consists of two tasks - the first is to build the half adder circuit and the second is to construct the given circuit and observe the outputs.

Uploaded by

Abdul Basit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Bahria University, Lahore Campus

Department of Computer Sciences


Lab Journal 07
(Spring 2020)

Course: Digital Logic Design Lab Date:


Course Code: CEL-120 Max Marks: 30
Faculty’s Name: Ms. Munazza Sher Lab Engineer: Mr. Shoaib Khan

Name: _____________________________ Enroll No: _______________________

Objective(s):
▪ To construct half adder circuit.

Lab Tasks:

Task 1: Construct Half Adder with basic logic gates (using Module KL-33004, block a).

Task 2: Construct the given circuit and observe the output of each gate.

Lab Grading Sheet :


Max Obtained
Task Comments(if any)
Marks Marks
1. 15
2. 15

Total 30 Signature

Note : Attempt all tasks and get them checked by your Lab Instructor
Lab 07: Half Adder Circuit

Objective(s):

“To construct half adder circuit”.

Tool(s) used:

● KL-31001 DLD Trainer


● Module KL-33004
● Connector leads

Overview:

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
The carry signal represents an overflow into the next digit of a multi-digit addition.

Task 01: Time: 30 Minutes

Construct Half Adder with basic logic gates (using Module KL-33004, block a).

TruthTable:

Input Output

SW1 (A) SW0 (B) F1 F2

0 0 0 0

0 1 1 0

1 0 1 0
1 1 0 1

Diagram:

Task 02: Time: 30 Minutes


Construct the given circuit and observe the output of each gate.
A B G1 G2 G3 G4 G5 G6 G7

0 0 1 1 1 1 0 1 0

0 1 1 0 0 1 1 1 0

1 0 0 1 1 0 1 1 0

1 1 0 0 1 1 0 0 1

0 0 1 1 1 1 0 1 0

0 1 1 0 0 1 1 1 0

1 0 0 1 1 0 1 1 0

1 1 0 0 1 1 0 0 1
Diagram:

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