A Course Material on

MICROPROCESSOR AND MICROCONTROLLER

By

Mr. C.JAGADEESHWARAN

ASSISTANT PROFESSOR

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SASURIE COLLEGE OF ENGINEERING

VIJAYAMANGALAM – 638 056

 QUALITY CERTIFICATE

This is to certify that the e-course material

Subject Code : EE2354

Scubject : Microprocessor and Microcontroller

Class : III Year EEE

being prepared by me and it meets the knowledge requirement of the university curriculum.

Signature of the Author

Name: C.Jagadeeshwaran

Designation: Assistant Professor/ECE

This is to certify that the course material being prepared by Mr. C.Jagadeeshwaran is of adequate
quality. He has referred more than five books amont them minimum one is from aborad author.

Signature of HD

Name: S.Sriram
 CONTENTS

UNIT–1 8085 & 8086 PROCESSOR 1 to 23

1.1 Hardware Architecture of 8085 Microprocessor 1
1.2 Pin Diagram 3
1.3 Memory Interfacing 6
1.3.1 Typical EPROM and Static RAM 6
1.3.2 Example for Memory Interfacing 8
1.4 Timing Diagram 9
1.4.1 Machine cycles of 8085 9
1.4.2 Timing diagram for STA 526AH 12
1.4.3 Timing diagram for INR M 13
1.5 Interrupts 14
1.5.1Types of Interrupts 14
1.6 Hardware Architecture of 8085 Microprocessor 17
1.7 8086-Minimum mode of operation 20
1.7.1 Minimum Mode Interface 21
1.7.2 Maximum Mode Interface 21
1.8 I/O Ports 23
UNIT–2 PROGRAMMING OF 8085 PROCESSOR 25 to 35
2.1 Instruction Format 25
2.1.1 One-Byte Instructions 25
2.1.2 Two-Byte Instructions 26
2.1.3 Three-Byte Instructions 27
2.2 The 8085 Addressing Modes 27
2.3 Instruction Set Classification 28
2.3.1 Data Transfer Croup 28
2.3.2 Arithmetic Group 29
2.3.3 Logical Group 29
2.3.4 Branch Group 30
2.3.5 Stack Instructions 31
2.3.6 I/0 instructions 31
2.3.7 Machine Control instructions 31
2.4 Sample Program 31
2.5 Programming using Loop structure with Counting and Indexing 32
2.6 Programming using subroutine Instructions 34
2.7 Programming using Look up table 35
UNIT–3 PERIPHERAL INTERFACING 37 to 58
3.1 Programmable peripheral interface (8255) 37
3.1.1 Architecture of 8255 37
3.1.2 Pin Diagram of 8255 38
3.1.3 Operational Modes of 8255 39
 3.1.4 Control Word Format 40
3.2 Programmable Interrupt Controller (8259) 41
3.2.1 Features 41
3.2.2 Pinout 42
3.2.3 Block diagram 43
3.3 8251 USART 47
3.3.1 Block Diagram of 8251 47
3.3.2 Control Words 48
3.3.3 Status Word 51
3.4 Programmable Keyboard/Display Interface - 8279 51
3.4.1 Pinout Definition 8279 52
3.4.2 Block Diagram of 8279 53
3.4.2 Keyboard Interface of 8279 54
3.5 ADC Interfacing with 8085 Microprocessor 56
3.5.1 Features 56
3.5.2 Block Diagram of ADC 0809 57
3.6 DAC Interfacing with 8085 Microprocessor 58
3.6.1 DAC 0800 Features 58
3.6.2 Circuit Diagram of DAC 0800 58
UNIT–4 8051 MICRO CONTROLLER 61 to 69
4.1 Architecture of 8051 61
4.1.1 Memory Organization 61
4.1.2 Interrupt Structure 62
4.1.3 Port Structure 62
4.1.4 Timer/Counter 63
4.2 Instruction Format 63
4.2.1 One-Byte Instructions 63
4.2.2 Two-Byte Instructions 63
4.2.3 Three-Byte Instructions 64
4.3 Addressing Modes of 8051 64
4.4 Interrupt Structure 65
4.4.1 External Interrupt 66
4.4.2 Handling Interrupt 66
4.5 I/O Ports 67
4.6 Timers 67
4.6.1Timer SFR 68
4.6.2 13-bit Time Mode (mode 0) 68
4.6.3 16-bit Time Mode (mode 1) 68
4.6.4 8-bit Time Mode (mode 2) 68
4.6.5 Split Timer Mode (mode 3) 68
4.6.6 Using Timers As Event Counters 69
4.7 Serial Communication 69
UNIT–5 MICRO CONTROLLER PROGRAMMING & APPLICATIONS 70 to 89
5.1 Arithmetic Instructions 70
5.2 Logical Instructions 70
5.3 Data Transfer Instructions that access the Internal Data Memory 71
5.4 Data Transfer Instructions that access the External Data Memory 71
5.5 Look up Tables 71
5.6 Boolean Instructions 72
5.7 Jump Instructions 72
5.8 Interfacing Keyboard to 8051 Microcontroller 73
5.9 Program for Keyboard Interfacing with 8051 74
5.10 Seven Segment Disply Interfacing with 8051 75
5.11 LCD Interfacing 76
5.12 Stepper Motor Interfacing 82
5.13 Servo Motor 85
5.13.1 Controlling the Servo Motor 85
5.13.2 Program 87
5.14 Washing Machine Control 88
5.14.1 SCHEMATIC 89
5.14.2 Working of Washing Machine 89
EE2354 MICROPROCESSORS AND MICRO CONTROLLER LT PC
3 0 03

AIM

To introduce Microprocessor Intel 8085 and 8086 and the Micro Controller 8051

OBJECTIVES

 To study the Architecture of 8085 & 8086, 8051

 To study the addressing modes & instruction set of 8085 & 8051.
 To introduce the need & use of Interrupt structure 8085 & 8051.
 To develop skill in simple program writing for 8051 & 8085 and applications
 To introduce commonly used peripheral / interfacing ICs

UNIT I 8085 and 8086 PROCESSOR 9

Hardware Architecture pintouts - Signals – Memory interfacing – I/O ports and data transfer concepts –
Timing Diagram – Interrupt structure.

UNIT II PROGRAMMING OF 8085 PROCESSOR 9

Instruction format and addressing modes – Assembly language format – Data transfer, data manipulation
& control instructions – Programming: Loop structure with counting & Indexing - Look up table -
Subroutine instructions - stack.

UNIT III PERIPHERAL INTERFACING 9

Study of Architecture and programming of ICs: 8255 PPI, 8259 PIC, 8251 USART, 8279 Key board
display controller and 8253 Timer/ Counter – Interfacing with 8085 - A/D and D/A converter interfacing.

UNIT IV 8051 MICRO CONTROLLER 9

Functional block diagram - Instruction format and addressing modes – Timing Diagram Interrupt
structure – Timer –I/O ports – Serial communication.

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9

Data Transfer, Manipulation, Control & I/O instructions – Simple programming exercises key board and
display interface – Closed loop control of servo motor- stepper motor control - Washing Machine
Control.

L = 45 T = 15 TOTAL : 60 PERIODS
TEXT BOOKS

1. “Microprocessor and Microcontrollers”, Krishna Kant Eastern Company Edition, Prentice – Hall of
India, New Delhi , 2007.
2. Muhammad Ali Mazidi & Janice Gilli Mazidi, R.D.Kinely ‘The 8051 Micro Controller and
Embedded Systems’, PHI Pearson Education, 5th Indian reprint, 2003.

REFERENCES

1. R.S. Gaonkar, ‘Microprocessor Architecture Programming and Application’, Wiley Eastern Ltd.,
New Delhi.
2. The 8088 & 8086 Microprocessors , Walter A Tribal & Avtar Singh, Pearson, 2007, Fourth Edition.
EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT - 1

8085 & 8086 PROCESSOR

1.1 Hardware Architecture of 8085 Microprocessor

Fig 1.1 Hardware Architecture of 8085

Control Unit:

Generates signals within Microprocessor to carry out the instruction, which has been decoded.
In reality causes certain connections between blocks of the µP to be opened or closed, so that data
goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit:

The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc.
Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation
in Accumulator.

Registers:

The 8085/8080A-programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program

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counter. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,
C, D, E, H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL
- to perform some 16-bit operations. The programmer can use these registers to store or copy data into
the registers by using data copy instructions.

Accumulator:

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register
is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation
is stored in the accumulator. The accumulator is also identified as register A.

Flags:

The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero (Z), Carry (CY),
Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Zero, Carry,
and Sign. The microprocessor uses these flags to test data conditions.

For example, after an addition of two numbers, if the sum in the accumulator id larger than eight
bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an arithmetic
operation results in zero, the flip-flop called the Zero (Z) flag is set to one. The first Figure shows an
8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register;
five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are stored in
the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the
register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor. The
conditions (set or reset) of the flags are tested through the software instructions. For example, the
instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is
set.

Program Counter (PC):

This 16-bit register deals with sequencing the execution of instructions. This register is a memory
pointer. Memory locations have 16-bit addresses, and that is why this is a16-bit register. The
microprocessor uses this register to sequence the execution of the instructions. The function of the
program counter is to point to the memory address from which the next byte is to be fetched. When a
byte (machine code) is being fetched, the program counter is incremented by one to point to the next
memory location

Stack Pointer (SP):

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading 16- bit
address in the stack pointer.

Instruction Register/Decoder:

Temporary store for the current instruction of a program. Latest instruction sent here from
memory prior to execution. Decoder then takes instruction and „decodes‟ or interprets the instruction.
Decoded instruction then passed to next stage.

Memory Address Register:

Holds address, received from PC, of next program instruction. Feeds the address bus with

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addresses of location of the program under execution.

Control Generator:

Generates signals within µP to carry out the instruction which has been decoded.

In reality causes certain connections between blocks of the µP to be opened or closed, so that
data goes where it is required, and so that ALU operations occur.

Register Selector:

This block controls the use of the register stack in the example. Just a logic circuit which switches
between different registers in the set will receive instructions from Control Unit.

1.2 Pin Diagram

Fig 1.2 Pin Diagram of 8085

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A8 - A15 (Output 3 State):

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3
stated during Hold and Halt modes.

AD0 - AD7 (Input / Output 3 state):

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on
the bus during the first clock cycle of a machine state. It then becomes thedata bus during the second
and third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output):

Address Latch Enable: It occurs during the first clock cycle of a machine state and enables
the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information. ALE can also be used to strobe the status
information. ALE is never 3stated.

SO, S1 (Output):

Data Bus Status. Encoded status of the bus cycle:

S1 S0

0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH S1 can be used as an advanced R/W status.

RD (Output 3state):

READ: indicates the selected memory or I/0 device is to be read and that the Data Bus is available
for the data transfer.

WR (Output 3state):

WRITE: indicates the data on the Data Bus is to be written into the selected memory or I/0
location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

READY (Input):

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the
read or write cycle.

HOLD (Input):

HOLD: indicates that another Master is requesting the use of the Address and Data Buses. The
CPU, upon receiving the Hold request will relinquish the use of buses as soon as the completion of the
current machine cycle. Internal processing can continue. The processor can regain the buses only after
the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines
are 3stated.

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HLDA (Output):

HOLD ACKNOWLEDGE: indicates that the CPU has received the Hold request and that it will
relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The
CPU takes the buses one half clock cycle after HLDA goes low.

INTR (Input):

INTERRUPT REQUEST is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited
from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction
can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software.
It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output):

INTERRUPT ACKNOWLEDGE: is used instead of (and has the same timing as) RDduring the
Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or
some other interrupt port.

RESTART INTERRUPTS:

These three inputs have the same timing as INTR except they cause an internal
RESTART to be automatically inserted.

 RST 7.5 Highest Priority

 RST 6.5
 RST 5.5 Lowest Priority

TRAP (Input):

Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as INTR. It
is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

RESET IN (Input):

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.
None of the other flags or registers (except the instruction register) are affected The CPU is held in the
reset condition as long as Reset is applied.

RESET OUT (Output):

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the
processor clock.

X1, X2 (Input):

Crystal or R/C network connections to set the internal clock generator X1 can also be an external
clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating
frequency.

CLK (Output):

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the
CPU. The period of CLK is twice the X1, X2 input period.

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IO/M (Output):

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt
modes.

SID (Input):

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.

SOD (output):

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc:

+5 volt supply.

Vss:

Ground Reference.

1.3 Memory Interfacing

The memory is made up of semiconductor material used to store the programs and data. Three
types of memory is,

 Process memory
 Primary or main memory
 Secondary memory

1.3.1 Typical EPROM and Static RAM

Fig 1.3 Static RAM and EPROM

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Table1.1 Number of Address Pins and Data Pins in Memory ICs

Memory IC Number of Number of data
Capacity
EPROM/RAM address pins pins
2708/6208 1 kb 10 8
2716/6216 2 kb 11 8
2732/6232 4 kb 12 8

2764/6264 8 kb 13 8

27256/62256 32 kb 15 8

27512/62512 64 kb 16 8

27010/62128 128 kb 17 8

27020/62138 256 kb 18 8

27040/62148 512 kb 19 8

 A typical semiconductor memory IC will have n address pins, m data pins (or output pins).
 Having two power supply pins (one for connecting required supply voltage (V and the other for
connecting ground).
 The control signals needed for static RAM are chip select (chip enable), read control (output
enable) and write control (write enable).
 The control signals needed for read operation in EPROM are chip select (chip enable) and read
control (output enable).

Fig 1.4 Block Diagram of 3 to 8 Decoder

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Table 1.2 Truth Table for 3 to 8 decoder

Input Output
C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1

Fig 1.5 Block Diagram of 2-4 Decoder

Table 1.3 Truth Table for 2-4 Decoder

Input Output
B A Y3 Y2 Y1 Y0
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1

1.3.2 Example for Memory Interfacing

Consider a system in which the full memory space 64kb is utilized for EPROM memory.
Interface the EPROM with 8085 processor. The memory capacity is 64 Kbytes. i.e 2^n = 64 x 1000
bytes where n = address lines. So, n = 16.

In this system the entire 16 address lines of the processor are connected to address input pins of
memory IC in order to address the internal locations of memory. The chip select (CS) pin of EPROM is
permanently tied to logic low (i.e., tied to ground).

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Since the processor is connected to EPROM, the active low RD pin is connected to active low
output enable pin of EPROM. The range of address for EPROM is 0000H to FFFFH.

Fig 1.6 Memory Interfacing

1.4 Timing Diagram

Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:

The time required to execute an instruction is called instruction cycle.

Machine Cycle:

The time required to access the memory or input/output devices is called machine cycle.

T-State:

 The machine cycle and instruction cycle takes multiple clock periods.
 A portion of an operation carried out in one system clock period is called as T-state.

1.4.1 Machine cycles of 8085

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

 Opcode fetch cycle (4T)

 Memory read cycle (3 T)
 Memory write cycle (3 T)
 I/O read cycle (3 T)
 I/O write cycle (3 T)

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Fig 1.7 Clock Signal

1.Opcode fetch machine cycle of 8085 :

Fig 1.8 Opcode fetch machine cycle

 Each instruction of the processor has one byte opcode.

 The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle
to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

2. Memory Read Machine Cycle of 8085:

 The memory read machine cycle is executed by the processor to read a data byte from memory.
 The processor takes 3T states to execute this cycle.
 The instructions which have more than one byte word size will use the machine cycle after the
opcode fetch machine cycle.

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
Fig 1.9 Memory Read Machine Cycle

3. Memory Write Machine Cycle of 8085

Fig 1.10 Memory Write Machine Cycle

 The memory write machine cycle is executed by the processor to write a data byte in a memory
location.
 The processor takes, 3T states to execute this machine cycle.

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4. I/O Read Cycle of 8085

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the
peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.
 The IN instruction uses this machine cycle during the execution.

Fig 1.11 I/O Read Cycle

1.4.2 Timing diagram for STA 526AH

Fig 1.12 Timing Diagram for STA 526A H

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 STA means Store Accumulator -The contents of the accumulator is stored in the specified address
(526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see
fig). - OF machine cycle
 Then the lower order memory address is read (6A). - Memory Read Machine Cycle
 Read the higher order memory address (52).- Memory Read Machine Cycle
 The combination of both the addresses are considered and the content from accumulator is
written in 526A. - Memory Write Machine Cycle
 Assume the memory address for the instruction and let the content of accumulator is C7H. So,
C7H from accumulator is now stored in 526A.

1.4.3 Timing diagram for INR M

 Fetching the Opcode 34H from the memory 4105H. (OF cycle)
 Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data)
 Let the content of that memory is 12H.
 Increment the memory content from 12H to 13H. (MW machine cycle)

Fig 1.13 Timing Diagram for INR M

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1.5 Interrupts

Interrupt is signals send by an external device to the processor, to request the processor to
perform a particular task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer between the
peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the
peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program counter.
 It returned to main program by RET instruction.

1.5.1Types of Interrupts:

It supports two types of interrupts.

 Hardware
 Software

1.5.1.1 Software interrupts:

The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. The 8085 has eight software interrupts from RST 0 to RST 7. The vector address
for these interrupts can be calculated as follows.

 Interrupt number * 8 = vector address

 For RST 5,5 * 8 = 40 = 28H
 Vector address for interrupt RST 5 is 0028H

Table 1.4 Vector addresses of all interrupts.

1.5.1.2 Hardware interrupts:

An external device initiates the hardware interrupts and placing an appropriate signal at the
interrupt pin of the processor. If the interrupt is accepted then the processor executes an interrupt service
routine.

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The 8085 has five hardware interrupts

 TRAP
 RST 7.5
 RST 6.5
 RST 5.5
 INTR

TRAP:

 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means that the TRAP must go high and remain
high until it is acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
 There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:

 The RST 7.5 interrupt is a maskable interrupt.

 It has the second highest priority.
 It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
 Maskable interrupt. It is disabled by,

1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.

 Enabled by EI instruction.

RST 6.5 and 5.5:

 The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it
recognized.
 Maskable interrupt. It is disabled by,

1.DI, SIM instruction

2.System or processor reset.
3.After reorganization of interrupt.

 Enabled by EI instruction.
 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:

INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction

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2.System or processor reset.

3.After reorganization of interrupt

 Enabled by EI instruction.
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address
of ISR.
 It has lowest priority.
 It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state
until it recognized.

The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt
acknowledge signal, if the interrupt is enabled.

3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus.
In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by
the 8085 to transfer the additional bytes into the microprocessor.

4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.

SIM and RIM for interrupts:

 The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
 The status of these interrupts can be read by executing RIM instruction.

 The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by
moving an 8-bit data to accumulator and then executing SIM instruction.

Fig 1.15 8 bit data to be loaded into the Accumulator

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 The status of pending interrupts can be read from accumulator after executing RIM instruction.
 When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown in fig.

Fig 1.16 Format of 8 bit data in Accumulator after executing RIM Instruction

1.6 Hardware Architecture of 8085 Microprocessor

 Intel 8086 was launched in 1978.

 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of 8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
a. 8086 (5 MHz)
b. 8086-2 (8 MHz)
c. 8086-1 (10 MHz)
 It consists of 29,000 transistors.

Bus Interface Unit (BIU):

The function of BIU is to

 Fetch the instruction or data from memory.

 Write the data to memory.
 Write the data to the port.
 Read data from the port.

Instruction Queue:

 To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from
memory.
 All six bytes are then held in first in first out 6 byte register called instruction queue.
 Then all bytes have to be given to EU one by one.
 This pre fetching operation of BIU may be in parallel with execution operation of EU, which
improves the speed execution of the instruction.

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Execution Unit (EU):

The functions of execution unit are

 To tell BIU where to fetch the instructions or data from.

 To decode the instructions.
 To execute the instructions.

Fig 1.17 Architecture of 8086

The EU contains the control circuitry to perform various internal operations. A decoder in EU
decodes the instruction fetched memory to generate different internal or external control signals
required to perform the operation. EU has 16-bit ALU, which can perform arithmetic and logical
operations on 8-bit as well as 16-bit.

General Purpose Registers of 8086:

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to
have AX,BX, CX, and DX.

a. AX Register: AX register is also known as accumulator register that stores operands for
arithmetic operation like divided, rotate.
b. BX Register: This register is mainly used as a base register. It holds the starting base location
of a memory region within a data segment.
c. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop
counter.
d. DX Register: DX register is used to contain I/O port address for I/O instruction.

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Segment Registers:

Fig 1.18 Memory Segments of 8086

Additional registers called segment registers generate memory address when combined with
other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow:

a. Code Segment (CS): The CS register is used for addressing a memory location in the Code
Segment of the memory, where the executable program is stored.
b. Data Segment (DS): The DS contains most data used by program. Data are accessed in the
Data Segment by an offset address or the content of other register that holds the offset
address.
c. Stack Segment (SS): SS defined the area of memory used for the stack.
d. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold
the destination data.

Flag Registers of 8086:

Fig 1.19 Flag Register of 8086

Flags Register determines the current state of the processor. They are modified automatically by
CPU after mathematical operations, this allows to determine the type of the result, and to determine
conditions to transfer control to other parts of the program. 8086 has 9 flags and they are divided into
two categories:

 Conditional Flags
 Control Flags

Conditional Flags

Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are
as follows:

 Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is
also used in multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower
nibble (i.e. D0 D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to

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D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform
Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1‟s, the Parity Flag is set and for odd number of 1‟s, the Parity
Flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
 Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set.
 Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates
that the result has exceeded the capacity of machine.

Control Flags:

Control flags are set or reset deliberately to control the operations of the execution unit. Control flags
are as follows:

 Trap Flag (TP):

a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
 Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI instruction.
 Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower memory
address.
c. When it is reset, the string bytes are accessed from lower memory address to higher
memory address.

1.7 8086-Minimum mode of operation

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Fig 1.20 Minimum mode of 8086

1.7.1 Minimum Mode Interface

 Address/Data bus: 20 bits vs 8 bits multiplexed

 Status signals: A16-A19 multiplexed with status signals S3-S6 respectively
a. S3 and S4 together form a 2 bit binary code that identifies which of the internal segment
registers was used to generate the physical address that was output on the address bus
during the current bus cycle.
b. S5 is the logic level of the internal interrupt enable flag, s6 is always logic 0.

Control Signals:

 Address Latch Enable (ALE) is a pulse to logic 1 that signals external circuitry when a valid
address is on the bus. This address can be latched in external circuitry on the 1-to-0 edge of the
pulse at ALE.
 IO/M line: memory or I/O transfer is selected (complement for 8086)
 DT/R line: direction of data is selected
 SSO (System Status Output) line: =1 when data is read from memory and =0 when code is
read from memory (only for 8088)
 BHE (Bank High Enable) line : =0 for most significant byte of data for 8086 and also carries
S7
 RD line: =0 when a read cycle is in progress
 WR line: =0 when a write cyle is in progress
 DEN line: (Data enable) Enables the external devices to supply data to the processor.
 Ready line: can be used to insert wait states into the bus cycle so that it is extended by a number
of clock periods

Interrupt signals:

 INTR (Interrupt request) :=1 shows there is a service request, sampled at the final clock cycle
of each instruction acquisition cycle.
 INTA : Processor responds with two pulses going to 0 when it services the interrupt and waits
for the interrupt service number after the second pulse.
 TEST: Processor suspends operation when =1. Resumes operation when=0. Used to syncronize
the processor to external events.
 NMI (Nonmaskable interrupt) : A leading edge transition causes the processor go to the
interrupt routine after the current instruction is executed.
 RESET : =0 Starts the reset sequence.

1.7.2 Maximum Mode Interface

 For multiprocessor environment 8288 Bus Controller is used for bus control
 WR¯ ,IO/M¯ ,DT/R¯ ,DEN¯ ,ALE, INTA¯ signals are not available
 Instead
a. MRDC¯ (memory read command)
b. MWRT¯ (memory write command)
c. AMWC¯ (advanced memory write command)
d. IORC¯ (I/O read command)
e. IOWC¯ (I/O write command)
f. AIOWC¯ (Advanced I/O write command)
g. INTA¯ (interrupt acknowledge)
 The signals shown above are produced by 8288 depending on the state of S0, S1 and S2.

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a. DEN, DT/R¯ and ALE signals are the same as minimum-mode systems
b. LOCK¯ : when =0, prevents other processors from using the bus
c. QS0 and QS1 (queue status signals): informs about the status of the queue
d. RQ¯ /GT ¯ 0 and RQ¯ /GT ¯ 1 are used instead of HOLD and HLDA lines in a
multiprocessor environment as request/grant lines.

Fig 1.21 Maximum Mode Interface

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Fig 1.22 Block and Pin Diagram of 8288 Bus controller

2. I/O Ports

There are two methods in which I/O devices can be connected to the Microprocessor.

 Memory mapped I/O

 I/O mapped I/O

Memory mapped I/O:

In this method I/O device is treated like the memory. Here there is no IO/M signal. If the
processor wants to read the data from a I/O device it will place the address of the I/O device on the
address bus. Then the I/O device will get selected. The memory which is having the same address
will also get selected.so we have to use separate address for memory and separate address for I/O
device.

I/O mapped I/O:

Here we have the IO/M signal. So we can select either the memory or I/O device for read
and write operation.

2.4 Data Transfer Concepts

 Parallel data transfer

 Serial data transfer

I. Parallel data transfer

 Programmed I/O
 Interrupt I/O
 DMA

Programmed I/O:

Here the processor has to check whether the I/O device is ready or not through the Ready
signal of the I/O device. If the ready signal is high then it will send the data to the I/O device. Otherwise
it will continuously check the Ready signal. The processor is busy in checking the Ready signal. The

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drawback is wastage of time.

Interrupt I/O:

In this method the I/O device will interrupt the Processor through the INTR signal to indicate
to the processor that it is ready to accept the next data. Then the processor will send the INTA signal.
Then the processor stops its normal execution and start transferring the data to the I/O device.

DMA:

Using DMA I/O device can directly transfer the data to the Memory using the Address and Data
buses of Processor.

II. Serial data Transfer

Some of the external I/0 devices receive only the serial data. Normally serial communication is used
in the MultiProcessor environment. 8051 has two pins for serial communication.

 SID- Serial Input data.

 SOD-Serial Output data.

Interrupts

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of the
POPF instruction.

When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts,
fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine
address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return
with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt
type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This
interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
 INTO instruction - interrupt on overflow
 Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.

Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).

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UNIT - 2

PROGRAMMING OF 8085 PROCESSOR

2.1 Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified data.

Each instruction has two parts: one is task to be performed, called the operation code (opcode), and the
second is the data to be operated on, called the operand. The operand (or data) can be specified in various
ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit)
address. In some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according to word size:

 One-word or 1-byte instructions

 Two-word or 2-byte instructions
 Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.

2.1.1 One-Byte Instructions

A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal
register and are coded into the instruction

Table 2.1 Example for 1 byte Instruction

These instructions are 1-byte instructions performing three different tasks. In the first instruction,
both operand registers are specified. In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit
operand. These instructions are stored in 8- bit binary format in memory; each requires one memory
location.

MOV rd, rs

rd  rs copies contents of rs into rd.

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Coded as 01 ddd sss

where ddd is a code for one of the 7 general registers which is the destination of the data, sss is the code
of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such
processors).

ADD r

AA+r

2.1.2 Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. Source operand is a data byte immediately following the opcode. For example:

Table 2.2 Example for 2 byte Instruction

The instruction would require two memory locations to store in memory.

MVI r,data

r  data

Example: MVI A,30H coded as 3EH 30H as two contiguous bytes.

This is an example of immediate addressing.

ADI data

A  A + data

OUT port

0011 1110

DATA

Where port is an 8-bit device address. (Port)  A.

Since the byte is not the data but points directly to where it is located this is called direct addressing.

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2.1.3 Three-Byte Instructions

In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify
the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order
address.

opcode + data byte + data byte

Table 3.3 Example for 3 byte Instruction

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are 16-bit data
in L H order of significance.

rp  data16

LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.

LDA addr

A  (addr) Addr is a 16-bit address in L H order.

Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing.

2.2 The 8085 Addressing Modes

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In
these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly,
a destination can be a register or an output port. The sources and destination are operands. The various
formats for specifying operands are called the ADDRESSING MODES. For 8085, they are:

 Immediate addressing.
 Register addressing.
 Direct addressing.
 Indirect addressing.

Immediate addressing:

Data is present in the instruction. Load the immediate data to the destination provided.

Example: MVI R,data

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Register addressing:

Data is provided through the registers.

Example: MOV Rd, Rs

Direct addressing:

Used to accept data from outside devices to store in the accumulator or send the data stored in
the accumulator to the outside device. Accept the data from the port 00H and store them into the
accumulator or Send the data from the accumulator to the port 01H.

Example: IN 00H or OUT 01H

Indirect Addressing:

This means that the Effective Address is calculated by the processor. And the contents of the
address (and the one following) is used to form a second address. The second address is where the data
is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address
and a further access (or accesses) to retrieve the data which is to be loaded into the register.

2.3 Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a specific

function. The entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. These instructions can be classified into the following five functional
categories: data transfer (copy) operations, arithmetic operations, logical operations, branching
operations, and machine-control operations.

2.3.1 Data Transfer Croup

The data transfer instructions move data between registers or between memory and registers.

MOV Move

MVI Move Immediate

LDA Load Accumulator Directly from Memory

STA Store Accumulator Directly in Memory

LHLD Load H & L Registers Directly from Memory

SHLD Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits);

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair

STAX Store Accumulator in Address in Register Pair

XCHG Exchange H & L with D & E

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XTHL Exchange Top of Stack with H & L

2.3.2 Arithmetic Group

The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.

ADD Add to Accumulator

ADI Add Immediate Data to Accumulator

ADC Add to Accumulator Using Carry Flag

ACI Add immediate data to Accumulator Using Carry

SUB Subtract from Accumulator

SUI Subtract Immediate Data from Accumulator

SBB Subtract from Accumulator Using Borrow (Carry) Flag

SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag

INR Increment Specified Byte by One

DCR Decrement Specified Byte by One

INX Increment Register Pair by One

DCX Decrement Register Pair by One

DAD Double Register Add; Add Content of Register

Pair to H & L Register Pair

2.3.3 Logical Group

This group performs logical (Boolean) operations on data in registers and memory and on
condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in
the accumulator ON or OFF.

ANA Logical AND with Accumulator

ANI Logical AND with Accumulator Using Immediate Data

ORA Logical OR with Accumulator

OR Logical OR with Accumulator Using Immediate Data

XRA Exclusive Logical OR with Accumulator

XRI Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;

CMP Compare

CPI Compare Using Immediate Data

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The rotate instructions shift the contents of the accumulator one bit position to the left or right:

RLC Rotate Accumulator Left

RRC Rotate Accumulator Right

RAL Rotate Left Through Carry

RAR Rotate Right Through Carry

Complement and carry flag instructions:

CMA Complement Accumulator

CMC Complement Carry Flag

STC Set Carry Flag

2.3.4 Branch Group

The branching instructions alter normal sequential program flow, either unconditionally or
conditionally. The unconditional branching instructions are as follows:

JMP Jump

CALL Call

RET Return

Conditional branching instructions examine the status of one of four condition flags to determine
whether the specified branch is to be executed. The conditions that may be specified are as follows:

NZ Not Zero (Z = 0)

Z Zero (Z = 1)

NC No Carry (C = 0)

C Carry (C = 1)

PO Parity Odd (P = 0)

PE Parity Even (P = 1)

P Plus (S = 0)

M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns

INC CNC RNC (No Carry)

JNZ
C CNZ
CC RNZ
RC (Not Zero)
(Carry)

JZ CZ RZ (Zero)
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JM CM RM (Minus)

JP0 CPO RPO (Parity Odd)

JPE CPE RPE (Parity Even)
JM CM RM (Minus)

JPE CPE RPE (Parity Even)

JP0 CPO RPO (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program counter:

PCHL Move H & L to Program Counter

RST Special Restart Instruction Used with Interrupts

2.3.5 Stack Instructions

The following instructions affect the Stack and/or Stack Pointer

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack

XTHL Exchange Top of Stack with H & L

SPHL Move content of H & L to Stack Pointer

2.3.6 I/0 instructions

IN Initiate Input Operation

OUT Initiate Output Operation

2.3.7 Machine Control instructions

EI Enable Interrupt System

DI Disable Interrupt System

HLT Halt

NOP No Operation

2.4 Sample Program

(1)Write an assembly program to add two numbers Program

MVI D, 8BH MVI C, 6FH MOV A, C

1100 0011

1000 0101

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0010 0000

ADD D

OUT PORT1

HLT

(2)Write an assembly program to multiply a number by 8 Program

MVI A, 30H RRC

RRC RRC

OUT PORT1

HLT

(3)Write an assembly program to find greatest between two numbers Program

MVI B, 30H MVI C, 40H MOV A, B CMP C

JZ EQU JC GRT

OUT PORT1

HLT

EQU: MVI A, 01H OUT PORT1

HLT

GRT: MOV A, C OUT PORT1

HLT

2.5 Programming using Loop structure with Counting and Indexing

(i) 16 bit Multiplication

ADDRESS LABEL MNEMONICS OPCODE

START LHLD 4200

SPHL

LHLD 4202

XCHG

LXI H,0000

L1 LXI B,0000

DAD SP

JNC L2

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INX B

L2 DCX D

MOV A,E

ORA D

JNZ L1

SHLD 4204

MOV L,C

MOV H,B

SHLD 4206

HLT

(ii)Finding the maximum number in the given array

ADDRESS LABEL MNEMONICS OPCODE

START LDA 4500

MOV C, A

LXI H, 4501

L2 MOV A, M

L3 DCR C

INX H

JZ L1

CMP M

JC L2

JMP L3

L1 STA 4520

HLT

(iii) To sort the array of data in ascending order

ADDRESS LABEL MNEMONICS OPCODE

START

L3 MVI B, 00

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LXI H, 4200

MOV C, M

DCR C

INX H

L2 MOV A, M

INX H

CMP M

JC L1

MOV D, M

MOV M, A

DCX H

MOV M, D

INX H

MVI B, 01

L1 DCR C

JNZ L2

DCR B

JZ L3

HLT

2.6 Programming using subroutine Instructions

Generation of Square waveform using DAC

ADDRESS LABEL MNEMONICS OPCODE

START MVI A,00H

OUT C8

CALL DELAY

MVI A,FF

OUT C8

CALL DELAY

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JMP START

MVI B,05H

MVI C,FF

DELAY DCR C

L2 JNZ L1

L1 DCR B

JNL L2

RET

2.7 Programming using Look up table

ADDRESS LABEL MNEMONICS OPCODE

START MVI B,08

MVI A,00 (DISPLAY MODE SETUP)

OUT C2

MVI A,CC (CLEAR DISPLAY)

OUT C2

MVI A,90 (WRITE DISPLAY RAM)

OUT C2

MVI A, FF (CLEAR DISPLAY RAM)

OUT C0

DCR B

JNZ L1

IN C2

L2 ANI 07

JZ L2

MVI A, 40 (SET TO READ FIFO RAM)

OUT C2

IN C0

ANI 0F

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MOV L, A

MVI H, 42

MOV A, M

OUT C0

JMP L2

LOOKUP TABLE

4200 0C 9F 4A 0B

4204 99 29 28 8F

4208 08 09 88 38

420C 6C 1A 68 E8

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UNIT - 3

PERIPHERAL INTERFACING

3.1 Programmable peripheral interface (8255)

3.1.1 Architecture of 8255

The parallel input-output port chip 8255 is also called as programmable peripheral input- output
port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors.
It has 24 input/output lines which may be individually programmed in two groups of twelve lines each,
or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of
these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four
lines or a 4-bit port.

Thus Group A contains an 8-bit port A along with a 4-bit port. C upper. The port A lines are
identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B
contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The
port C upper and port C lower can be used in combination as an 8-bit port C. Both the port C are assigned
the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from
8255. All of these ports can function independently either as input or as output ports. This can be
achieved by programming the bits of an internal register of 8255 called as control word register (CWR).
This buffer receives or transmits data upon the execution of input or output instructions by the
microprocessor. The control words or status information is also transferred through the buffer.

Fig 3.1 8255 Architecture

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3.1.2 Pin Diagram of 8255

Fig 3.2 Pin Diagram of 8255

The signal description of 8255 are briefly presented as follows:

 PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
 PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers lines.
This port also can be used for generation of handshake lines in mode 1 or mode 2.
 PC3-PC0: These are the lower port C lines, other details are the same as PC7-PC4 lines.
 PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered input
lines in the same way as port A.
 RD: This is the input line driven by the microprocessor and should be low to indicate read operation
to 8255.
 WR: This is an input line driven by the microprocessor. A low on this line indicates write operation.
 CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR
signals, otherwise RD and WR signal are neglected.
 A1-A0: These are the address input lines and are driven by the microprocessor. These lines A1-A0
with RD, WR and CS from the following operations for 8255. These address lines are used for
addressing any one of the four registers, i.e. three ports and a control word register as given in table
below. In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and
A1 pins of 8255 are connected with A1 and A2 respectively.
 D0-D7: These are the data bus lines those carry data or control word to/from the microprocessor.
 RESET: A logic high on this line clears the control word register of 8255. All ports are set as input
ports by default after reset.

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3.1.3 Operational Modes of 8255

There are two main operational modes of 8255:

 Input/output mode
 Bit set/reset mode

3.1.3.1 Input / Output Mode

There are three types of the input/output mode. They are as follows:

Mode 0

In this mode, the ports can be used for simple input/output operations without handshaking. If
both port A and B are initialized in mode 0, the two halves of port C can be either used together as an
additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are
independent, they may be used such that one-half is initialized as an input port while the other half is
initialized as an output port. The input output features in mode 0 are as follows:

 O/p are latched.

 I/p are buffered not latched.
 Port do not have handshake or interrupt capability.

Mode 1

When we wish to use port A or port B for handshake (strobed) input or output operation, we
initialize that port in mode 1 (port A and port B can be initialized to operate in different modes, ie, for
eg., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C function as handshake
lines.

For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,
PC1 and PC2 pins function as handshake lines. If port A is initialized as mode 1 input port, then, PC3,
PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output
lines. The mode 1 which supports handshaking has following features: 1.

Two ports i.e. port A and B can be used as 8-bit I/O port. 2. Each port uses three lines of port c
as handshake signal and remaining two signals can be function as I/O port. 3. Interrupt logic is supported.
4. Input and Output data are latched.

Mode 2

Only group A can be initialized in this mode. Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 -
PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can be used as
input/output lines if group B is initialized in mode 0. In this mode, the 8255 may be used to extend the
system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller.

3.1.3.2 Bit Set/Reset (BSR) mode

In this mode only port b can be used (as an output port). Each line of port C (PC0 - PC7) can be
set/reset by suitably loading the command word register.no effect occurs in input-output mode. The
individual bits of port c can be set or reset by sending the signal OUT instruction to the control register.

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3.1.4 Control Word Format

3.1.4.1 Input/output mode format

Fig 3.3 Control Word format for Input/Output Mode

 The figure shows the control word format in the input/output mode. This mode is selected by making
D7 = '1' .
 D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively. When D0 or D1
or D3 or D4 are "SET", the corresponding ports act as input ports. For eg, if D0 = D4 = '1', then
lower port C and port A act as input ports. If these bits are "RESET", then the corresponding ports
act as output ports. For eg, if D1 = D3 = '0', then port B and upper port C act as output ports.
 D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0', mode 0 is
selected and when D2 = '1', mode 1 is selected.
 D5, D6 are used for mode selection for group A (Upper Port C and Port A). The format is as follows:

D6 D5 Mode

0 0 0

0 1 1

1 X 2

3.1.4.2 BSR mode format

 Control Word format in BSR mode

 The figure shows the control word format in BSR mode. This mode is selected by making
D7='0'.
 D0 is used for bit set/reset. When D0= '1', the port C bit selected (selection of a port C bit is
shown in the next point) is SET, when D0 = '0', the port C bit is RESET.
 D1, D2, D3 are used to select a particular port C bit whose value may be altered using D0 bit as
mentioned above.

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Fig 3.4 Control Register format in BSR mode

B2 B1 B0 PC Bit Control Word (Set) Control Word (Reset)
0 0 0 0 0000 0001 = 01h 0000 0000 = 00h
0 0 1 1 0000 0011 = 03h 0000 0010 = 02h
0 1 0 2 0000 0101 = 05h 0000 0100 = 04h
0 1 1 3 0000 0111 = 07h 0000 0110 = 06h
1 0 0 4 0000 1001 = 09h 0000 1000 = 08h
1 0 1 5 0000 1011 = 0Bh 0000 1010 = 0Ah
1 1 0 6 0000 1101 = 0Dh 0000 1100 = 0Ch
1 1 1 7 0000 1111 = 0Fh 0000 1110 = 0Eh

 The selection of the port C bits are done as follows:

D3 D2 D1 Bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

 D4, D5, D6 are not used.

3.2Programmable Interrupt Controller (8259)

3.2.1 Features

 8 levels of interrupts.
 Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
 Internal priority resolver.
 Fixed priority mode and rotating priority mode.
 Individually maskable interrupts.
 Modes and masks can be changed dynamically.
 Accepts IRQ, determines priority, checks whether incoming priority > current level being
serviced, issues interrupt signal.

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 In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector number.
 Polled and vectored mode.
 Starting address of ISR or vector number is programmable.
 No clock required.

3.2.2 Pinout

Fig 3.5 Pin Diagram of 8259

Table 3.1 Pin Description of 8259

Bi-directional, tristated, buffered data lines. Connected to data bus directly or

D0-D7
through buffers

RD-bar Active low read control

WR-bar Active low write control

A0 Address input line, used to select control register

CS-bar Active low chip select

Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these
CAS0-2 lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may
be regarded as slave-select.

SP-bar /EN- Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish
bar master/slave PIC. In buffered mode, it is output line used to enable buffers

INT Interrupt line, connected to INTR of microprocessor

INTA-bar Interrupt ack, received active low from microprocessor

IR0-7 Asynchronous IRQ input lines, generated by peripherals.

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3.2.3 Block diagram

Fig 3.6 Block Diagram of 8259

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

 D0: IC4: 0=no ICW4, 1=ICW4 required

 D1: SNGL: 1=Single PIC, 0=Cascaded PIC
 D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204,
etc) 0=ISR's are 8 byte apart (0200, 0208, etc)

D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment.

The lower byte is of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are
provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself:

A7 A6 A5 A4 A3 A2 A1 A0

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ADI=1 (spacing 4 bytes)

IRQ A7 A6 A5 A4 A3 A2 A1 A0

IR0 A7 A6 A5 0 0 0 0 0

IR1 A7 A6 A5 0 0 1 0 0

IR2 A7 A6 A5 0 1 0 0 0

IR3 A7 A6 A5 0 1 1 0 0

IR4 A7 A6 A5 1 0 0 0 0

IR5 A7 A6 A5 1 0 1 0 0

IR6 A7 A6 A5 1 1 1 0 0

IR7 A7 A6 A5 1 1 1 0 0

ADI=0 (spacing 8 bytes)

IRQ A7 A6 A5 A4 A3 A2 A1 A0

IR0 A7 A6 0 0 0 0 0 0

IR1 A7 A6 0 0 1 0 0 0

IR2 A7 A6 0 1 0 0 0 0

IR3 A7 A6 0 1 1 0 0 0

IR4 A7 A6 1 0 0 0 0 0

IR5 A7 A6 1 0 1 0 0 0

IR6 A7 A6 1 1 0 0 0 0

IR7 A7 A6 1 1 1 0 0 0

ICW2 (Initialization Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

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ICW3 (Initialization Command Word Three)

D7 D6 D5 D4 D3 D2 D1 D0
A0
Master S7 S6 S5 S4 S3 S2 S1 S0
1
Slave 0 0 0 0 0 ID3 ID2 ID1

 Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt
 Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000 0100)

ICW4 (Initialization Command Word Four)

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI Mode

 SFNM: 1=Special Fully Nested Mode, 0=FNM

 M/S: 1=Master, 0=Slave
 AEOI: 1=Auto End of Interrupt, 0=Normal
 Mode: 0=8085, 1=8086

OCW1 (Operational Command Word One)

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)

OCW2 (Operational Command Word Two)

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 R SL EOI 0 0 L3 L2 L1

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R SL EOI Action

0 0 1 Non specific EOI (L3L2L1=000)

EOI
Specific EOI command (Interrupt to clear
0 1 1
given by L3L2L1)

1 0 1 Rotate priorities on non-specific EOI

Auto rotation of priorities (L3L2L1=000) 1 0 0 Rotate priorities in auto EOI mode set

0 0 0 Rotate priorities in auto EOI mode clear

Rotate priority on specific EOI command

1 1 1
(resets current ISR bit)

Specific rotation of priorities (Lowest

priority ISR=L3L2L1) 1 1 0 Set priority (does not reset current ISR bit)

0 1 0 No operation

OCW3 (Operational Command Word Three)

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 D7 ESMM SMM 0 1 MODE RIR RIS

ESMM SMM Effect

0 X No effect

1 0 Reset special mask

1 1 Set special mask

Interrupt sequence (single PIC)

 One or more of the IR lines goes high.

 Corresponding IRR bit is set.
 8259 evaluates the request and sends INT to CPU.

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 CPU sends INTA-bar.

 Highest priority ISR is set. IRR is reset.
 8259 releases CALL instruction on data bus.
 CALL causes CPU to initiate two more INTA-bar's.
 8259 releases the subroutine address, first lowbyte then highbyte.
 ISR bit is reset depending on mode.

3.3 8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

(USART)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication. As a peripheral device of a microcomputer system, the 8251receives parallel data
from the CPU and transmits serial data after conversion. This device also receives serial data from the
outside and transmits parallel data to the CPU after conversion.

3.3.1 Block Diagram of 8251

Fig 3.7 Block diagram of the 8251 USART (Universal Synchronous Asynchronous
Receiver Transmitter)

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3.3.2 Control Words

There are two types of control word.

 Mode instruction (setting of function)

 Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write"
at either internal reset or external reset. That is, the writing of a control word after resetting will be
recognized as a "mode instruction."

Items set by mode instruction are as follows:

 Synchronous/asynchronous mode
 Stop bit length (asynchronous mode)
 Character length
 Parity bit
 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)
 Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 3.8 and 3.9. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were
written, a function will be set because the writing of sync characters constitutes part of mode instruction.

Fig 3.8 Bit Configuration of Mode Instruction (Asynchronous)

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Fig 3.9 Bit Configuration of Mode Instruction (synchronous)

2) Command

Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

 Transmit Enable/Disable
 Receive Enable/Disable
 DTR, RTS Output of data.
 Resetting of error flag.
 Sending to break characters
 Internal resetting
 Hunt mode (synchronous mode)

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Fig 3.10 Bit Configuration of Command

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3.3.3 Status Word

It is possible to see the internal status of the 8251 by reading a status word.

Fig 3.11 Bit Configuration of Status Word

3.4 Programmable Keyboard/Display Interface - 8279

A programmable keyboard and display interfacing chip. Scans and encodes up to a 64-key
keyboard. Controls up to a 16-digit numerical display. Keyboard section has a built-in FIFO 8 character
buffer. The display is controlled from an internal 16x8 RAM that stores the coded display information.

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3.4.1 Pinout Definition 8279

Fig 3.12 Pin Diagram of 8279

 A0: Selects data (0) or control/status (1) for reads and writes between micro and 8279.
 BD: Output that blanks the displays.
 CLK: Used internally for timing. Max is 3 MHz.
 CN/ST: Control/strobe, connected to the control key on the keyboard
 CS: Chip select that enables programming, reading the keyboard, etc.
 DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.
 IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
 OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant nibble of
display.
 RD(WR): Connects to micro's IORC or RD signal, reads data/status registers.
 RESET: Connects to system RESET.
 RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix.
 Shift: Shift connects to Shift key on keyboard.
 SL3-SL0: Scan line outputs scan both the keyboard and displays.

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3.4.2 Block Diagram of 8279

Fig 3.13 Block Diagram of 8279

Display section:

 The display section has eight output lines divided into two groups A0-A3 and B0-B3.
 The output lines can be used either as a single group of eight lines or as two groups of four lines,
in conjunction with the scan lines for a multiplexed display.
 The output lines are connected to the anodes through driver transistor in case of common cathode
7-segment LEDs.
 The cathodes are connected to scan lines through driver transistors.
 The display can be blanked by BD (low) line.
 The display section consists of 16 x 8 display RAM. The CPU can read from or write into any
location of the display RAM.

Scan section:

 The scan section has a scan counter and four scan lines, SL0 to SL3.
 In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
 In encoded scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output.
 The scan lines are common for keyboard and display.
 The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers
of a multiplexed display, to turn ON/OFF.

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CPU interface section:

 The CPU interface section takes care of data transfer between 8279 and the processor.
 This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and
CPU. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting
control register of8279.
 The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
 It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
 The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the
input clock by an internal prescaler.
 The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

3.4.2 Keyboard Interface of 8279

The keyboard matrix can be any size from 2x2 to 8x8.Pins SL2-SL0 sequentially scan each
column through a counting operation. The 74LS138 drives 0's on one line at a time. The 8279 scans RL
pins synchronously with the scan. RL pins incorporate internal pull-ups, no need for external resistor
pull-ups. The 8279 must be programmed first.

First three bits given below select one of 8 control registers (opcode).

000DDMMM

Mode set: Opcode 000.

DD sets displays mode.

MMM sets keyboard mode.

DD field selects either:

 8- or 16-digit display
 Whether new data are entered to the rightmost or leftmost display position.

MMM Field:

DD Function
000 Encoded keyboard with 2 key lockout
001 Decoded keyboard with 2 key lockout
010 Encoded keyboard with N key rollover
011 Decoded keyboard with N key rollover
100 Encoded sensor matrix
101 Decoded sensor matrix
110 Strobed keyboard, encoded display scan
111 Strobed keyboard, decoded display scan

Encoded: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15.

Decoded: SL outputs are active-low (only one low at any time).

Pattern output: 1110, 1101, 1011, 0111.

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Strobed: An active high pulse on the CN/ST input pin strobes data from the RL pins into an internal
FIFO for reading by micro later.

2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed

simultaneously/Accepts all keys pressed from 1st to last.

Fig 3.13 Keyboard Interface of 8279

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Fig 3.14 Display Interface of 8279

3.5 ADC Interfacing with 8085 Microprocessor

3.5.1 Features

Fig 3.15 Pin Diagram of ADC 0809

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 The ADC0809 is an 8-bit successive approximation type ADC with inbuilt 8-channel
multiplexer.
 The ADC0809 is suitable for interface with 8086 microprocessor.
 The ADC0809 is available as a 28 pin IC in DIP (Dual Inline Package).
 The ADC0809 has a total unadjusted error of ±1 LSD (Least Significant Digit).
 The ADC0808 is also same as ADC0809 except the error. The total unadjusted error in ADC0808
is ± 1/2 LSD.

3.5.2 Block Diagram of ADC 0809

Fig 3.16 Block Diagram of ADC 0809

The successive approximation register (SAR) performs eight iterations to determine the digital
code for input value. The SAR is reset on the positive edge of START pulse and start the conversion
process on the falling edge of START pulse. A conversion process will be interrupted on receipt of new
START pulse. The End-Of-Conversion (EOC) will go low between 0 and 8 clock pulses after the
positive edge of START pulse. The ADC can be used in continuous conversion mode by tying the EOC
output to START input. In this mode an external START pulse should be applied whenever power is
switched ON. The 256R ladder network has been provided instead of conventional R/2R ladder because
of its inherent monotonic, which guarantees no missing digital codes. Also the 256R resistor network
does not cause load variations on the reference voltage.

The comparator in ADC0809/ADC0808 is a chopper- stabilized comparator. It converts the DC

input signal into an AC signal, and amplifies the AC sign using high gain AC amplifier. Then it converts
AC signal to DC signal. This technique limits the drift component of the amplifier, because the drift is
a DC component and it is not amplified/passed by the AC amp1ifier. This makes the ADC extremely
insensitive to temperature, long term drift and input offset errors. In ADC conversion process the input

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analog value is quantized and each quantized analog value will have a unique binary equivalent. The
quantization step in ADC0809/ADC0808 is given by,

PROGRAM

ADDRESS MNEMONICS OPCODE DESCRIPTION

MVI A,10 Channel 0 select

OUT 0C8 H ALE Low

MVI A,18 Channel 0, select

OUT 0C8 H ALE High

HLT

3.6 DAC Interfacing with 8085 Microprocessor

3.6.1 DAC 0800 Features

 To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be
employed.
 The DAC will accept a digital (binary) input and convert to analog voltage or current.
 Every DAC will have "n" input lines and an analog output.
 The DAC require a reference analog voltage (Vref) or current (Iref) source.
 The smallest possible analog value that can be represented by the n-bit binary code is called
resolution.
 The resolution of DAC with n-bit binary input is 1/2nof reference analog value.

3.6.2 Circuit Diagram of DAC 0800

 The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time
(conversion time) of 100 ns.
 It produces complementary current output, which can be converted to voltage by using simple
resistor load.
 The DAC0800 require a positive and a negative supply voltage in the range of ± 5V to ±18V.

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Fig 3.17 Circuit Diagram of DAC 0800

 It can be directly interfaced with TTL, CMOS, PMOS and other logic families.
 For TTL input, the threshold pin should be tied to ground (VLC = 0V).
 The reference voltage and the digital input will decide the analog output current, which can be
converted to a voltage by simply connecting a resistor to output terminal or by using an op-amp
I to V converter.
 The DAC0800 is available as a 16-pin IC in DIP.

Table 3.2 ADC Conversion Table

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Square Wave Generation Using DAC 0800

ADDRESS LABEL MNEMONICS OPCODE

START MVI A,00H

OUT C8

CALL DELAY

MVI A,FF

OUT C8

CALL DELAY

JMP START

MVI B,05H

MVI C,FF

DELAY DCR C

L2 JNZ L1

DCR B

L1 JNL L2

RET

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UNIT - 4

8051 MICRO CONTROLLER

4.1 Architecture of 8051

Fig 4.1 Architecture of 8051

4.1.1 Memory Organization

 Logical separation of program and data memory

 Separate address spaces for Program (ROM) and Data (RAM) Memory
 Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU

Program Memory

 Only be read, not written to

 The address space is 16-bit, so maximum of 64K bytes
 Up to 4K bytes can be on-chip (internal) of 8051 core
 PSEN (Program Store Enable) is used for access to external Program Memory

Data Memory

 Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its
instructions
 There is also a number of Special Function Registers (SFRs)
 Internal Data Memory contains four banks of eight registers and a special 32- byte long segment
which is bit addressable by 8051 bit-instructions
 External memory of maximum 64K bytes is accessible by “movx”

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Fig 4.2 Internal data Memory

4.1.2 Interrupt Structure

 The 8051 provides 4 interrupt sources

 Two external interrupts
 Two timer interrupts

4.1.3 Port Structure

 The 8051 contains four I/O ports

 All four ports are bidirectional
 Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an
output driver and an input buffer
 Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing
external memory
 Accessing external memory works like this
 Port 0 outputs the low byte of external memory address (which is time- multiplexed with the
byte being written or read)
 Port 2 outputs the high byte (only needed when the address is 16 bits wide)
 Port 3 pins are multifunctional
 The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

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Table 4.1 Alternate Functions of Port 3 pins

4.1.4 Timer/Counter

 The 8051 has two 16-bit Timer/Counter registers

1. Timer 0
2. Timer 1
 Both can work either as timers or event counters
 Both have four different operating modes

4.2 Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified data.

Each instruction has two parts: one is task to be performed, called the operation code (opcode), and the
second is the data to be operated on, called the operand. The operand (or data) can be specified in
various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or
16-bit) address. In some instructions, the operand is implicit.

Instruction word size

The 8051 instruction set is classified into the following three groups according to word size:

 One-word or 1-byte instructions

 Two-word or 2-byte instructions
 Three-word or 3-byte instructions

4.2.1 One-Byte Instructions

A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal
register and are coded into the instruction.

These instructions are 1-byte instructions performing three different tasks. In the first instruction,
both operand registers are specified. In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit
operand. These instructions are stored in 8- bit binary format in memory; each requires one memory
location.

4.2.2 Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. Source operand is a data byte immediately following the opcode.

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4.2.3 Three-Byte Instructions

In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify
the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order
address.

4.3 Addressing Modes of 8051

The 8051 provides a total of five distinct addressing modes.

 immediate
 register
 direct
 register indirect
 indexed

Immediate Addressing Mode

 The operand comes immediately after the op-code.

 The immediate data must be preceded by the pound sign, "#".

Register Addressing Mode

Register addressing mode involves the use of registers to hold the data to be manipulated

Direct Addressing Mode

 It is most often used to access RAM locations 30 - 7FH.

 This is due to the fact that register bank locations are accessed by the register names of R0 - R7.
 There is no such name for other RAM locations so must use direct addressing
 In the direct addressing mode, the data is in a RAM memory location whose address is known,
and this address is given as a part of the instruction

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Register Indirect Addressing Mode

 A register is used as a pointer to the data.

 If the data is inside the CPU, only registers R0 and R 1 are used for this purpose.
 R2 - R7 cannot be used to hold the address of an operand located in RAM when using indirect
addressing mode.
 When RO and R 1 are used as pointers they must be preceded by the@ sign.

Indexed Addressing Mode

 Indexed addressing mode is widely used in accessing data elements of look-up table entries
located in the program ROM space of the 8051.
 The instruction used for this purpose is : MOVC A, @ A+DPTR
 The 16-bit register DPTR and register A are used to form the address of the data element stored
in on-chip ROM.
 Because the data elements are stored in the program (code) space ROM of the 8051, the
instruction MOVC is used instead of MOV. The "C" means code.
 In this instruction the contents of A are added to the 16-bit register DPTR to form the 16- bit
address of the needed data.

4.4 Interrupt Structure

 8051 provides 4 interrupt sources

1. 2 external interrupts
2. 2 timer interrupts
 They are controlled via two SFRs, IE and IP
 Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE
(Interrupt Enable). IE also exists a global disable bit, which can be cleared to disable all
interrupts at once
 Each interrupt source can also be individually set to one of two priority levels by setting or
clearing a bit in IP (Interrupt Priority)
 A low-priority interrupt can be interrupted by high-priority interrupt, but not by another low-
priority one
 A high-priority interrupt can‟t be interrupted by any other interrupt source
 If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced, so within each priority lever there is a second
priority structure
 This internal priority structure is determined by the polling sequence, shown in the
following table

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Table 4.2 Interrupt Priority Level

4.4.1 External Interrupt

 External interrupts ~INT0 and ~INT1 have two ways of activation

1. Level-activated
2. Transition-activated
 This depends on bits IT0 and IT1 in TCON
 The flags that actually generate these interrupts are bits IE0 and IE1 in TCON
 On-chip hardware clears that flag that generated an external interrupt when the service routine
is vectored to, but only if the interrupt was transition-activated
 When the interrupt is level-activated, then the external requesting source is controlling the
request flag, not the on-chip hardware

4.4.2 Handling Interrupt

 When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set
(1)), the interrupt system generates an LCALL to the appropriate location in Program Memory,
unless some other conditions block the interrupt
 Several conditions can block an interrupt
 An interrupt of equal or higher priority level is already in progress
 The current (polling) cycle is not the final cycle in the execution of the instruction in progress
 The instruction in progress is RETI or any write to IE or IP registers
 If an interrupt flag is active but not being responded to for one of the above conditions,
must be still active when the blocking condition is removed, or the denied interrupt will not be
serviced
 Next step is saving the registers on stack. The hardware-generated LCALL causes only the
contents of the Program Counter to be pushed onto the stack, and reloads the PC with the
beginning address of the service routine
 In some cases it also clears the flag that generated the interrupt, and in other cases it doesn‟t. It
clears an external interrupt flag (IE0 or IE1) only if it was transition- avtivated.
 Having only PC be automatically saved gives programmer more freedom to decide how
much time to spend saving other registers. Programmer must also be more careful with proper
selection, which register to save.
 The service routine for each interrupt begins at a fixed location. The interrupt locations are
spaced at 8-byte interval, beginning at 0003H for External Interrupt 0, 000BH for Timer 0,
0013H for External Interrupt 1 and 001BH for Timer 1.

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Fig 4.3 Interrupt Location in 8051 Program Memory

4.5 I/O Ports

 The 8051 contains four I/O ports

 All four ports are bidirectional
 Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an
output driver and an input buffer
 Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing
external memory
 Accessing external memory works like this
1. Port 0 outputs the low byte of external memory address (which is time- multiplexed
with the byte being written or read)
2. Port 2 outputs the high byte (only needed when the address is 16 bits wide)
 Port 3 pins are multifunctional
 The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

Table 4.3 Alternate Functions of Port 3 pins

4.6 Timers

The 8051 comes equipped with two timers, both of which may be controlled, set, read, and
configured individually. The 8051 timers have three general functions: 1) Keeping time and/or
calculating the amount of time between events, 2) Counting the events themselves, or 3) Generating
baud rates for the serial port.

One of the primary uses of timers is to measure time. We will discuss this use of timers first and
will subsequently discuss the use of timers to count events. When a timer is used to measure time it is
also called an "interval timer" since it is measuring the time of the interval between two events.

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4.6.1Timer SFR

8051 has two timers which each function essentially the same way. One timer is TIMER0 and
the other is TIMER1. The two timers share two SFRs (TMOD and TCON) which control the timers,
and each timer also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

Table 4.4 SFR

SFR Name Description SFR Address
TH0 Timer 0 High Byte 8Ch
TL0 Timer 0 Low Byte 8Ah
TH1 Timer 1 High Byte 8Dh
TL1 Timer 1 Low Byte 8Bh
TCON Timer Control 88h
TMOD Timer Mode 89h

4.6.2 13-bit Time Mode (mode 0)

Timer mode "0" is a 13-bit timer. This is a relic that was kept around in the 8051 to maintain
compatability with its predecesor, the 8048. Generally the 13-bit timer mode is not used in new
development.

When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is incremented from
31, it will "reset" to 0 and increment THx. Thus, effectively, only 13 bits of the two timer bytes are
being used: bits 0-4 of TLx and bits 0-7 of THx. This also means, in essence, the timer can only contain
8192 values. If you set a 13-bit timer to 0, it will overflow back to zero 8192 machine cycles later.

Again, there is very little reason to use this mode and it is only mentioned so you wont be
surprised if you ever end up analyzing archaeic code which has been passed down through the
generations (a generation in a programming shop is often on the order of about 3 or 4 months).

4.6.3 16-bit Time Mode (mode 1)

Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It functions just like 13-
bit mode except that all 16 bits are used.

TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes
THx to be incremented by 1. Since this is a full 16-bit timer, the timer may contain up to

65536 distinct values. If you set a 16-bit timer to 0, it will overflow back to 0 after 65,536
machine cycles.

4.6.4 8-bit Time Mode (mode 2)

Timer mode "2" is an 8-bit auto-reload mode. What is that, you may ask? Simple. When a
timer is in mode 2, THx holds the "reload value" and TLx is the timer itself. Thus, TLx starts counting
up. When TLx reaches 255 and is subsequently incremented, instead of resetting to 0 (as in the case
of modes 0 and 1), it will be reset to the value stored in THx.

4.6.5 Split Timer Mode (mode 3)

Timer mode "3" is a split-timer mode. When Timer 0 is placed in mode 3, it essentially becomes
two separate 8-bit timers. That is to say, Timer 0 is TL0 and Timer 1 is TH0. Both timers count
from 0 to 255 and overflow back to 0. All the bits that are related to Timer 1 will now be tied to TH0.

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While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be put into modes
0, 1 or 2 normally--however, you may not start or stop the real timer 1 since the bits that do that are
now linked to TH0. The real timer 1, in this case, will be incremented every machine cycle no matter
what.

4.6.6 Using Timers As Event Counters

We've discussed how a timer can be used for the obvious purpose of keeping track of time.
However, the 8051 also allows us to use the timers to count events.

How can this be useful? Let's say you had a sensor placed across a road that would send a pulse
every time a car passed over it. This could be used to determine the volume of traffic on the road.
We could attach this sensor to one of the 8051's I/O lines and constantly monitor it, detecting when it
pulsed high and then incrementing our counter when it went back to a low state. This is not terribly
difficult, but requires some code. Let's say we hooked the sensor to P1.0; the code to count cars
passing would look something like this:

JNB P1.0, $ ; If a car hasn't raised the signal, keep waiting

JB P1.0, $ ; The line is high which means the car is on the sensor right now

INC COUNTER ; The car has passed completely, so we count it

4.7 Serial Communication

Some of the external I/0 devices receive only the serial data. Normally serial communication is
used in the Multi-Processor environment.8051 has two pins for serial communication.

 SID- Serial Input data.

 SOD-Serial Output data.

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UNIT – 5

MICRO CONTROLLER PROGRAMMING & APPLICATIONS

5.1 Arithmetic Instructions

5.2 Logical Instructions

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5.3 Data Transfer Instructions that access the Internal Data Memory

5.4 Data Transfer Instructions that access the External Data Memory

5.5 Look up Tables

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5.6 Boolean Instructions

5.7 Jump Instructions

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5.8 Interfacing Keyboard to 8051 Microcontroller

The key board here we are interfacing is a matrix keyboard. This key board is designed with a
particular rows and columns. These rows and columns are connected to the microcontroller through its
ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051
can be easily connected to the rows and columns of the key board.

Whenever a key is pressed, a row and a column gets shorted through that pressed key and all
the other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates
microcontroller that the key is pressed. By this high on the bit key in the corresponding column is
identified.

Once we are sure that one of key in the key board is pressed next our aim is to identify that key.
To do this we firstly check for particular row and then we check the corresponding column the key
board.

To check the row of the pressed key in the keyboard, one of the row is made high by making
one of bit in the output port of 8051 high . This is done until the row is found out. Once we get the
row next out job is to find out the column of the pressed key. The column is detected by contents in the
input ports with the help of a counter. The content of the input port is rotated with carry until the carry
bit is set.

The contents of the counter is then compared and displayed in the display. This display is
designed using a seven segment display and a BCD to seven segment decoder IC 7447.

The BCD equivalent number of counter is sent through output part of 8051 displays the number
of pressed key.

Fig 5.1 Interfacing Keyboard to 8051 Microcontroller

Fig 5.2 Circuit Diagram of Interfacing Keyboard to 8051

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5.9 Program for Keyboard Interfacing with 8051

Start of main program:

to check that whether any key is pressed

start: mov a,#00h

mov p1,a ;making all rows of port p1 zero mov a,#0fh

mov p1,a ;making all rows of port p1 high

press: mov a,p2

jz press ;check until any key is pressed

after making sure that any key is pressed

mov a,#01h ;make one row high at a time mov r4,a

mov r3,#00h ;initiating counter

next: mov a,r4

mov p1,a ;making one row high at a time

mov a,p2 ;taking input from port A

jnz colscan ;after getting the row jump to check column

mov a,r4

rl a ;rotate left to check next row

mov r4,a

mov a,r3

add a,#08h ;increment counter by 08 count

mov r3,a

sjmp next ;jump to check next row

after identifying the row to check the colomn following steps are followed

colscan:mov r5,#00h

in: rrc a ;rotate right with carry until get the carry

jc out ;jump on getting carry

inc r3 ;increment one count

jmp in

out: mov a,r3

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da a ;decimal adjust the contents of counter before display

mov p2,a

jmp start ;repeat for check next key

5.10 Seven Segment Disply Interfacing with 8051

Fig 5.3 Interfacing LEDS to 8051 Microcontroller

Fig 5.4 Seven Segment Display

Fig 5.5 Connecting Seven segment Display with 8051

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5.11 LCD Interfacing

This section describes the operation modes of LCDs, then describes how to program and interface an
LCD to an 8051 using Assembly and C.

LCD operation:

In recent years the LCD is finding widespread use replacing LEDs (seven-segment LEDs or other
multisegment LEDs). This is due to the following reasons:

 The declining prices of LCDs.

 The ability to display numbers, characters, and graphics. This is in contrast to
LEDs, which are limited to numbers and a few characters.
 Incorporation of a refreshing controller into the LCD, thereby relieving the
CPU of the task of refreshing the LCD. In contrast, the LED must be refreshed
by the CPU (or in some other way) to keep displaying the data.
 Ease of programming for characters and graphics.

LCD pin descriptions

The LCD discussed in this section has 14 pins. The function of each pin is given in Table 5-1.
Figure 5.6 shows the pin positions for various LCDs.

Table 5.1 Function of Pins

VCC> VSS> and VEE

While Vcc and Vss provide +5V and ground, respectively, VEE is used for controlling LCD contrast.

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RS, register select

There are two very important registers inside the LCD. The RS pin is used for their selection as
follows. If RS = 0, the instruction command code register is selected, allowing the user to send a
command such as clear display, cursor at home, etc. If RS = 1 the data register is selected, allowing the
user to send data to be displayed on the LCD.

R/W, read/write

R/W input allows the user to write information to the LCD or read information from it. R/W =
1 when reading; R/W = 0 when writing.

E, enable

The enable pin is used by the LCD to latch information presented to its data pins. When data is
supplied to data pins, a high-to-low pulse must be applied to this pin in order for the LCD to latch in the
data present at the data pins. This pulse must be a minimum of 450 ns wide.

DO-D7

The 8-bit data pins, DO - D7, are used to send information to the LCD or read the contents of
the LCD's internal registers. To display letters and numbers, we send ASCII codes for the letters A - Z,
a - z, and numbers 0 - 9 to these pins while making RS = 1.

Figure 5.6 Pin Positions.

There are also instruction command codes that can be sent to the LCD to clear the display or
force the cursor to the home position or blink the cursor. Table 12-2 lists the instruction command codes.
We also use RS = 0 to check the busy flag bit to see if the LCD is ready to receive information. The

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busy flag is D7 and can be read when R/W = 1 and RS = 0, as follows: if R/W= 1, RS = 0. When D7 =
1 (busy flag = 1), the LCD is busy taking care of internal operations and will not accept any new
information. When D7 = 0, the LCD is ready to receive new information. Note: It is recommended to
check the busy flag before writing any data to the LCD.

Figure 5.7 Pin Positions for Various LCDs from Optrex

Sending commands and data to LCDs with a time delay

Program 5.1: Communicating with LCD using a delay

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To send any of the commands from Figure 5.6 to the LCD, make pin RS = 0. For data, make RS
= 1. Then send a high-to-low pulse to the E pin to enable the internal latch of the LCD. This is shown
in Program 5-1. See Figure 5.7 for LCD connections.

Program 5.2 Sending code or data to the LCD with checking busy flag

The above code showed how to send commands to the LCD without checking the busy flag.
Notice that we must put a long delay between issuing data or commands to the LCD. However, a much
better way is to monitor the busy flag before issuing a command or data to the LCD. This is shown in
Program 5.3.

Program 5.3: Communicating with LCD using the busy flag

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Figure 5.8. LCD Timing for Read ( L-to-H for E line)

Notice in the above program that the busy flag is D7 of the command register. To read the
command register we make R/W = 1 and RS = 0, and a L-to-H pulse for the E pin will provide us the
command register. After reading the command register, if bit D7 (the busy flag) is high, the LCD is busy
and no information (command or data) should be issued to it. Only when D7 = 0 can we send data or
commands to the LCD. Notice in this method that no time delays are used since we are checking the
busy flag before issuing commands or data to the LCD.

Contrast the Read and Write timing for the LCD in Figures 5.8 and 5.9. Note that the E line is
negative-edge triggered for the write while it is positive-edge triggered for the read.

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Figure 5.9. LCD Timing for Write (H-to-L for E line)

LCD data sheet

In the LCD, one can put data at any location. The following shows address locations and how
they are accessed.

where AAAAAAA = 0000000 to 0100111 for line 1 and AAAAAAA - 1000000 to 1100111 for
line 2. See Table 12-3.

Table 5.3 LCD Addressing

The upper address range can go as high as 0100111 for the 40-charac-ter-wide LCD, while for
the 20-character-wide LCD it goes up to 010011 (19 decimal = 10011 binary). Notice that the upper
range 0100111 (binary) = 39 decimal, which corresponds to locations 0 to 39 for the LCDs of 40x2 size.

From the above discussion we can get the addresses of cursor positions for various sizes of
LCDs. See Figure 12-5 for the cursor addresses for common types of LCDs. Note that all the addresses
are in hex. Table 12-4 provides a detailed list of LCD commands and instructions. Table 12-2 is
extracted from this table.

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Figure 5.10 Cursor Addresses for Some LCDs

5.12 Stepper Motor Interfacing

This section begins with an overview of the basic operation of stepper motors. Then we describe
how to interface a stepper motor to the 8051. Finally, we use Assembly language programs to
demonstrate control of the angle and direction of stepper motor rotation.

Stepper motors:

A stepper motor is a widely used device that translates electrical pulses into mechanical
movement. In applications such as disk drives, dot matrix printers, and robotics, the stepper motor is
used for position control. Stepper motors commonly have a permanent magnet rotor (also called the
shaft) surrounded by a stator. There are also steppers called variable reluctance stepper motors that do
not have a PM rotor. The most common stepper motors have four stator windings that are paired with a
center-tapped common as shown in Figure 5.11. This type of stepper motor is commonly referred to as
a. four-phase or unipolar stepper motor. The center tap allows a change of current direction in each of
two coils when a winding is grounded, thereby resulting in a polarity change of the stator. Notice that
while a conventional motor shaft runs freely, the stepper motor shaft moves in a fixed repeat-able
increment, which allows one to move it to a precise position. This repeatable fixed movement is possible
as a result of basic magnetic theory where poles of the same polarity repel and opposite poles attract.
The direction of the rotation is dictated by the stator Poles. The stator poles are determined by the
current sent through the wire coils. As the direction of the current is changed, the polarity is also changed
causing the reverse motion of the rotor. The stepper motor discussed here has a total of 6 leads: 4 leads
representing the four stator windings and 2 commons for the center-tapped leads. As the sequence of
power is applied to each stator winding, the rotor will rotate.

Table 5.4 Normal 4-Step Sequence

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There are several widely used sequences where each has a different degree of precision. Table
5.4 shows a 2-phase, 4-step stepping sequence.

It must be noted that although we can start with any of the sequences in Table 5.5, once we start
we must continue in the proper order. For example, if we start with step 3 (0110), we must continue in
the sequence of steps 4, 1,2, etc.

Step angle

Table 5.5 Stepper Motor Step Angle

How much movement is associated with a single step? This depends on the internal construction
of the motor, in particular the number of teeth on the stator and the rotor. The step angle is the minimum
degree of rotation associated with a single step. Various motors have different step angles. Table 5.5
shows some step angles for various motors. In Table 5.5, notice the term steps per revolution. This is
the total number of steps needed to rotate one complete rotation or 360 degrees (e.g., 180 steps x 2
degrees = 360). It must be noted that perhaps contrary to one's initial impression, a stepper motor does
not need more terminal leads for the stator to achieve smaller steps. All the stepper motors discussed in
this section have 4 leads for the stator winding and 2 COM wires for the center tap. Although some
manufacturers set aside only one lead for the common signal instead of two, they always have 4 leads
for the stators. Next we discuss some associated terminology in order to understand the stepper motor
further.

Example 5.1

Describe the 8051 connection to the stepper motor of Figure 5.11 and code a program to rotate it
continuously.

Solution:

The following steps show the 8051 connection to the stepper motor and its programming.

 Use an ohmmeter to measure the resistance of the leads. This should identify which COM leads
are connected to which winding leads.
 The common wire(s) are connected to the positive side of the motor's power supply.
In many motors, +5 V is sufficient.
 The four leads of the stator winding are controlled by four bits of the 8051 port (Pl.O
- P1.3). However, since the 8051 lacks sufficient current to drive the stepper motor
windings, we must use a driver such as the ULN2003 to energize the stator. Instead
of the ULN2003, we could have used transistors as drivers, as shown in Figure 17-9.
However, notice that if transistors are used as drivers, we must also use diodes to
take care of inductive current generated when the coil is turned off. One reason that
using the ULN2003 is preferable to the use of transistors as drivers is that the
ULN2003 has an internal diode to take care of back EMF.

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Change the value of DELAY to set the speed of rotation. We can use the single-bit instructions
SETB and CLR instead of RR A to create the sequences.

Figure 5.11. 8051 Connection to Stepper Motor

Steps per second and rpm relation:

The relation between rpm (revolutions per minute), steps per revolution, and steps per second is
as follows.

The four-step sequence and number of teeth on rotor

The switching sequence shown earlier in Table 5.4 is called the 4-step switching sequence since
after four steps the same two windings will be "ON" How much movement is associated with these four

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steps? After completing every four steps, the rotor moves only one tooth pitch. Therefore, in a stepper
motor with 200 steps per revolution, the rotor has 50 teeth since 4x50 = 200 steps are needed to complete
one revolution. This leads to the conclusion that the minimum step angle is always a function of the
number of teeth on the rotor. In other words, the smaller the step angle, the more teeth the rotor passes.

5.13 Servo Motor

Servos are DC motors with built in gearing and feedback control loop circuitry. And no motor
drivers required. They are extremely popular with robot, RC plane, and RC boat builders. Most servo
motors can rotate about 90 to 180 degrees. Some rotate through a full 360 degrees or more. However,
servos are unable to continually rotate, meaning they can't be used for driving wheels, unless they are
modified (how to modify), but their precision positioning makes them ideal for robot legs and arms,
rack and pinion steering, and sensor scanners to name a few.

Since servos are fully self-contained, the velocity and angle control loops are very easy to
implement, while prices remain very affordable. To use a servo, simply connect the black wire to
ground, the red to a 4.8-6V source, and the yellow/white wire to a signal generator (such as from your
microcontroller). Vary the square wave pulse width from 1-2 ms and your servo is now position/velocity
controlled. Pulse width modulation (PWM) is a powerful technique for controlling analog circuits with
a processor's digital outputs. PWM is employed in a wide variety of applications, ranging from
measurement and communications to power control and conversion. The general concept is to simply
send an ordinary logic square wave to your servo at a specific wave length, and your servo goes to a
particular angle (or velocity if your servo is modified). The wavelength directly maps to servo angle.

Fig 5.9 Pulse for controlling Servo motor

5.13.1 Controlling the Servo Motor

PWM

Pulse width modulation (PWM) is a powerful technique for controlling analog circuits with a
processor's digital outputs. PWM is employed in a wide variety of applications, ranging from
measurement and communications to power control and conversion. The general concept is to
simply send an ordinary logic square wave to your servo at a specific wave length, and your servo
goes to a particular angle (or velocity if your servo is modified). The wavelength directly maps
to servo angle.

Programmable Counter Array (PCA)

The PCA is a special modules in Philips P89V51RD2 which includes a special 16-bit Timer that

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to
operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or
pulse width modulator. Each module has a pin associated with it in port 1.

Module 0 is connected to P1.3 (CEX0), module 1 to P1.4 (CEX1), etc. Registers CH and CL
contain current value of the free running up counting 16-bit PCA timer. The PCA timer is a common
time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source
is determined from the CPS1 and CPS0 bits in the CMOD SFR.

In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which
allows the PCA to stop during idle mode, WDTE which enables or disables the Watchdog function on
module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON
SFR) to be set when the PCA timer overflows. The Watchdog timer function is implemented in module
4 of PCA. Here, we are interested only PWM mode.

8051 Pulse width modulator mode

All of the PCA modules can be used as PWM outputs. Output frequency depends on the source
for the PCA timer. All of the modules will have the same frequency of output because they all
share one and only PCA timer.

The duty cycle of each module is independently variable using the module's capture register
CCAPnL. When the value of the PCA CL SFR is less than the value in the module's CCAPnL SFR the
output will be low, when it is equal to or greater than the output will be high.

When CL overflows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. This
allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn
register must be set to enable the PWM mode. For more details see P89V51RD2 datasheet.

This is an example how to control servos with 8051 by using PWM. The schematic is shown below.
I use P1.4 (CEX1) to control the left servo and P1.2 (CEX2) to control the right servo. Here, I use
GWS servo motor model S03T STD. I need three states of duty cycle:

 20 ms to Stop the servo

 1 ms to Rotate Clockwise

Calculation for duty cycle (for XTAL 18.432 MHz with 6 Clock/Machine cycle)

 Initial PWM Period = 20mS (18.432MHz /6-Cycle Mode)

 Initial PCA Count From Timer0 Overflow
 1 Cycle of Timer0 = (1/18.432MHz)x6 = 0.326 uS
 Timer0 AutoReload = 240 Cycle = 78.125 uS
 1 Cycle PCA = [(1/18.432MHz)x6]x240 = 78.125 uS
 Period 20mS of PCA = 20ms/78.125us = 256 (CL Reload)
 CL (20mS) = 256 Cycle Auto Reload
 Load CCAPxH (1.0mS) = 256-13 = 243 (243,244,...,255 = 13 Cycle)
 Load CCAPxH (2.0mS) = 255-26 = 230 (230,231,...,255 = 26 Cycle)

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

Fig 5.10 Schematic Control

5.13.2 Program
Filename : pwm_servos.h
Hardware : Controller -> P89V51RD2
XTAL -> 18.432 MHz
Mode -> 6 Clock/MC
I/O : P1.4 -> Left (PWM-CEX1)
P1.5 -> Right (PWM-CEX2)
Compiler : SDCC
/* Control the Left servo */
void ServoL_back()
{
CCAP1H = 243;
}
void ServoL_forward()
{
CCAP1H = 230;
}
void ServoL_stop()
{
CCAP1H = 0;
}
/* Control the Right servo */
void ServoR_back()
{
CCAP2H = 230;
}
void ServoR_forward()
{

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

CCAP2H = 243;
}
void ServoR_stop()
{
CCAP2H = 0;
}

/* Initialize the PCA and PWM mode */

void Servos_init()
{
/* Initial Timer0 Generate Overflow PCA */

TMOD = 0x02; /* Timer0 Mode2 : 8bit auto reload */

TH0 = 16; /* 256-240, 8.125usec Auto-relead (20msec/PWM) */ TL0 = TH0;
TCON = 0x10; /* setb TR0, TCON or 0001,0000*/
/*Initial PWM Period = 20mS (18.432MHz /6-Cycle Mode) Initial PCA Count From Timer0 Overflow
1 Cycle of Timer0 = (1/18.432MHz)x6 = 0.326uS Timer0 AutoReload = 240 Cycle = 78.125uS 1 Cycle
PCA = [(1/18.432MHz)x6]x240 = 78.125uS Period 20mS of PCA = 20ms/78.125us = 256(CL Reload)
CL(20mS) = 256 Cycle Auto Reload Load CCAPxH(1.0mS) = 256-13 = 243 (243,244,...,255 = 13
Cycle) Load CCAPxH(2.0mS) = 255-26 = 230 (230,231,...,255 = 26 Cycle)*/
CMOD=0x04; CCAPM1=0x42; CCAPM2=0x42; CCAP1H=0x00; CCAP2H=0x00; CCON=0x40;
}
test.c
#include <p89v51rd2.h>
#include "pwm_servos.h"
void PowerOn()
{
unsigned char inner, outer;
IE = 0x00;
P1 = 0xFF; /* Motor STOP */
for (outer = 0x00; outer < 0x10; outer++) { /* Delay for a while */
for (inner = 0x00; inner < 0xFF; inner++);
}
Servos_init();
IE = 0x80; /* Start interrupt */
}
void main()
{
PowerOn();
ServoR_forward(); ServoL_back();
while (1);
}

5.14 Washing Machine Control

Many washing m/c shell in the market has mechanical controlled sequence for activated the
timer and the sequence back and forth for their motor; washing motor or spinning motor. Spinning
motor control only has one direction only, and its simple could be changed to the discrete mechanical
timer which sell on the market. But washing motor control has 2 direction for this purpose, it means
to squeeze the clothes, it must go to forward and then reversed. The sequence is like this:

 First, go to forward direction for about a few seconds

 Than stop, while the chamber is still rotate

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 Second, go back to reverse direction for about a few seconds

 Than stop, while the chamber is still rotate
 And so on, back and forth, until the the timer elapsed

5.14.1 Schematic

Timing sequence like the above description, can be implemented with many way, by using
discrete electronic components, timer, using a program or a microcontroller or microprocessor, etc.
Because I am learning the PIC microcontroller for right now, I will implement this function using this
microcontroller, but for you who familiar with another kind of microcontroller my adapted it to your
purpose. By using PIC micro, it can be made more compact. First I plan to make 2 buttons, 1 for set
the timer and another for reset the timer or for the emergency stop push button. Then to know the timer
works or not, I need a visual display.

For this purpose I will use 7-segmen display showing the rest of the timer. To run the motor
sequence of course I need a pair of relays (power relays, about 3 Amperes output), one for forward
and another for reverse option. I will use the very common family of PIC micro, ie : 16F84A, because
this is the most popular type and very simples used and very much used. Also can be obtained easily
in the market. But this is the medium type of PIC micro family. It has 1kByte of memory (EEPROM
type) and 13 I/O pins. It can be reprogrammable thousands times. Because the I/O just only 13 pins, I
used a BCD to 7-segmen chip. So it will left a few I/O pins for expanded in the future. You can
omitted this chip for timing sequence purpose and save one IC price, because the I/O just exactly
enough.

 I/O port A-0 = SET push button

 I/O port A-1 = RST push button
 I/O port A-2 = Reserved
 I/O port A-3 = Reserved
 I/O port A-4 = Reserved
 I/O port B-0 = Forward Relay (Run motor forward)
 I/O port B-1 = Reverse Relay (Run motor reverse)
 I/O port B-2 = Activated unit 7-segmen (multiplexed)
 I/O port B-3 = Activated ten 7-segmen (multiplexed)
 I/O port B-4 = BCD data A (for 7-segmen)
 I/O port B-5 = BCD data B (for 7-segmen)
 I/O port B-6 = BCD data C (for 7-segmen)
 I/O port B-7 = BCD data D (for 7-segmen)
 Also integrated power supply to run it modularly

The I/O can be configured as input pin or output pin bit-ly. It is up to you to choose the I/O pin
number goes to what function, but it infect the program firmware of course. Once you choose,
then it is just like that, except you also change both, the program and the hardware.

5.14.2 Working of Washing Machine

The direction of rotation can be controlled when switchS1 is in position A, coil L1 of the motor
receives the current directly, whereas coil L2 receives the current with a phase shift due to
capacitor C. So the rotor rotates in clockwise direction (see Fig. 2(a)). When switch S1 is in
position B, the reverse happens and the rotor rotates in anti-clock wise direction Thus switch S1 can
change the rotation direction. The motor cannot be reversed instantly. It needs a brief pause between
switching directions, or else it may get damaged. For this purpose, another spin direction control
timer (IC2) is employed. It is realised with an IC 555. This timer gives an alternate „on‟ and „off‟
time duration of 10 seconds and 3 seconds, respectively. So after every l0 seconds of running (either
in clockwise or anti clockwise direction), the motor stops for a brief duration of 3 seconds. The values

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

of R3 and R4 are calculated accordingly. The master timer is realised with monostable IC555 (IC1) and
its „on‟ time is decided by the resistance of 1-mega- ohm potmeter VR. A 47-kilo-ohm resistor is added
in series so that even when the VR knob is in zero resistance position, the net series resistance is not
zero

Fig 5.11 Circuit Diagram of Washing Machine

Fig 5.12 Rotation of Motor

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

QUESTION BANK

SCE 91 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT-1

8085 & 8086 PROCESSOR

Two Marks Questions with Answers

1. What is microprocessor? Give the power supply &clock frequency of 8085

A microprocessor is a multipurpose, programmable logic device that reads binary instructions

from a storage device called memory accepts binary data. As input and processes data according
to those instructions and provides result as output. The power of 8085 is +5v and clock frequency in
3MHZ.

2. List few applications of microprocessor-based system.

It is used:

 For measurements, display and control of current, voltage, Temperature, pressure, etc.
 For traffic control and industrial tool control.
 For speed control of machines.

3. What are the functions of an accumulator?

The accumulator is the register associated with the ALU operations and sometimes I/O
operations. It is an integral part of ALU. It holds one of d a t a t o be processed by ALU. It also
temporarily stores the result of the operation performed by the ALU.

4. List the 16 – bit registers of 8085 microprocessor.

Stack pointer (sp) and program counter (pc).

5.List the allowed register pairs of 8085.

 B-C register pair

 D-C register pair
 H-L register pair.

6.Mention the purpose of SID and SOD lines

 SID(serial input data line):

It is an input line through which the microprocessor accepts serial data.

 SOD(serial output data line):

It is an output line through which the microprocessor sends output serial data.

7.What is an opcode?

The part of the instruction that specifies the operation to be performed is called the
operation code or opcode.

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8. What is the function of IO/M signal in the 8085?

It is a statussignal. It is used to differentiate between memory locations and I/O operations

w h e n this signal is low (IO/M=0) it denotes the memory related operations. When this signal is high
(IO/M=1) it denotes an I/O operation

9. What is an operand?

The data on which the operation is to be performed is called as an operand.

10. How many address lines in a 4096*8 EPROM CHIP?

12 Address lines.

11. Control signals used for DMA operation are

 HOLD
 HLDA

12. What is meant by wait state?

This state is used by slow peripheral devices. The peripheral devices can transfer the data to
or from the microprocessor by using READY input line. The microprocessor remains in the wait
state as long as READY line is low. During the wait state, the contents of the address, address/data and
control buses are held constant.

13. What is meant by polling?

Polling or device polling is a process which identifies the device that has interrupted the
microprocessor.

14. What is meant by interrupt?

Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.

15. Explain priority interrupts of 8085?

The 8085 microprocessor has five interrupt inputs. They are TRAP, RST7.5, RST 6.5, RST
5.5, and INTR. these interrupts have a fixed priority of interrupt service. If two or more interrupts
go high at the same time, the 8085 will service them on priority basis. The TRAP has the highest priority
followed by RST7.5, RST6.5, and RST5.5. The p r i o r i t y of interrupts in 8085 is shown in the
table.
Interrupts priority
TRAP 1
RST7.5 2
RST6.5 3
RST5.5 4
INTR 5

16. What is a microcomputer?

A computer that is designed using a microprocessor as its CPU is called microcomputer.

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17. What is the signal classification of 8085?

All the signals of 8085 can be classified into 6 groups

 Address bus
 Data bus
 Control and status signals
 Power supply and frequency signals
 Externally intiated signals
 Serial I/O ports

18. What are operations performed on data in 8085?

The various operations performed are

 Store 8-bit data

 Perform arithmetic and logical operations
 Test for conditions
 Sequence the execution of instructions
 Store data temporarily during execution in the defined R/W
 Memory locations called the stack

19. Steps involved to fetch a byte in 8085?

 The pc places the 16-bit memory address on the address bus

 The control unit sends the control signal RD to enable the memory chip
 The byte from the memory location is placed on the data bus
 The byte is placed in the instruction decoder of the microprocessor and the task is carried
out according to the instruction.

20. How many interrupts does 8085 have mention them

The 8085 has 5 interrupt signals they have INTR, RST7.5, RST6.5, RST5.5 and TRAP

21. Basic concepts in the memory interfacing?

The primary function of memory interfacing is that the microprocessor should be able to read
from and write into a given register of a memory chip.to perform these operations the
microprocessor should,

 Be able to select the chip

 Identify the register
 Enable the appropriate buffer

22. Define instruction cycle, machine cycle and T-state?

Instruction cycle is defined as the time required completing the execution of an

instruction. Machine cycle is defined as the time required completing one operation of accessing
memory, I/O or acknowledging an external request. T cycle is defined as one subdivision of the
operation performed in one clock period.

23. What is the use of ALE?

The ALE is used to latch the lower order address so that it can be available in T2 and T3 and
used for identifying the memory address. During T1 the ALE goes high, the latch is transparent ie,

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

the output changes according to the input data, so the output of the latch is the lower order address.
When ALE goes low, the lower order address is latched until the next ALE.

24. How many machine cycles does 8085 have? Mention them.

The 8085 have seven machine cycles they are

 Opcode fetch
 Memory read
 Memory write
 I/O read
 I/Owrite
 Interrupt acknowledge
 Bus idle

25. Explain the signals HOLD, READY and SID.

 HOLD indicates that a peripheral such a DMA controller is requesting the use of address bus,
data bus and control bus.
 READY is used to delay the microprocessor read or write cycles until a slow responding
peripheral is ready to accept or send data.
 SID is used to accept serial data bit by bit.

26. What is the use of bidirectional buffer?

It is used to increase the driving capacity of data bus. The data bus of the microcomputer system
is bidirectional, so it requires a buffer that allow the data to flow in both directions.

27. Give the register organization of 8085?

 W(8)Register
 Z(8) Register
 B(8)Register
 E(8)Register
 H(8) Register
 L(8) Register
 Stack pointer(16)
 Program counter(16)

28. What is the microcontroller and microcomputer?

 Microcontroller is a device that includes microprocessor, memory and I/O signal lines on a
single chip, fabricated using VLSI technology.
 Microcomputer is a computer that is designed using microprocessor as its CPU.it
includes microprocessor, memory and I/O.

29. Define flags?

The flags are used to reflect the data conditions in the accumulator. The 8085 flags are

 S-sign flag
 Zero flag
 Auxiliary flag
 Parity flag
 Carry Flag

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30. Difference between memory mapped I/O and peripheral I/O?

MEMORY MAPPEED I/O PERIPHERAL I/O
16-bit device address 8-bit device address
The data transfer between any general- The data transfer only between accumulator and
purpose register and I/O port I/O port
The memory map(64kb)is shared between The I/O map is independent of the memory
I/O device and system memory map,256 input device and 256 output device
More hardware is required to decode 16-bit Less hardware is required to decode 8-bit address
address

31. What is interfacing?

An interface is a shared boundary between the devices which involves sharing information.
Interfacing is the process of making two different systems communicate with each other.

32. What is memory mapping?

The assignment of memory address to various registers in a memory chip is called as

memory mapping.

32. What is I/O mapping?

The assignment of address to various I/O devices in the memory chip is called as I/O
Mapping

………………………………………………………………….

8 Marks Questions
1. Describe the functional pin diagram of 8085.
2. Describe the functional block diagram of 8085.
3. Explain the 8085 interrupt system in detail.
4. Explain various machine cycles supported by 8085
5. What is the difference between minimum and maximum modes of 8086? How are T modes selected?
6. Describe the sequence of event that may occur during the different T state in the opcode fetch
machine cycle of 8086
7. List out the maskable and non maskable interrupts available in 8086
8. Write short notes on addressing memory
9. Give the functions of NMI, BHE and TEST pins of 8086
10. Write notes on addressing input and output devices.
11. Describe the sequence of event that may occur during the different T state in the opcode fetch
machine cycle of 8086
12. Explain the concept of pipelining in 8086. Discuss its advantages and disadvantages

………………………………………………………………….

SCE 96 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

16 Marks Questions

1. Draw and explain the architecture of 8086

2. Design a microprocessor system to interface an 8K × 8 EPROM and 8K × 8 RAM.
3. How many interrupts are available in 8086? List the predefined software interrupts available in 8086
4. Explain the minimum mode of operation of 8086.
5. Explain the Maximum mode of operation of 8086
6. Draw and explain the architecture of 8085
………………………………………………………………….

SCE 97 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT-2

PROGRAMMING OF 8085 PROCESSOR

Two Marks Questions with Answers

1. What is an instruction?

An instruction is a binary pattern entered through an input device to command the

microprocessor to perform that specific function.

2. How many operations are there in the instruction set of 8085 microprocessor?

There are 74 operations in the 8085 microprocessor

3. List out the five categories of the 8085 instructions. Give e.g. of the instructions for each
group?

 Data transfer group – MOV,MVI,LXI

 Arithmetic group – ADD,SUB,INR.
 Logical group- ANA,XRA,CMP.
 Branch group – JMP,JNZ,CALL.
 Stack I/O and machine control group – PUSH,POP,IN,HLT.

4. Explain the difference between a JMP instruction and CALL instruction.

A JMP instruction permanently changes the program counter. A CALL instruction leaves
information on the stack so that the original program execution sequence can be resumed.

5. Explain the purpose of the I/O instructions IN and OUT

 The IN instruction is used to move data from an I/O port in to the accumulator.
 The OUT instruction is used to move data from the accumulator to an I/O port.
 The IN and OUT instructions are used only on microprocessor, which u s e a separate
address space for interfacing.

6. What is the difference between the shift and rotate instructions?

A rotate instruction is a closed loop instruction .that is the data moved out at one end is put
back in at the other end. The shift instruction loses the data that is moved out of the last bit
locations.

7. List the four instructions which control the interrupt structure of the 8085
microprocessor?

 DI(disable interrupts)
 EI(enable interrupts)
 RIM(read interrupt masks)
 SIM(set interrupt masks)

8. Mention the categories of instruction and give two ex for each category?

The instructions of 8085 can be categorized in to the following five

SCE 98 Dept. of ECE

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1. Data transfer MOV RD,RS,STA 16-BIT

2. Arithmetic ADD R,DCR M.
3. Logical XRI 8- bit,RAR
4. Branching JNZ CALL 16-bit
5. Machine control HLT,NOP

9. Explain LDA, STA AND DAA instructions

LDA copies the data byte in to the accumulator from the memory location specified by the
16-bit address. STA copies the data byte from the accumulator in the memory location specified
by 16-bit address. DAA changes the content of the accumulator from binary to 4-bit BCD digits

10. Explain the different instruction formats with ex?

The instruction set is grouped in to the following formats One byte instruction MOV C,A
Two byte instruction MVI A,39H Three byte instruction JMP 2345H

11. What is the use of addressing modes, mention the different types?

The v a r i o u s formats of specifying the operands are called as addressing modes, it is used to access
the operands or data. The different types are as follows

1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
5. Implicit addressing

12. Define stack and stack related instructions?

The stack is a group of memory locations in the R/W memory that is used for the
temporary storage of binary information during the execution of the program. The stack related
instructions are PUSH and POP

13. Why do we use XRA A instruction?

The XRA A instruction is used to clear the contents of the accumulator and store the
value 00H

14. Compare CALL and PUSH instructions

CALL PUSH

When CALL is executed the microprocessor

The program uses the instruction PUSH to save
automatically stores the 16-bit address of the
the contents of the register pair on the stack
instruction next to CALL on the stack

When CALL is executed the stack pointer is When PUSH is executed the stack pointer
decremented by two register is decremented by two

15. How does the microprocessor differentiate b/w data and instruction?

When the first m/c code of an instruction is fetched and decoded in the instruction register, the

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microprocessor recognizes the n u m b e r o f b y t e s r e q u i r e d to f e t c h t h e e n t i r e

instruction. For ex MVI A,data, the second byte is always considered as data. If the data byte is omitted
by mistake whatever is in that memory location will be considered as data and the byte after the
“data “will be treated as the next instruction.

16. Compare RET and POP

RET POP

RET transfers the content of the top two locations Pop transfers the content of the top two locations
of the stack to the PC of the stack to the specified register pair

When RET is executed the SP is incremented by When POP is executed the SP is incremented by
two. And it has 8 conditional RETURN two and no conditional POP instructions
instructions

17. What are subroutine?

Procedures are group of instructions stored as a separate program in memory and it is

called from the main program in memory and it is called from the main program whenever
required. The type of procedure depends on where the procedures are stored in memory. If it is in
the same code segment as that of the main program then it is a near procedure otherwise it is a far
procedure.

18. What is a recursive procedures?

A recursive procedure is a procedure, which calls itself. Recursive procedures are used to
work with complex data structures called trees. If the procedure is called with N=3, then the N i s
decremented by 1 after each procedure CALL and the procedure is called until N=0.

19. How to access subroutine with in the main program procedure?

 accessed by CALL & RET instruction

 machine code of instruction is put only once in the memory iii)with procedures less memory
is required
 parameters can be passed in registers, memory location or stack

20. Define stack?

Stack is a sequence of RAM memory locations defined by the programmer.

21. How the microprocessor is synchronized with peripherals?

The timing and control unit synchronizes all the microprocessor operations with clock and
generates control signals necessary for communication between the microprocessor and
peripherals.

22. What is the minimum s/m and how it is formed in 8085?

A minimum s/m is one which is formed using minimum number of IC chips. The 8085
based minimum s/m is formed using 8155, 8355 & 8755.

………………………………………………………………….

SCE 100 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

8 Marks Questions

1. Write a program to arrange /n numbers in ascending order.

2. Write a program to unpack a two digit BCD number stored at memory location 1C00H

3. Write a program to calculate the factorial of a number between 0 to 8

4. Write a program to find the number of negative, zero and positive numbers

5. Write a program to ADD two 8 Bit numbers.

6. Explain the stack operations with an example

7. Describe an Input/Output instructions with an example.

8. Explain the BCD to Decimal code conversion technique and write 8085 assembly language

program for the same

9. Explain the BCD to Seven Segment code conversion technique and write 8085 assembly

language program for the same.

10. Discuss in detail about jump instructions

11. Discuss the operation of Looping, Counting and indexing with Look up table

………………………………………………………………….
16 Marks Questions

1. Explain the addressing modes of 8085 with example

2. Explain the Different types of instruction in 8085

3. Explain the Arithmetic and logical instruction in 8085 with example

4. With an example , Explain the operation of Data transfer instructions

5. Discuss in detail about the operation of Subroutines instructions

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SCE 101 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT- 3

PERIPHERAL INTERFACING

Two Marks Questions with Answers

1. What is the use of 8051 chip?

Intel’s 8251A is a universal synchronous asynchronous receiver and transmitter

compatible with Intel’s Processors. This may be programmed to operate in any of the serial
communication modes built into it. This chip converts the parallel data into a serial stream of bits
suitable for serial transmission. It is also able to receive a serial stream of bits and converts it into
parallel data bytes to be read by a microprocessor.

2. What are the different types of methods used for data transmission?

The data transmission between points involves unidirectional or bi-directional

transmission of meaningful digital data through a medium. There are basically there modes of data
transmission

 Simplex
 Duplex
 Half Duplex

In simplex mode, data is transmitted only in one direction over a single communication channel.
For example, a computer (CPU) may transmit data for a CRT display unit in this mode.

In duplex mode, data may be transferred between two trans receivers in both directions
simultaneously.

In half duplex mode, on the other hand, data transmission may take place in either direction,
but at a time may be transmitted only in one direction. For example, a computer may communication
with a terminal in this mode. When the terminal sends data (i.e. terminal is sender).The message is
received by the computer (i.e. computer is receiver). However, it is not possible to transmit data
from the computer to terminal and from terminal to the computer simultaneously.

3. What is the various programmed data transfer method?

 Synchronous data transfer

 Asynchronous data transfer
 Interrupt driven data transfer

4. What is synchronous data transfer?

It is a data method which is used when the I/O device and the microprocessor match in
speed. The transfer a data to or from the device, the user program issues a suitable instruction
addressing the device. The data transfer is completed at the end of the execution of this
instruction.

5. What is asynchronous data transfer?

It is a data transfer method which is used when the speed of I/O device does not match with
the speed of the microprocessor. Asynchronous data transfer is also called as Handshaking.

SCE 102 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

6. What are the functional types used in control words of 8251a?

The control words of 8251A are divided into two functional types

Mode Instruction control word: - This defines the general operational characteristics of 8251A.
Command Instruction control word: - The command instruction controls the actual operations of
the selected format like enable transmit/receiver, error reset and modem control.

7. What are the basic modes of operation of 8255?

There are two basic modes of operation of 8255, viz.

 I/O mode.
 BSR mode

In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C
(PC0-PC7) can be used to set or reset its individual port bits. Under the IO mode of operation, further
there are three modes of operation of 8255, So as to support different types of applications,
viz. mode 0, mode 1, and mode 2.

Mode 0- Basic I/O mode

Mode 1-Strobe I/O mode

Mode 2- Strobe bi-direction I/O

8. Write the features of mode 0 in 8255?

 Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are available.
Thetwo 4-bit ports can be combined used as a third8-bitport.
 Any port can be used as an input or output port.
 Output ports are latched. Input ports are not latched.
 A maximum of four ports are available so that overall 16 I/O configurations are possible.

9. What are the features used mode 1 in 8255?

 Two groups A and group B are available for strobe data transfer.
 Each group contains one 8-bit data I/O port and one 4-bit control/data port.
 The 8-bit data port can be either used as input or output port. The inputs and outputs both are
latched.
 Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and PC3=PC5 are
used to generate control signals for port A. The inputs PC6, PC7 may be used as independent
data lines.

10. What are the signals used in input control signal and output control signals?

 Input control signals

STB (Strobe input) IBF (Input buffer full) INTR (Interrupt request)
 Output control signal
OBF (Output buffer full) ACK (Acknowledge input)
INTR (Interrupt request)

11. What are the features used mode 2 in8255?

The signals 8-bit port in group A is available.

SCE 103 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

 The 8-bit port is bi-directional and additionally a 5-bit control port is available.
 Three I/O lines are available at port C, viz PC2-PC0.
 Inputs and output are both latched.
 The 5-bit control port C (PC3-PC7) is used for generating/accepting handshake Signals for the
8-bit data transfer on port A.

12. What are the modes of operation used in 8253?

Each of the three counters of 8253 can be operated in one of the following six modes of operation.

 Mode 0 (Interrupt on terminal count)

 Mode 1 (Programmable monoshot)
 Mode 2 (Rate generator)
 Mode 3 (Square wave generator)
 Mode 4 (Software triggered strobe)
 Mode 5 (Hardware triggered strobe)

13. What are the different types of write operations used in 8253?

There are two types write operation in 8253

 Writing a control word register

 Writing a count value into a count register

The control word register accepts data from the data buffer and initialize

 Initializing the operating modes (mode 0- mode 4)

 Selection of counters (counter 0- counter 2)
 Choose binary /BCD counters.
 Loading of the counter registers.

The mode control register is a write only register and the CPU cannot read its contents.

14. Give the different types of command words used in 8259A

The command words of 8259A are classified in two groups

 Initialization command words (ICWs)

 Operation command words (OCWs)

15. Give the operation modes of 8259A?

 Fully Nest Mode

 End of Interrupt
 Automatic Rotation
 Automatic EOI mode
 Specific Rotation
 Special Mask Mode
 Edge and level Triggered Mode
 Reading 8259 Status
 Poll command
 Special Fully Nested Mode

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EE2354 MICROPROCESSOR AND MICROCONTROLLER

 Buffered Mode
 Cascade Mode

16. Define scan counter?

The scan counter has two modes to scan the key matrix and refresh the display. In the encoded
mode, the counter provides binary count that is to be externally decoded to provide the scan lines for
keyboard and display. In the decoded scan mode, the counter internally decodes the least significant 2
bit and provides a decoded 1 out of 4 scan on SL3-SL 3. The keyboard and display both are in the
same mode at a time.

17. What is the output modes used in 8279?

8279 provides two output modes for selecting the display options.

 Display scan
 In this mode, 8279 provides 8 or 16 character- multiplexed displays those can be organized as
dual 4-bit or single 8-bit display units.
 Display Entry 8279 allows options for data entry on the displays. The display data is entered
for display from the right side or from the left side.

18. What are the modes used in keyboard modes?

 Scanned Keyboard mode with 2 Key Lockout

 Scanned K e y b o a r d w i t h N -Key Rollover.
 Scanned Keyboard Special Error Mode.
 Scanned Matrix Mode.

19. What are the modes used in display modes?

1. Left Entry Mode

In the left entry mode, the data is entered from the left side of the display unit.

2. Right Entry Mode

In the right entry mode, the first entry to be displayed is entered on the rightmost display.

20. What is the use of modem control unit in 8251?

The modem control unit handles the modem handshake signals to coordinate the
communication between the modem and the USART.

21. List the operation modes of 8255?

a) I/O Mode

 Mode 0- Simple Input/Output.

 Mode 1- Strobe Input/Output (handshake mode)
 Mode 2- Strobe bi-directional mode b) Bit Set/Reset Mode.

22. What is a control word?

It is a word stored in a register (control register) used to control the operation of a program
digital device.

SCE 105 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

23. What is the purpose of control word written to control register in 8255?

The control words written to control register specify an I/O function for each I/O port. The
bit D7 of the control word determines either the I/O functions of the BSR function.

24. What is the size of ports in 8255?

Port - A : 8- bits Port - B : 8- bits

Port -CU : 4- bits Port -CL : 4- bits

25. What is an USART?

USART stands for universal Synchronous / Asynchronous Receiver / Transmitter. It is a

programmable communication interface that can communicate by using either synchronous or
asynchronous serial data.

26. What is the use of 8251 chip?

8251 chip is mainly used as the asynchronous serial interface between the processor and the
external equipment.

27. The 8279 is a programmable ----------------- interface.

Keyboard/ Display

28. List the major components of the Keyboard/ Display interface.

 Keyboard section
 Scan section
 Display section
 CPUinterface section

29. What is Key bouncing?

Mechanical switch are used as keys in most of the keyboard. When a key is pressed the contact
bounce back and forth and settle down only after a small time delay (about 20ms). Even though a key
is actuated once, it will appear to have been actuated several times. This problem is called Key
Bouncing

30. What is TXD?

TXD- Transmitter Data Output

This output pin carries serial of the transmitted data bits along with other information like start bit,
stop bits and priority bit.

31. Define HRQ?

The hold request output request the access of the system bus. In non- cascaded 8257
systems, this is connected with HOLD pin of CPU. In cascade mode, this pin of a slave is
connected with a DRQ input line of the master 8257, while that of the master is connected with HOLD
input of the CPU.

SCE 106 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

32. What is RXD?

RXD- Receive Data Input

This input pin of 8251A receives a composite stream of the data to be received by 8251A.

33. What are the internal devices of a typical DAC?

The internal devices of a DAC are R/2R resistive network, an internal latch and current to voltage
converting amplifier.

34. What is setting or conversion time in DAC?

The time taken by the DAC to convert a given digital data to corresponding analog signal is called
conversion time.

35. What are the different types of ADC?

The different types of ADC are successive approximation ADC, counter type ADC, flash type
ADC, integrator converters and voltage to frequency converters

………………………………………………………………….

8 Marks Questions

1. Using model, write a program to communicate between two microprocessors using 8255

2. Bring about the features of 8251

3. Explain the advantages of using the USART chips in microprocessor based systems

4. Show the control word format of 8255 and explain how each bit is programmed

5. Use RST 5.5 instead of RST 7.5 and change mask pattern accordingly

6. Describe with any one of the mode configurations of 8254 timer in detail

7. Use RST 5.5 instead of RST 7.5 and change mask pattern accordingly

8. Bring about the features of 8251

9. With neat block diagram explain the functions of 8259

10. Explain the advantages of using the keyboard and display controller chips in microprocessor

based system

………………………………………………………………….

SCE 107 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

16 Marks Questions

1. Explain any one of the modes of 8255 in detail

2. With neat block diagram explain PPI

3. Explain the working of 8254 timer

4. Explain how to convert an analog signal into digital signal

5. Explain the 7 segment LED interface with microprocessor

………………………………………………………………….

SCE 108 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT-IV

MICROCONTROLLERS 8051

Two Marks Questions with Answers

1. What is mean by microcontroller?

A device which contains the microprocessor with integrated peripherals like memory,
serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like
ADC, DAC is called microcontroller.

2. Explain DJNZ instruction of Intel 8051 microcontroller?

 DJNZ Rn, rel Decrement the content of the register Rn and jump if not zero.
 DJNZ direct, rel Decrement the content of direct 8- bit address and jump if not zero.

3. State the function of RS1 and RS0 bits in the flag register of Intel 8051 microcontroller?

RS1, RS0- Register bank select bits

RS1, RS0- Bank

Bank 0

Bank 1

Bank 2

Bank 3

4. Give the alternate functions for the port pins of port3?

RD WR T1 T0

INT 1 INT 0 TXD RXD

 RD – Read data control output

 WR – Write data control output
 T1 – Timer / counter 1 external input or test pin T0 – Timer / counter 0 external input or test
pin INT 1 – Interrupt 1 input pin
 INT 0 – interrupt 0 input pin
 TXD – Transmit data pin for serial port in UART mode
 RXD – Receive data pin for serial port in UART mode

5. Specify the single instruction, which clears the most significant bit of B register of 8051,
without affecting the remaining bits.

Single instruction, which clears the most significant bit of B register of 8051, without
affecting the remaining bits, is CLR B.7.

6. Explain the function of the pins PSEN and EA of 8051.

PSEN: PSEN stands for program store enable. In 8051 based system in which an external

SCE 109 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

ROM holds the program code, this pin is connected to the OE pin of the ROM.

EA: EA stands for external access. When the EA pin is connected to Vcc, program fetched to address
0000H through 0FFFH are directed to the internal ROM and program fetches to addresses
1000H through FFFFH are directed to external ROM/EPROM. When the EA pin is grounded, all
addresses fetched by program are directed to the external ROM/EPROM.

7. Explain the 16-bit registers DPTR and SP of 8051. DPTR:

DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL).

Its function is to hold a 16-bit address. It may be manipulated as a 16- bit data registers. It
serves as a base register in indirect jumps, lookup table instructions and external data transfer.

SP:

SP stands for stack pointer. SP is a 8-bit wide register. It is incremented before data is
stored during PUSH and CALL instructions. The stack array can reside anywhere in-chip RAM.
The stack pointer is initiailsed to 07H after a reset. This causes the stack to begin at location. 08H.

8. Name the special functions registers available in 8051.

 Accumulator
 B Register
 Stack pointer.
 Data pointer
 Interrupt priority control register.
 Interrupt enable control register.

9. Explain the register IE format of 8051.

EA ET2 ES
ET1 EX1 ET0 EX0
EA- Enable all control bit.

 ET2- Timer 2 interrupt enable bit. ES- Enable serial port control bit. ET1- Enable Timer1
control bit.
 EX1-Enable external interrupt1 control bit. ET0-Enable Timer0 control bit.
 EX0-Enable external interrupt0 control bit.

10. Compare Microprocessor and Microcontroller.

Microprocessor Microcontroller

1. Microprocessor contains ALU, general Microcontroller contains the circuitry of Purpose

register counter, clock timing microprocessor and in addition it has Circuit and
interrupt circuit. Built-in ROM, RAM, I/O devices and counter.

2. It has many instructions to move data It has many instructions to move between memory
and CPU. data between memory and CPU.

3. It has one or two bit handling it has many bit handling instructions.
instruction .

SCE 110 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

4. Access times for memory and I/O Less access times for built-in memory
Devices are more. and I/O devices.

5. Microprocessor based system Microcontroller based system requires

requires more hardware less hardware reducing PCB size and
Increasing the reliability.

11. Name the five interrupt sources of 8051?

The interrupt are:

Vector address

 External interrupt 0: IE0: 0003H

 Timers interrupt 0: TF0: 000BH
 External interrupt 1: IE1: 0013H
 Timers interrupt 1: TF1:001BH

Serial interrupt

 Receive interrupt: RI: 0023H

 Transmit interrupt: TI: 0023H

12. Write a program to subtract the contents of RI of Bank0 from the contents of R0 0f Bank2.

MOV PSW, #10

MOV A, R0

MOV PSW, #00

SUBB A, R1

13. How the RS-232 serial bus is interrupt to 1TL logic device?

The RS-232 signal voltage level devices are not compatible with TTL logic levels. Hence for
interfacing TTL devices to RS-232 serial bus, level converters are used. The popularly used level
converters are MC 1488 & MC 1489 or MAX 232.

14. List some of the features of 8096 microcontroller.

 The 8096 is a 16-bit microcontroller.

 The 8096 is designed to use in application which require high speed calculations and fast
I/O operation.
 The high speed I/O section of an 8096 includes a 16-bit timer, a 16- bit counter, a 4 input
programmable edge detector, 4 software timer and counter 6-output programmable events
Generator.
 It has 100 instructions, which can operate on bit, byte, word and double words.

15. List the features of 8051 microcontroller?

The features are

 Single supply +5 volt operation using HMOS technology.

 4096 bytes program memory on chip (not on 8031)

SCE 111 Dept. of ECE

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 128 data register banks

 Four register mode, 16-bit timer/ counter.
 Extensive Boolean processing capabilities.
 64 KB external RAM size
 32 bi-directional individually addressable I/O lines.
 8 bit CPU optimized for control applications.

16. Explain the operating mode 0 of 8051 serial ports?

In this mode serial enters & exits through RXD, TXD outputs the shift clock 8 bits are
transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator
frequency.

17. Explain the operating mode 0 of 8051 ports?

In this mode 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
8 data bits (LSB first) a, programmable 9th data bit, & a stop bit (1).ON transmit the 9th data bit
(TB* in SCON) can be assigned the value of 0 or 1.

For eg: the parity bit (P, in the PSW) could be moved into TB8. On receive the 9th data bit
go in to the RS8 in Special Function Register SCON, while the stop bit is ignored. The baud rate
is programmable to either 1/32, or 1/64 the oscillator frequency.

18. Explain the mode 3 of 8051 serial ports?

In this mode 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
8 data bits (LSB first) a, programmable 9th data bit, & a stop bit (1). In fact, Mode 3 is the same
as Mode 2 in all respect except the baud rate. The baud rate in Mode 3 is variable.

In all the four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI=0 & REN=1. Reception is initiated in
other modes by the incoming start bit if REn=1.

19. List the addressing modes of 8051?

 Direct addressing
 Register addressing
 Register indirect addressing
 Implicit addressing
 Immediate addressing
 Index addressing
 Bit addressing

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SCE 112 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

8 Marks Questions

1. Explain the different serial communication modes in 8051

2. Discuss the peripheral interface of 8051

3. Explain the memory structure of 8051

4. Explain the interrupt structure of 8051 microcontroller Explain how interrupts are Prioritized

5. What is the difference between the Microprocessors and Microcontrollers?

6. Explain the I/O port structure of 8051

7. Discuss the peripheral interface of 8051

8. Explain the different serial communication modes in 8051

9. Explain the timing diagram for 8051

10. Discuss in detail about operation of addressing modes

………………………………………………………………….

16 Marks Questions

1. Describe the architecture of 8051 with neat diagram

2. States various modes available for timer in 8051

3. Explain the functional pin diagram of 8051 Microcontroller

4. Discuss in detail about the operation of interrupt.

5. With an example, explain the operation of instruction format in 8051

………………………………………………………………….

SCE 113 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIT V

MICRO CONTROLLER PROGRAMMING & APPLICATIONS

Two Marks Questions with Answers

1. Write a program using 8051 assembly language to change the data 55h stored in the lower
byte of the data pointer register to AAH using rotate instruction?

MOV DPL,#55H

MOV A,DPL RL A

LABEL : SJMP Label

2. Explain the contents of the accumulator after the execution of the following program
segments?

MOV A,#3CH

MOV R4,#66H ANL A,R4

A 3C R4 66

A 24

3. Write a program to load accumulator a,DPH and DPL with 30H?

MOV A,#30

MOV DPH,A MOV DPL,A

4. Write a program to perform multiplication of 2 nos using 8051?

MOV A,#data 1

MOV B,#data 2

MUL AB

MOV DPTR,#5000

MOV @DPTR,A(lower value) INC DPTR

MOV A,B

MOVX@DPTR,A

5. Write a program to mask the 0th &7th bit using 8051?

MOV A,#data

ANL A,#81

SCE 114 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

MOV DPTR,#4500

MOVX @DPTR,A LOOP SJMP LOOP

6. Write about CALL statement in 8051?

There are two subroutine CALL instructions. They are

 LCALL(Long CALL)
 ACALL(Absolute CALL)

Each increments the pc to the 1st byte of the instruction & pushes them in to the stack.

7. Write about the jump statement?

There are three forms of jump. They are

 LJMP(Long-jump)-address 16
 AJMP(Absolute jump)-address 11
 Sjmp(short jump)-relative address

8. Write a program to load accumulator DPH & DPL using 8051?

MOV A,#30

MOV DPH,A MOV DPL,A

9. Write a program to find 2’s complement using 8051?

MOV A,R0

CPL A INC A

10. Write a program to add two 8-bit numbers using 8051?

MOV A,#30H

ADD A,#50H

11. Write a program to swap two numbers using 8051?

MOV A,#data

SWAP A

12. Write a program to subtract two 8-bit numbers & exchange the digits using 8051?

MOV A,#9F MOV R0,#40

SUBB A,R0

SWAP A

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13. Write a program to subtract the contents of R1 of bank 0from the contents of R0 of
bank 2 using 8051?

MOV PSW,#10

MOV A,R0

MOV PSW,#00

SUBB A,R1

14. Explain the operating mode0 of 8051 serial ports?

In this mode serial enters & exits through RXD,TXD output the shift clock 8 bits are transmitted
or received 8 data bits(LSB first).the baud rate is fixed at 1/12 the oscillator frequency.

15. Explain the operating mode2 of 8051 serial ports?

In this mode 11 bits are transmitted (through TXD)or received(through RXD)A start
bit(0),8 data bits(LSB first),a programmable 9th data bit & a stop bit(1) ON transmit the 9th data
bit(TB*in SCON) can be assigned the value of 0 or 1.or for eg: the parity bit(p,in the PSW) could be
moved into TB8. On receive the 9th data bit go in to the RB8 in special function register SCON,
while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator
frequency.

16. Explain the mode3 of 8051 serial ports?

In this mode 11 bits are transmitted(through TXD)or received(through RXD): a start

bit(0).8 data bits(LSB first), a programmable 9th data bit,& a stop bit(1).in fact, mode3 is the same as
mode2 in all respects except the baud rate. the baud rate in mode3 is variable.in all the four modes,
transmission is initiated by any instruction that uses SBUF as a destination register.
Reception is initiated by any instruction that uses SBUF as a destination register. Reception is initiated
in mode0 by the condition R1=0 & REN=1.reception is initiated in other modes by the incoming start
bit if REN-1.

17. What are the tasks involved in keyboard interfacing?

The task involved in keyboard interfacing are sensing a keyboard interfacing are sensing a
key actuation, de bouncing the key and generating key codes(decoding the key).these task are
performed software if the keyboard is interfaced through ports and they are performed by
hardware if the keyboard is interfaced through 8279.

18. How a keyboard matrix is formed in keyboard interface?

The return lines RL0 to RL7 of 8279 are used to form the columns of keyboard matrix.in
decoded scan the scan lines SLO to SL3 of 8279 are used to form the rows of keyboard matrix. In
encoded scan mode, the output lines of external decoder are used as rows of keyboard matrix.

19. What is scanning in keyboard and what is scan time?

The process of sending a zero to each row of a keyboard matrix and reading the columns for
key actuation is called scanning. The scan time is the time taken by the processor to scan all the
rows one by one starting from first row and coming back to the first row.

SCE 116 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

20. What is scanning in display and what is the scan time?

In display devices the process of sending display codes to 7-segment LED’S to display the
led’s one by one is called scanning. The scan time is the time taken to display all the 7- segment
LED’S one by one, starting from first LED and coming back to the first LED again.

21. Give some ex of input devices to microprocessor-based systems

The input devices used in the microprocessor- based system are keyboards, DIP switches ADC,
floppy disc, etc.

………………………………………………………………….

8 Marks Questions

1. Write 8051 ALP to read data from port I when negative edge triggered at INTO and supply the data

to port 2 by masking the upper 4 bits

2. Write 8051 ALP to transmit ‘Hello World’ to PC at 9600 baud for external crystal frequency of

11.0592MHz

3. Explain addition and subtraction instructions of 8051

4. Explain various types of jump instructions according to range

5. Write a 8051 ALP to find Fibonacci series of N given numbers

6. Write a 8051 ALP to find the average of given N numbers

7. Discuss the operation of Data transfer operation.

8. Write the program for closed loop control of servo motor

9. Write the program for stepper motor control

10. Write the program for Washing Machine Control.

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SCE 117 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

16 Marks Questions

1. With a neat circuit diagram explain how a 4 х 4 keypad is interfaced with 8051 microcontroller and

write 8051 ALP for keypad scanning

2. Draw the schematic for interfacing a stepper motor with 8051 microcontroller and write 8051 ALP

for changing speed and direction of motor

3. Draw the schematic for interfacing a servo motor with 8051 microcontroller and write 8051 ALP for

servo motor control

4. Explain Data Transfer and manipulation instructions of 8051

5. Explain Control & I/O instructions of 8051 with an example

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SCE 118 Dept. of ECE

EE2354 MICROPROCESSOR AND MICROCONTROLLER

UNIVERSITY
QUESTION PAPERS

SCE 119 Dept. of ECE

 Reg. No. :

Question Paper Code : 11322

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011
Sixth Semester
Electrical and Electronics Engineering

21
EE 2354 — MICROPROCESSORS AND MICROCONTROLLERS
(Regulation 2008)
Time : Three hours Maximum : 100 marks
Answer ALL questions

4
PART A — (10 × 2 = 20 marks)
1. Specify the size of data, address, memory word and memory capacity of
8085 microprocessor.
2. How is the memory segment accessed by 8086 microprocessor identified?
3. State the function of given 8085 instructions: JP, JPE, JPO, JNZ.
4. How is PUSH B instruction executed? Find the status after the execution.
21
5. What are the different ways to end the interrupt execution in 8259
programmable Interrupt controller?
6. What is the function of Scan section in 8279 programmable
keyboard/Display Controller?
7. List the alternative functions assigned to Port 3 pins of 8051
4

microcontroller.
8. Mention the size of DPTR and Stack Pointer in 8051 microcontroller.
9. What is the operation of the given 8051 microcontroller instructions: XRL
A, direct?
10. What are the different operations performed by Boolean variable
instructions of 8051?
21

PART B — (5 × 16 = 80 marks)

11. (a) (i) Explain the architecture, data flow and instruction execution of
8085 microprocessor. (8)
(ii) With timing diagram, explain the memory read operation in
8085 microprocessor. (8)
4

Or
(b) (i) Show the pin configuration and function of signals of 8086
microprocessor. (8)
(ii) Show the memory organization and interfacing with 8086
microprocessor. Explain how the memory is accessed. (8)

12. (a) (i) Describe the instruction format and addressing modes of 8085
microprocessor. (8)
 (ii) Write an assembly language program based on 8085
microprocessor instruction set to search the smallest data in a
set. (8)

Or
(b) (i) With suitable example, discuss about 8085 microprocessor
instructions used for data manipulation. (8)
(ii) Write an assembly language program based on 8085

21
microprocessor instruction set to find the square root of data
from 1 to n using Lookup table. (8)

13. (a) (i) Explain the operation of 8255 PPI Port A programmed as input
and output in Mode 1 with necessary handshaking signals. (8)
(ii) Show and explain the ADC interfacing with 8085

4
microprocessor.
(8)

Or
(b) With functional block diagram, explain the operation and
programming of 8251 USART in detail. (16)

14. (a) Discuss about the organization of Internal RAM and Special function
21
registers of 8051 microcontroller in detail. (16)

Or
(b) (i) Explain the Interrupt structure with the associated registers in
8051 microcontroller. (8)
(ii) Explain in detail the modes of operation of Timer unit in 8051
4

microcontroller. (8)

15. (a) (i) Explain the Data transfer instructions and Program control
instructions of 8051 microcontroller. (8)
21

Or
(b) (i) Explain the interfacing of Keyboard/Display with 8051
microcontroller. (8)
(ii) Explain the Servomotor control using 8051 microcontroller. (8)
4

————––––——

2 11322
 Anna University
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Electrical and Electronics Engineering
EE 2354 — MICROPROCESSORS AND MICROCONTROLLER
(Regulation 2008)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. Draw the schematic of latching low-order address bus in 8085 microprocessor.
2. If the stack segment register contains 3000h and stack pointer register contains 8434h, what is the physical address of the
top of the stack in 8086 microprocessor?
3. Why do we need look-up table?
4. How are the 8085 instructions classified according to the functional categories?
5. Draw the ‘Mode Word’ format of 8251 USART.
6. State the use of ISR and PR registers in 8259 PIC.
7. List the on-chip peripherals of 8051 microcontroller.
8. What are the addressing modes of 8051 microcontroller?
9. Why do we need opto-isolator circuit between microcontroller and the Stepper motor?
10. Mention the I/O instructions of 8051 microcontroller.
PART B — (5 × 16 = 80 marks)
11. (a) (i) Explain in detail the 8085 interrupt structure. (8)
(ii) Draw the timing diagram for IN and OUT instruction of 8085 and explain. (8)
Or
(b) (i) Draw the internal block diagram of 8086 and explain the bus interface unit and execution unit. (8)
(ii) How address decoding is done in memory Interface. (8)
12. (a) (i) Write a program to count from 0 to 9 with one second delay between each count. At the count of 9, the counter
should reset itself to 0 and repeat the sequence continuously. Assume the clock frequency is 1 MHz. (8)
(ii) Write a program with a flowchart to multiply two 8-bit numbers.(8)
Or
(b) (i) Compare the similarities and differences of CALL and RET instructions with PUSH and POP instructions. (8)
(ii) Sixteen bytes are stored in memory locations at XX50h to XX5Fh. Transfer the entire block of data to new memory
locations starting at XX70h. (8)
13. (a) (i) Explain the operating modes of 8255 programmable peripheral interface. (8)
(ii) Draw the logical block diagram of 8279 keyboard display controller and explain. (8)
Or
(b) (i) Draw the control word of 8253 timer/counter and explain the operating modes of 8253 timer/counter. (8)
(ii) Why do we need A/D converter and D/A converter? Draw the block diagram to interface 8085 microprocessor with A/D
convertor and D/A convertor. (8)
14. (a) (i) Explain the program memory and data memory structure of 8051 microcontroller. (8)
(ii) Draw the pin diagram of 8051 microcontroller and explain its port structure. (8)
Or
(b) (i) Draw the TMOD register format and explain the different operating modes of timer in 8051 microcontroller. (8)
(ii) Explain how serial communication is performed in 8051 microcontroller. (8)
15. (a) (i) Explain with a program to rotate the stepper motor in both clockwise and anticlockwise direction using 8051
microcontroller. (8)
(ii) How to interface a 7 segment display using 8051 microcontroller. (8)
Or
(b) (i) How 8051 is used in washing machine control? (8)
(ii) How do you interface a 4 × 4 matrix keyboard using 8051 microcontroller? (8)
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