CAT25020VI-G CAT25010VI-GT3 CAT25040VI-GT3 CAT25040VP2I- CAT25010HU4I-

GT3 GT3
CAT25010, CAT25020,
CAT25040

1-Kb, 2-Kb and 4-Kb SPI

Serial CMOS EEPROM
Description
The CAT25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS www.onsemi.com
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16−byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD SOIC−8 UDFN−8
input may be used to pause any serial communication with the V SUFFIX HU4 SUFFIX
CASE 751BD CASE 517AZ
CAT25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.

Features
• 20 MHz (5 V) SPI Compatible
PDIP−8* TSSOP−8
• 1.8 V to 5.5 V Supply Voltage Range L SUFFIX Y SUFFIX
• SPI Modes (0,0) & (1,1) CASE 646AA CASE 948AL

• 16−byte Page Write Buffer

• Self−timed Write Cycle PIN CONFIGURATION
• Hardware and Software Protection CS 1 VCC
• Block Write Protection
SO HOLD
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology WP SCK

• 1,000,000 Program/Erase Cycles VSS SI

• 100 Year Data Retention PDIP (L), SOIC (V),

• Industrial and Extended Temperature Range
TSSOP (Y), UDFN (HU4)

• PDIP, SOIC, TSSOP 8−Lead and UDFN 8−Pad Packages For the location of Pin 1, please consult the
corresponding package drawing.
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
* Not recommended for new designs
Compliant
PIN FUNCTION
VCC
Pin Name Function
CS Chip Select
SI
CS SO Serial Data Output
CAT25010
WP CAT25020 SO WP Write Protect
CAT25040
HOLD VSS Ground
SCK SI Serial Data Input
SCK Serial Clock
VSS
HOLD Hold Transmission Input
Figure 1. Functional Symbol VCC Power Supply

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

July, 2015 − Rev. 25 CAT25010/D
 CAT25010, CAT25020, CAT25040

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units
Operating Temperature −45 to +130 °C

Storage Temperature −65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) −0.5 to VCC + 0.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years

Table 3. D.C. OPERATING CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICC Supply Current Read, Write, VCC = 5.0 V, 10 MHz / −40°C to 85°C 2 mA
SO open
5 MHz / −40°C to 125°C 2 mA
ISB1 Standby Current VIN = GND or VCC, CS = VCC, 2 mA
WP = VCC, VCC = 5.0 V
ISB2 Standby Current VIN = GND or VCC, CS = VCC, TA = −40°C to +85°C 4 mA
WP = GND, VCC = 5.0 V
TA = −40°C to +125°C 5 mA
IL Input Leakage Current VIN = GND or VCC −2 2 mA
ILO Output Leakage CS = VCC, TA = −40°C to +85°C −1 1 mA
Current VOUT = GND or VCC
TA = −40°C to +125°C −1 2 mA
VIL Input Low Voltage −0.5 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC + 0.5 V
VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V
VOH1 Output High Voltage VCC > 2.5 V, IOH = −1.6 mA VCC − 0.8 V V
VOL2 Output Low Voltage VCC > 1.8 V, IOL = 150 mA 0.2 V
VOH2 Output High Voltage VCC > 1.8 V, IOH = −100 mA VCC − 0.2 V V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (SO) VOUT = 0 V 8 pF
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.

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 CAT25010, CAT25020, CAT25040

Table 5. A.C. CHARACTERISTICS − Mature Product

(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 4, 8)
VCC = 1.8 V − 5.5 V / −405C to +855C VCC = 2.5 V − 5.5 V
VCC = 2.5 V − 5.5 V / −405C to +1255C −405C to +855C

Symbol Parameter Min Max Min Max Units

fSCK Clock Frequency DC 5 DC 10 MHz

tSU Data Setup Time 40 20 ns

tH Data Hold Time 40 20 ns
tWH SCK High Time 75 40 ns
tWL SCK Low Time 75 40 ns
tLZ HOLD to Output Low Z 50 25 ns
tRI (Note 5) Input Rise Time 2 2 ms
tFI (Note 5) Input Fall Time 2 2 ms
tHD HOLD Setup Time 0 0 ns
tCD HOLD Hold Time 10 10 ns
tV Output Valid from Clock Low 75 40 ns
tHO Output Hold Time 0 0 ns
tDIS Output Disable Time 50 20 ns
tHZ HOLD to Output High Z 100 25 ns
tCS CS High Time 140 70 ns
tCSS CS Setup Time 30 15 ns
tCSH CS Hold Time 30 15 ns
tCNS CS Inactive Setup Time 20 15 ns
tCNH CS Inactive Hold Time 20 15 ns
tWPS WP Setup Time 10 10 ns
tWPH WP Hold Time 10 10 ns
tWC (Note 7) Write Cycle Time 5 5 ms

Table 6. POWER−UP TIMING (Notes 5, 6)

Symbol Parameter Max Units
tPUR Power−up to Read Operation 1 ms

tPUW Power−up to Write Operation 1 ms

4. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev. C) the tCSH is defined relative to the negative clock edge (please refer to data sheet Doc. No.
MD−1006 Rev. U)

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 CAT25010, CAT25020, CAT25040

Table 7. A.C. CHARACTERISTICS – New Product (Rev E)

(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended), unless otherwise specified.) (Note 9)
VCC = 1.8 V − 5.5 V VCC = 2.5 V − 5.5 V VCC = 4.5 V − 5.5 V
−405C to +855C −405C to +1255C −405C to +855C

Symbol Parameter Min Max Min Max Min Max Units

fSCK Clock Frequency DC 5 DC 10 DC 20 MHz
tSU Data Setup Time 20 10 5 ns
tH Data Hold Time 20 10 5 ns
tWH SCK High Time 75 40 20 ns
tWL SCK Low Time 75 40 20 ns
tLZ HOLD to Output Low Z 50 25 25 ns
tRI (Note 10) Input Rise Time 2 2 2 ms
tFI (Note 10) Input Fall Time 2 2 2 ms
tHD HOLD Setup Time 0 0 0 ns
tCD HOLD Hold Time 10 10 5 ns
tV Output Valid from Clock Low 70 35 20 ns
tHO Output Hold Time 0 0 0 ns
tDIS Output Disable Time 50 20 20 ns
tHZ HOLD to Output High Z 100 25 25 ns
tCS CS High Time 80 40 20 ns
tCSS CS Setup Time 30 30 15 ns
tCSH CS Hold Time 30 30 20 ns
tCNS CS Inactive Setup Time 20 20 15 ns
tCNH CS Inactive Hold Time 20 20 15 ns
tWPS WP Setup Time 10 10 10 ns
tWPH WP Hold Time 10 10 10 ns
tWC (Note 12) Write Cycle Time 5 5 5 ms

Table 8. POWER−UP TIMING (Notes 10, 11)

Symbol Parameter Min Max Units
tPUR Power−up to Read Operation 0.1 1 ms

tPUW Power−up to Write Operation 0.1 1 ms

9. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF

10. This parameter is tested initially and after a design or process change that affects the parameter.

11. tPUR and tPUW are the delays required from the time VCC is stable at the operating voltage until the specified operation can be initiated.

12. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.

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 CAT25010, CAT25020, CAT25040

Pin Description Functional Description

SI: The serial data input pin accepts op−codes, addresses The CAT25010/20/40 devices support the Serial
and data. In SPI modes (0,0) and (1,1) input data is latched Peripheral Interface (SPI) bus protocol, modes (0,0) and
on the rising edge of the SCK clock input. (1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 9.
SO: The serial data output pin is used to transfer data out of
Reading data stored in the CAT25010/20/40 is
the device. In SPI modes (0,0) and (1,1) data is shifted out
accomplished by simply providing the READ command and
on the falling edge of the SCK clock.
an address. Writing to the CAT25010/20/40, in addition to
SCK: The serial clock input pin accepts the clock provided a WRITE command, address and data, also requires
by the host and used for synchronizing communication enabling the device for writing by first setting certain bits in
between host and CAT25010/20/40. a Status Register, as will be explained later.
CS: The chip select input pin is used to enable/disable the After a high to low transition on the CS input pin, the
CAT25010/20/40. When CS is high, the SO output is CAT25010/20/40 will accept any one of the six instruction
tri−stated (high impedance) and the device is in Standby op−codes listed in Table 9 and will ignore all other possible
Mode (unless an internal write operation is in progress). 8−bit combinations. The communication protocol follows
Every communication session between host and the timing from Figure 2.
CAT25010/20/40 must be preceded by a high to low transition
and concluded with a low to high transition of the CS input. Table 9. INSTRUCTION SET (Note 13)
WP: The write protect input pin will allow all write Instruction Opcode Operation
operations to the device when held high. When WP pin is WREN 0000 0110 Enable Write Operations
tied low all write operations are inhibited. WRDI 0000 0100 Disable Write Operations
HOLD: The HOLD input pin is used to pause transmission RDSR 0000 0101 Read Status Register
between host and CAT25010/20/40, without having to
retransmit the entire sequence at a later time. To pause, WRSR 0000 0001 Write Status Register
HOLD must be taken low and to resume it must be taken READ 0000 X011 Read Data from Memory
back high, with the SCK input low during both transitions. WRITE 0000 X010 Write Data to Memory
When not used for pausing, the HOLD input should be tied
13. X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
to VCC, either directly or through a resistor.
tCS

CS

tCSS tWH tWL

tCNH tCSH tCNS

SCK

tH tRI
tSU tFI
VALID
SI
IN
tV tV tDIS
tHO
HI−Z VALID HI−Z
SO
OUT

Figure 2. Synchronous Data Timing

Status Register
The Status Register, as shown in Table 10, contains a Write Enable state and when set to 0, the device is in a Write
number of status and control bits. Disable state.
The RDY (Ready) bit indicates whether the device is busy The BP0 and BP1 (Block Protect) bits determine which
with a write operation. This bit is automatically set to 1 during blocks are currently write protected. They are set by the user
an internal write cycle, and reset to 0 when the device is ready with the WRSR command and are non−volatile. The user is
to accept commands. For the host, this bit is read only. allowed to protect a quarter, one half or the entire memory,
The WEL (Write Enable Latch) bit is set/reset by the by setting these bits according to Table 11. The protected
WREN/WRDI commands. When set to 1, the device is in a blocks then become read−only.

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 CAT25010, CAT25020, CAT25040

Table 10. STATUS REGISTER

7 6 5 4 3 2 1 0
1 1 1 1 BP1 BP0 WEL RDY

Table 11. BLOCK PROTECTION BITS

Status Register Bits

BP1 BP0 Array Address Protected Protection

0 0 None No Protection

0 1 CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF Quarter Array Protection

1 0 CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF Half Array Protection
1 1 CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF Full Array Protection

WRITE OPERATIONS
The CAT25010/20/40 device powers up into a write instruction to the CAT25010/20/40. Care must be taken to
disable state. The device contains a Write Enable Latch take the CS input high after the WREN instruction, as
(WEL) which must be set before attempting to write to the otherwise the Write Enable Latch will not be properly set.
memory array or to the status register. In addition, the WREN timing is illustrated in Figure 3. The WREN
address of the memory location(s) to be written must be instruction must be sent prior to any WRITE or WRSR
outside the protected area, as defined by BP0 and BP1 bits instruction.
from the status register. The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
Write Enable and Write Disable operations by resetting the WEL bit, will protect the device
The internal Write Enable Latch and the corresponding against inadvertent writes.
Status Register WEL bit are set by sending the WREN

CS

SCK

SI 0 0 0 0 0 1 1 0

HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 3. WREN Timing

CS

SCK

SI 0 0 0 0 0 1 0 0

HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing

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 CAT25010, CAT25020, CAT25040

Byte Write Page Write

Once the WEL bit is set, the user may execute a write After sending the first data byte to the CAT25010/20/40,
sequence, by sending a WRITE instruction, a 8−bit address the host may continue sending data, up to a total of 16 bytes,
and data as shown in Figure 5. For the CAT25040, bit 3 of according to timing shown in Figure 6. After each data byte,
the write instruction opcode contains A8 address bit. the lower order address bits are automatically incremented,
Internal programming will start after the low to high CS while the higher order address bits (page address) remain
transition. During an internal write cycle, all commands, unchanged. If during this process the end of page is
except for RDSR (Read Status Register) will be ignored. exceeded, then loading will “roll over” to the first byte in the
The RDY bit will indicate if the internal write cycle is in page, thus possibly overwriting previously loaded data.
progress (RDY high), or the device is ready to accept Following completion of the write cycle, the
commands (RDY low). CAT25010/20/40 is automatically returned to the write
disable state.

CS

0 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23
SCK

OPCODE BYTE ADDRESS DATA IN

SI 0 0 0 0 X* 0 1 0 A7 A0 D7 D6 D5 D4 D3 D2 D1 D0

HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 5. Byte WRITE Timing

CS

0 1 2 3 4 5 6 7 8 13 14 15 16−23 24−31 16+(N−1)x8−1..16+(N−1)x8

SCK 16+Nx8−1

OPCODE BYTEADDRESS DATA IN Data Byte N

SI 0 0 0 0 X* 0 1 0 A7 A0 7..1 0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 6. Page WRITE Timing

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 CAT25010, CAT25020, CAT25040

Write Status Register Write Protection

The Status Register is written by sending a WRSR When WP input is low all write operations to the memory
instruction according to timing shown in Figure 7. Only bits array and Status Register are inhibited. WP going low while
2 and 3 can be written using the WRSR command. CS is still low will interrupt a write operation. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the Status Register
or memory array. The WP input timing is shown in Figure 8.

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

OPCODE DATA IN
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 7. WRSR Timing

tWPS tWPH

CS

SCK

WP

WP

Dashed Line = mode (1, 1)

Figure 8. WP Timing

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 CAT25010, CAT25020, CAT25040

READ OPERATIONS

Read from Memory Array Read Status Register

To read from memory, the host sends a READ instruction To read the status register, the host simply sends a RDSR
followed by a 8−bit address (for the CAT25040, bit 3 of the command. After receiving the last bit of the command, the
read instruction opcode contains A8 address bit). CAT25010/20/40 will shift out the contents of the status
After receiving the last address bit, the CAT25010/20/40 register on the SO pin (Figure 10). The status register may
will respond by shifting out data on the SO pin (as shown in be read at any time, including during an internal write cycle.
Figure 9). Sequentially stored data can be read out by simply While the internal write cycle is in progress, the RDSR
continuing to run the clock. The internal address pointer is command will output the full content of the status register
automatically incremented to the next higher address as data (New product, Rev. E) or the RDY (Ready) bit only (i.e.,
is shifted out. After reaching the highest memory address, data out = FFh) for previous product revisions C, D (Mature
the address counter “rolls over” to the lowest memory product). For easy detection of the internal write cycle
address, and the read cycle can be continued indefinitely. completion, both during writing to the memory array and to
The read operation is terminated by taking CS high. the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.

CS

0 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 21 22
SCK

OPCODE BYTE ADDRESS

SI 0 0 0 0 X* 0 1 1 A7 A0

DATA OUT
HIGH IMPEDANCE
SO D7 D6 D5 D4 D3 D2 D1 D0
Dashed Line = mode (1, 1) MSB
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 9. READ Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK

OPCODE
SI 0 0 0 0 0 1 0 1

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
Dashed Line = mode (1, 1) MSB

Figure 10. RDSR Timing

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 CAT25010, CAT25020, CAT25040

Hold Operation VCC drops below the POR trigger level. This bi−directional
The HOLD input can be used to pause communication POR behavior protects the device against ‘brown−out’
between host and CAT25010/20/40. To pause, HOLD must failure following a temporary loss of power.
be taken low while SCK is low (Figure 11). During the hold The CAT25010/20/40 device powers up in a write disable
condition the device must remain selected (CS low). During state and in a low power standby mode. A WREN instruction
the pause, the data output pin (SO) is tri−stated (high must be issued prior to any writes to the device.
impedance) and SI transitions are ignored. To resume After power up, the CS pin must be brought low to enter
communication, HOLD must be taken high while SCK is low. a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
Design Considerations a write disable mode. The CS input must be set high after the
The CAT25010/20/40 devices incorporate Power−On proper number of clock cycles to start the internal write
Reset (POR) circuitry which protects the internal logic cycle. Access to the memory array during an internal write
against powering up in the wrong state. The device will cycle is ignored and programming is continued. Any invalid
power up into Standby mode after VCC exceeds the POR op−code will be ignored and the serial output pin (SO) will
trigger level and will power down into Reset mode when remain in the high impedance state.

CS
tCD tCD

SCK

tHD

HOLD tHD

tHZ
HIGH IMPEDANCE
SO
tLZ
Dashed Line = mode (1, 1)

Figure 11. HOLD Timing

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 CAT25010, CAT25020, CAT25040

PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01
ISSUE A

SYMBOL MIN NOM MAX

A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56

E1 b2 1.14 1.52 1.78

c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
E1 6.10 6.35 7.11
e 2.54 BSC
eB 7.87 10.92
PIN # 1
IDENTIFICATION L 2.92 3.30 3.80
D

TOP VIEW
E

A2
A

A1

c
b2
L

eB
e b

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.

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 CAT25010, CAT25020, CAT25040

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01
ISSUE O

SYMBOL MIN NOM MAX

A 1.35 1.75
A1 0.10 0.25
b 0.33 0.51
c 0.19 0.25
E1 E D 4.80 5.00
E 5.80 6.20
E1 3.80 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
PIN # 1
IDENTIFICATION θ 0º 8º

TOP VIEW

D h

A1 θ
A

c
e b L

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.

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 CAT25010, CAT25020, CAT25040

PACKAGE DIMENSIONS

TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b

SYMBOL MIN NOM MAX

A 1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b 0.19 0.30
E1 E c 0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 1.00 REF
L1 0.50 0.60 0.75
θ 0º 8º

TOP VIEW

A2 c
A q1

A1 L1
L
SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.

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 CAT25010, CAT25020, CAT25040

PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ−01
ISSUE O

D A b e

DAP SIZE 1.8 x 1.8

E E2

PIN #1
IDENTIFICATION

A1
PIN #1 INDEX AREA D2

TOP VIEW SIDE VIEW BOTTOM VIEW

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
0.065 REF DETAIL A A3 A
b 0.20 0.25 0.30
D 1.95 2.00 2.05 FRONT VIEW
D2 1.35 1.40 1.45
E 2.95 3.00 3.05
E2 1.25 1.30 1.35
e 0.50 REF
L 0.25 0.30 0.35

0.065 REF
Notes: A3 0.0 - 0.05
Copper Exposed
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252. DETAIL A

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 CAT25010, CAT25020, CAT25040

ORDERING INFORMATION
Specific
Device
Marking
Device Order Number (Note 14) Package Type Temperature Range Lead Finish Shipping
CAT25010HU4I−GT3 S0U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel

CAT25010LI−G 25010E PDIP−8 −40°C to +85°C NiPdAu Tube, 50 Units

(Note 17)

CAT25010VI−G 25010E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tube, 100 Units
CAT25010VI−GT3 25010E SOIC−8, JEDEC −40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25010YI−G S01E TSSOP−8 −40°C to +85°C NiPdAu Tube, 100 Units
CAT25010YI−GT3 S01E TSSOP−8 −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel

CAT25020HU4I−GT3 S1U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25020LI−G 25020E PDIP−8 −40°C to +85°C NiPdAu Tube, 50 Units
(Note 17)

CAT25020VI−G 25020E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tube, 100 Units
CAT25020VI−GT3 25020E SOIC−8, JEDEC −40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25020YI−G S02E TSSOP−8 −40°C to +85°C NiPdAu Tube, 100 Units
CAT25020YI−GT3 S02E TSSOP−8 −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel

CAT25040HU4I−GT3 S2U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040LI−G 25040E PDIP−8 −40°C to +85°C NiPdAu Tube, 50 Units
(Note 17)

CAT25040VI−G 25040E SOIC−8, JEDEC −40°C to +85°C NiPdAu Tube, 100 Units
CAT25040VI−GT3 25040E SOIC−8, JEDEC −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040YI−G S04E TSSOP−8 −40°C to +85°C NiPdAu Tube, 100 Units
CAT25040YI−GT3 S04E TSSOP−8 −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
14. Specific Device Marking shows the first row top marking for new product (Revision E).
15. All packages are RoHS−compliant (Lead−free, Halogen−free).
16. The standard lead finish is NiPdAu.
17. Not recommended for new designs.
18. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
19. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
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Email: [email protected] Phone: 81−3−5817−1050 Sales Representative

www.onsemi.com CAT25010/D
15
CAT25010YI-GT3 CAT25020HU4I- CAT25020VI-GT3 CAT25020YI-GT3 CAT25040VI-G
GT3

CAT25040YI-GT3
 CAT25020VI-G CAT25010VI-GT3 CAT25040VI-GT3 CAT25040VP2I- CAT25010HU4I-
GT3 GT3

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