Programmable Read Only Memory

2019 - 2020 Programmable Read Only Memory
Final Exam Report,

This report is submitted to the electrical department,
College of Engineering, Kirkuk University.
Student Name: Amjad Aidan Musa
Subject:
Stage: forth
Student Signature:
A programmable read only memory (PROM) is a device that includes both the
decoder and the OR gates within a single IC package. It consists of n input lines and m
output lines. Each bit combination of the input variables is called an address. Each bit
combination that comes out of the output lines is called a word. The number of bits per
word is equal to the number of output lines, m. The address specified in binary number
denotes one of the minterms of n variables. The number of distinct addresses possible
with n input variables is 2". An output word can be selected by a unique address, and
since there are 2" distinct addresses in PROM, there are 2" distinct words in the PROM.
The word available on the output lines at any given time depends the address value
applied to the input lines.
Let us consider 64 x 4 PROM. The PROM consists of 64 words of 4 bits each. This
means that there are four output lines and particular word from 64 words presently
available on the output lines is determined from the six input lines. There are only six
inputs in a 64 x addresses or minterms. For each address input, there is a unique
selected word. Thus, if the input address is 000000, word number 0 is selected and
applied to the output lines. If the input address is 111111, word number 63 is selected
and applied to the output lines. 4 PROM because 2° = 64, and with six variables, we can
specify 64
The Fig. 1.2 shows the internal logic construction of a 64 x 4 PROM. The six input
variables are decoded in 64 lines by means of 64 AND gates and 6 inverters. Each output
of the decoder represents one of the minterms of a function of six variables. The 64
outputs of the decoder are connected through fuses to each OR gate. Only four of these
fuses are shown in the diagram, but actually each OR gate has 64 inputs and each input
goes through fuse that can be blown as desired.
1
Fig. 1.1
The PROM is a two level implementation in sum of minterms form. Let us see AND-OR
and AND-OR-INVERTER implementation of PROM. Fig. 1.3 shows the 4 x 2 PROM with
AND-OR and AND-OR-INVERTER implementations.
Fig. 1.3(a)
2
Fig. 1.3(b)
1.2.1 Combination Logic Implementation using PROM Looking at the logic diagram of
the PROM, we can realize that each output provides the sum of all the minterms of n
input variables. We know that any Boolean function can be expressed in sum of
minterms form. By breaking the links of those minterms not included in the function,
each PROM output can be made to represent the Boolean function of one of the output
variables in the combinational circuit. For an n-input, m-output combination circuit, we
need a 2" x m ROM
Example 1.1: Design a combinational using a PROM. The circuit accepts 3-bit binary
number and generates its equivalent Excess-3 code.
Solution : Let us derive the truth table for the given combination circuit. Table 1.1 shows
the truth table
Table 1.1 truth table for 3-bit binary to excess-3 converter
3
In practice when we are designing combinational circuits with PROM, it is not necessary
to show the internal gate connections of fuses inside the unit, as shown in the Fig. 1.4.
This was shown for demonstration purpose only. The designer has to only specify the
PROM (inputs and outputs) and its truth table, as shown in the Fig. 1.5.
fig. 1.4 3-bit binary to Excess-3 converter using PROM
fig. 1.5 (a) Block diagram Table 1.2 (b) PROM truth table
Example: 1.2 show the address ranges (first address and the last address)
for the rest address 32 x 2 PROM chips? Show how you get it?
Solution :
32—memory locations
2- Each locations
4
32 locations can be elected using (2^5)
5= input lines
32 x 2 ===> 64 bits ----size of ROM
*we can start at 00000 end at 11111
*here Each memory location has 2-bit data
*In hexa 00H starting to 1FH Ending
Example: 1.3 It is desired to combine several 1k X 8 PROM to produce a total

capacity of 4k X 8. how many PROM chips are required?
Solution :
ROM is generally represented as 2^nxm
Where n is the number of address lines. For
1kx8 ROM
2^n =1k
==> 2^n=2^10
=>n=10
10 Address lines are required (A0-A9)
For,
4kx8 ROM
2^n =4k
2^n =2^2X2^10
n=12
12 Address lines are required (A0-A11)
5
REFERENCES
[1] Digital Electronics By A.P. Godse, D.A. Godse, D.A. Godse ch4 p97
[2] Digital Logic Circuits By A.P.Godse, D.A.Godse ch9 p2
[3] Digital Principles & System Design By A.P.Godse, D.A.Godse ch5 p27

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2019 - 2020 Programmable Read Only Memory

Final Exam Report,

Student Name: Amjad Aidan Musa

Table 1.1 truth table for 3-bit binary to excess-3 converter

fig. 1.4 3-bit binary to Excess-3 converter using PROM

32 x 2 ===> 64 bits ----size of ROM

*we can start at 00000 end at 11111

*here Each memory location has 2-bit data

*In hexa 00H starting to 1FH Ending

Example: 1.3 It is desired to combine several 1k X 8 PROM to produce a total

ROM is generally represented as 2^nxm

Where n is the number of address lines. For

10 Address lines are required (A0-A9)

12 Address lines are required (A0-A11)

[2] Digital Logic Circuits By A.P.Godse, D.A.Godse ch9 p2

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