Pipelined Circuits Worksheet

Concept Inventory:

• Latency & throughput

• Pipelined circuits & conventions
• Pipeline diagrams
• Pipelining methodology: contours
• Pipelined components; interleaving

Notes:

Latency: the delay from when an input is established Pipelining methodology:

until the output associated with the input becomes • Form 1-pipeline by adding registers to all
valid. outputs
• Combinational circuits: L = tPD • To add a pipeline stage, draw contour across
• K-pipeline: L = K*tCLK all paths from inputs to outputs such that it
doesn’t cross other contours and all input-
Throughput: the rate at which inputs or outputs are output paths cross the contour in the same
processed. direction. This ensures the pipeline is well-
• Combinational circuits: T = 1/L formed (same # of registers on all input-
• K-pipeline: T = 1/tCLK output paths). A K-pipeline has K registers
on all input-output paths.
• Contours must take into account pipelined
or interleaved components. An N-way
interleaved component behaves like N-
pipeline.

Unpipelined:
L = 45ns, T = 1/L = 1/(45ns)
2-stage pipeline [tCLK=25ns]:
L = 2*25 = 50 ns, T = 1/(25ns)

6.004 Worksheet - 1 of 8 - Pipelined Circuits

Problem 1.

A simple combinational circuit is to be pipelined for maximum throughput using a minimal

number of registers. For each of the questions below, please create a valid K-stage pipeline.
Show your pipelining contours and place large black circles (●) on the signal arrows to indicate
the placement of ideal pipeline registers (tPD=0, tSETUP=0). Give the latency and throughput
for each design. Remember that our convention is to place a pipeline register on each output.

(A) (1 point). Show the maximum-throughput 1-stage

pipeline.

Latency (ns): __________

Throughput (ns-1): __________



(B) (2 points). Show the maximum-throughput 2-stage
pipeline using a minimal number of registers.

Latency (ns): __________

Throughput (ns-1): __________

(C) (2 points). Show the maximum-throughput 3-stage

pipeline using a minimal number of registers.

Latency (ns): __________

Throughput (ns-1): __________

(D) (2 points). Show the maximum-throughput 4-stage

pipeline using a minimal number of registers.

Latency (ns): __________

Throughput (ns-1): __________

6.004 Worksheet - 2 of 8 - Pipelined Circuits

Problem 2.

The following 1-stage pipelined circuit computes Z from the four inputs A, B, C, and D. Each
component is annotated with its propagation delay in ns.

(A) Please pipeline the circuit above for maximum throughput with the minimum possible
latency using ideal pipeline registers (tPD = 0, tSETUP = 0). Show the location of pipeline
registers in the diagram above using filled-in circles, like the one shown on the Z output.
Please give the latency and throughput of the resulting pipelined circuit.

Latency (ns)? __________

Throughput (1/ns)? __________

(B) Now suppose the “3” component is replaced by a two-way interleaved component with a
minimum tCLK of 1.5ns. Recall that a two-way interleaved component behaves like a 2-stage
pipelined component. Again, please pipeline the circuit below for maximum throughput
with the minimum possible latency using ideal pipeline registers. Show the location of
pipeline registers in the diagram below using filled-in circles, like the one shown on the Z
output. Please give the latency and throughput of the resulting pipelined circuit.

Latency (ns)? __________

Throughput (1/ns)? __________

6.004 Worksheet - 3 of 8 - Pipelined Circuits

Problem 3.

An unidentified government agency has a design for a combinational device depicted below:

A B C
X
20ns 20ns 30ns

D E F
20ns 20ns 30ns

G H J Z
Y 60ns 30ns 30ns

Although you don’t know the function of each of the component modules, they are each
combinational and marked with their respective propagation delays. You have been hired to
analyze and improve the performance of this device.

(A) (1 Point) What are the throughput and latency for the unpipelined combinational device?

Latency: ________ns; Throughput: ____________ ns-1

(B) (4 Points) Show how to pipeline the above circuit for maximum throughput, by marking
locations in the diagram where registers are to be inserted. Use a minimum number of
registers, but be sure to include one on the output. Assume that the registers have 0 tPD
and tSETUP.

(mark register locations in diagram above)

(C) (1 Point) What are the latency and throughput of your pipelined circuit?

Latency: ________ns; Throughput: ____________ ns-1

6.004 Worksheet - 4 of 8 - Pipelined Circuits

Problem 4.

The following circuit uses six full adder modules (as you’ve seen in lecture and lab) arranged in a
combinational circuit that computes a 3-bit value F=A+B+5 for 3-bit inputs A and B:

A2 B2 A1 B1 A0 B0

FA FA FA 0

1 0 1

FA FA FA 0

F2 F1 F0

The full adders have a tPD of 6ns.

(A) Give the latency and throughput of the combinational circuit.

Latency: _______ns; Throughput: __________

(B) Indicate, on the above diagram, appropriate locations to place ideal (zero-delay) registers to
pipeline the circuit for maximum throughput using a minimum number of registers. Be sure
to include a register on each output.
(mark circuit above)

(C) Give the latency and throughput of your pipelined circuit.

Latency: _______ns; Throughput: __________

6.004 Worksheet - 5 of 8 - Pipelined Circuits

Problem 5.

(A) You are provided with the circuit shown below. Each box represents some combinational
logic. The number in each box is the tPD of that combinational logic. The circuit has two
inputs, X and Y, and one output Out. Pay close attention to the direction of the arrows
especially the arrows shown in bold. What is the latency and throughput of this
combinational circuit?

Latency (ns): ________________

Throughput (1/ns): ________________

(B) Draw contours through the circuit above to produce a valid pipelined circuit whose tCLK =
9ns with minimum latency. Extra copies of the diagram are included below. Please use a
large dot to indicate the location of each pipeline register. Assume that you have ideal
pipeline registers (tPD=tCD=tSetup=tHold=0 ns). Pay close attention to the direction of each
arrow to ensure that you produce a valid pipeline. What is the latency and throughput of this
pipelined circuit?
Latency (ns): ________________

Throughput (1/ns): ________________

6.004 Worksheet - 6 of 8 - Pipelined Circuits

(C) You are now asked to consider the performance of this circuit using different clock periods
while achieving the minimum latency. For each suggested tCLK, specify whether or not you
can create a valid pipelined circuit using that clock period. If you can, then provide the
latency and throughput of the resulting circuit and specify the number of registers at each
input. If it results in an invalid pipeline, enter NA for the rest of the row.

Extra copies of the circuit diagram are provided below.

Pipeline Pipeline
Throughput
tCLK Valid/Invalid Latency (ns) registers at registers at
(1/ns)
input X input Y
6 ns
7 ns

Problem 6.

A complex combinational circuit is constructed entirely from 2-input NAND gates having a
propagation delay of 1 ns. If this circuit is pipelined for maximal throughput by adding (non-
ideal) registers whose setup time and propagation delay are each 1 ns, what is the throughput of
the resulting pipeline? Enter a number, a formula, or “CAN’T TELL”.

Throughput (ns-1): ________________

6.004 Worksheet - 7 of 8 - Pipelined Circuits

Problem 7.

The following combinational circuit computes F(X,Y) and G(X,Y) from inputs X and Y. The tPD
(in ns) of each individual component is shown inside its box.

(A) Using ideal zero-delay registers, mark the location of the minimal number of registers
necessary to achieve maximum throughput. Give the latency and throughput of your
pipelined circuit.
mark diagram above

Latency: __________ (ns); Throughput: _________ (1/ns)

Rummaging through the stockroom you find a pipelined component with two pipeline stages that
can replace the “7” module. The minimum tCLK for the new component is 4ns. The updated
circuit is shown below.

(B) Using ideal zero-delay registers, mark the location of the minimal number of registers
necessary to achieve maximum throughput. Give the latency and throughput of your
pipelined circuit.
mark diagram above

Latency: __________ (ns); Throughput: _________ (1/ns)

6.004 Worksheet - 8 of 8 - Pipelined Circuits