LAB REPORT

PRACTICE 5: FINITE STATE MACHINE

ALUMNOS: Diego Ortega Sanz, Ángel Salas Navarro y Guillermo de la Obra Pérez

SUBJECT: Electrónica Digital y de Microprocesadores

PROFFESOR: Víctor Manuel Padrón Nápoles

7 DE NOVIEMBRE DE 2017
UNIVERSIDAD EUROPEA DE MADRID
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NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ

INDEX
INTRODUCTION ............................................................................................................................. 2
FINITE STATE MSACHINES (FSM) ............................................................................................... 2
Classification.......................................................................................................................... 2
Implementation..................................................................................................................... 4
DESCRIPTION AND OBJETIVES OF THE PRACTISE ...................................................................... 5
DEVELOPMENT OF THE PRACTISE ................................................................................................. 6
BOARD ALTERA PREPARATION .................................................................................................. 6
STEPS FOR DOING THE PRACTISE .............................................................................................. 6
CREATE A NEW PROJECT WITH QUARTUS II ......................................................................... 6
FSM CONFIGURATION ........................................................................................................... 6
VHDL CONFIGURATION ............................................................................................................. 7
BLOCK CONFIGURATION ........................................................................................................... 9
COMPILATION ......................................................................................................................... 10
SHOWING RESULT ON THE ALTERA BOARD ................................................................................ 11
REFERENCES ................................................................................................................................ 20
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INTRODUCTION
FINITE STATE MSACHINES (FSM)
A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), finite
automaton, or simply a state machine, is a mathematical model of computation. It is
an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some external inputs; the
change from one state to another is called a transition. An FSM is defined by a list of its states,
its initial state, and the conditions for each transition.

The behavior of state machines can be observed in many devices in modern society that
perform a predetermined sequence of actions depending on a sequence of events with which
they are presented. Examples are vending machines, which dispense products when the
proper combination of coins is deposited, elevators, whose sequence of stops is determined by
the floors requested by riders, traffic lights, which change sequence when cars are waiting,
and combination locks, which require the input of combination numbers in the proper order.
The largest use of finite state machines is as a mathematical model for designing digital
logic circuits and computer programs.

The finite state machine has less computational power than some other models of
computation such as the Turing machine. The computational power distinction means there
are computational tasks that a Turing machine can do but a FSM cannot. This is because a
FSM's memory is limited by the number of states it has. FSMs are studied in the more general
field of automata theory.

Classification
Finite state machines can be subdivided into transducers, acceptors, classifiers and
sequencers.

Acceptors and recognizers

Fig. 4 Acceptor FSM: parsing the string "nice"

Acceptors, also called recognizers and sequence detectors, produce binary output, indicating
whether or not the received input is accepted. Each state of an FSM is either "accepting" or
"not accepting". Once all input has been received, if the current state is an accepting state, the
input is accepted; otherwise it is rejected. As a rule, input is a sequence of
symbols (characters); actions are not used.

A (possibly infinite) set of symbol sequences, aka. formal language, is called a regular
language if there is some Finite State Machine that accepts exactly that set. For example, the
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set of binary strings with an even number of zeroes is a regular language .A machine could also
be described as defining a language, that would contain every string accepted by the machine
but none of the rejected ones; that language is "accepted" by the machine. By definition, the
languages accepted by FSMs are the regular languages—; a language is regular if there is some
FSM that accepts it.

The problem of determining the language accepted by a given finite state acceptor is an
instance of the algebraic path problem—itself a generalization of the shortest path problem to
graphs with edges weighted by the elements of an (arbitrary) semiring.

The start state can also be an accepting state, in which case the automaton accepts the empty
string.

Fig. 5: Representation of a finite-state machine;

Classifiers
A classifier is a generalization of a finite state machine that, similar to an acceptor, produces a
single output on termination but has more than two terminal states.[citation needed]

Transducers[edit]

Fig. 6 Transducer FSM: Moore model example

Transducers
Transducers generate output based on a given input and/or a state using actions. They are
used for control applications and in the field of computational linguistics.
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In control applications, two types are distinguished:

Moore machine
The FSM uses only entry actions, i.e., output depends only on the state. The advantage of the
Moore model is a simplification of the behaviour. Consider an elevator door. The state
machine recognizes two commands: "command_open" and "command_close", which trigger
state changes. The entry action (E:) in state "Opening" starts a motor opening the door, the
entry action in state "Closing" starts a motor in the other direction closing the door. States
"Opened" and "Closed" stop the motor when fully opened or closed. They signal to the outside
world (e.g., to other state machines) the situation: "door is open" or "door is closed".

Fig. 7 Transducer FSM: Mealy model example

Mealy machine
The FSM also uses input actions, i.e., output depends on input and state. The use of a Mealy
FSM leads often to a reduction of the number of states. The example in figure 7 shows a Mealy
FSM implementing the same behaviour as in the Moore example (the behaviour depends on
the implemented FSM execution model and will work, e.g., for virtual FSM but not for event-
driven FSM). There are two input actions (I:): "start motor to close the door if command_close
arrives" and "start motor in the other direction to open the door if command_open arrives".
The "opening" and "closing" intermediate states are not shown.

Implementation
Hardware applications
In a digital circuit, an FSM may be built using a programmable logic device, a programmable
logic controller, logic gates and flip flops or relays. More specifically, a hardware
implementation requires a register to store state variables, a block of combinational logic that
determines the state transition, and a second block of combinational logic that determines the
output of an FSM. One of the classic hardware implementations is the Richards controller.

In a Medvedev machine, the output is directly connected to the state flip-flops minimizing the
time delay between flip-flops and output. Through state encoding for low power state
machines may be optimized to minimize power consumption.

Software applications
The following concepts are commonly used to build software applications with finite state
machines:

 Automata-based programming
 Event-driven finite-state machine
 Virtual finite-state machine
 State design pattern
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Finite state machines and compilers

Finite automata are often used in the frontend of programming language compilers. Such a
frontend may comprise several finite state machines that implement a lexical analyzer and a
parser. Starting from a sequence of characters, the lexical analyzer builds a sequence of
language tokens (such as reserved words, literals, and identifiers) from which the parser builds
a syntax tree. The lexical analyzer and the parser handle the regular and context-free parts of
the programming language's grammar.

DESCRIPTION AND OBJETIVES OF THE PRACTISE

 Learn how to work in Quartus II, the EDA tool from ALTERA.
 Learn how to design basic finite state machines (FSM).

Design and implement a finite state machine (FSM) for the automatic control of a garage door.
Check its operation using switches and LEDs on the DE2 Board.

The inputs and outputs of the FSM are:

 BIR or infrared barrier. Detects if there is a car or person under the door, emitting a
"1".
 Key. Emits a "1" when the garage key is activated.
 Control. Emits a "1" when a signal from the remote control is received activating the
door.
 PArriba. Signal that indicates with a "1" that the door has reached the upper limit
switch, indicating that the door is fully up.
 PAbajo. Signal that indicates with a "1" the door has reached the lower limit switch,
indicating that the door is completely closed.
 TON. Signal that indicates with a "1" that door opening time has elapsed.
 SubeMot. Active in "1". When this output is activated motor rotates to open the
garage door.
 BajaMot. Active in "1". When this output is activated motor rotates to close the garage
door.
 Clock and the reset signal active "0", which initializes the MEF.

The FSM has four States:

1. Abajo (Down). The door is closed. Activation from the remote control or the makes
FDM transit to Subiendo (Rising) state.
2. Subiendo (Going up). The door is opening. The FSM transits to Arriba (Up) state, when
signal PArriba is activated indicating that door is completely opened.
3. Arriba (Up). The door stays open until opening time elapses and then transits to
Bajando (Going down) state.
4. Bajando (Going down). The door is closing. The FSM transits to Abajo (Down), when
signal PAbajo is activated indicating that door is completely closed.
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NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ

DEVELOPMENT OF THE PRACTISE

BOARD ALTERA PREPARATION
We will use the next board in order to realise the practise asked. We should connect to the
current and put the USB port in “blaster”.

STEPS FOR DOING THE PRACTISE

CREATE A NEW PROJECT WITH QUARTUS II
We must follow the next septs:

To run a New Project Wizard

 Specify project directory, name, and top-level entity.

 Specify project design files.
 Specify Altera device family for the design.
 Specify device (or specify device information for automatic device selection).
EP3C16F484C6.
 Specify other EDA tools to be used for this project.
 Review project settings.

FSM CONFIGURATION
Once we have this, click on new and select “state machine file”
For logical expressions, we use this equivalencies:

Bool VHDL Verilog

  AND  &
  OR  | (ALT GR  1)
X  NOT ( X )  ( x  0)
X  NOT ( X ) ~ x (ALT GR  4)
X  X  ( x  1)
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Now, we proceed to configure our machine

VHDL CONFIGURATION
Once the design is finished, proceed to generate VHDL code by clicking on this icon

When we do it, the code generated is this:

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 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ

BLOCK CONFIGURATION
Create a new schematic to connect the FSM to switches and LEDS on the board and
check its operation. Click on File - > New... and select the type of file that is shown in
the following figure.

Select Symbol Tool (Figure 6) and connect the FSM, as shown in Figure 7, use the

Pin Tool tools to define the inputs and outputs. Connect components using the

Orthogonal Node Tool .

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Finally, we Import the file DE2_pin_assignments.csv file (download it from

campusvirtual, if you don’t have it) to define the connections on DE2 Board. To do this
click on Assignments -> Import Assignments...

COMPILATION
Now we proceed to compile the design by clicking on the icon Start Compilation .
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SHOWING RESULT ON THE ALTERA BOARD

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 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ
 GRADO EN INGENIERÍA ELECTRÓNICA
INDUSTRIAL Y AUTOMÁTICA

ASIGNATURA: ELECTRÓNICA DIGITAL Y MICROPROCESADORES

NOMBRE: DIEGO APELLIDOS: ORTEGA SANZ

REFERENCES
https://en.wikipedia.org/wiki/Finite-state_machine