Page | 2

Syllabus content & assessment at a glance

Sections Topics
Section 1 Theory of Computer Science
1.1 Data representation
1.1.1 Binary systems
1.1.2 Hexadecimal
1.1.3 Data storage
1.2 Communication and Internet technologies
1.2.1 Data transmission
1.2.2 Security aspects
1.2.3 Internet principles of operation
1.3 Hardware and software
1.3.1 Logic gates
1.3.2Computer architecture and the fetch-execute cycle
1.3.3 Input devices
1.3.4 Output devices
1.3.5 Memory, storage devices and media
1.3.6 Operating systems
1.3.7High- and low-level languages and their translators
1.4 Security
1.5 Ethics
Section 2 Practical Problem-solving and Programming
2.1 Algorithm design and problem-solving
2.1.1 Problem-solving and design
2.1.2 Pseudocode and flowcharts
2.2 Programming
2.2.1 Programming concepts
2.2.2 Data structures; arrays
2.3 Databases

Assessment at a glance
Components Weighting
Paper 1 Theory 1 hour 45 minutes 60%
This written paper contains short-answer and structured questions. All
questions are compulsory.
No calculators are permitted in this paper. 75 marks
Externally assessed.
Paper 2 Problem-solving and Programming 1 hour 45 minutes 40%
This written paper contains short-answer and structured questions. All
questions are compulsory. 20 of the marks for this paper are from questions
set on the pre-release material. 1
No calculators are permitted in this paper. 50 marks
Externally assessed.
Page | 3
About the developer of this workbook

Inqilab Patel is an O &A Level Computer Teacher. He has taught in many schools
including Yaqeen Model School, Karachi Cadet School, KN Academy, Beacon House
and The City School, PAF Chapter, Nakhlah Boys Campus Society and Hexis A
Level. Cambridge has selected him as a Member of Cambridge Editorial Review
Board. He is also associated with Aga Khan University Examination Board in the
capacity of Chief Examiner, Item Writer, E-Marker, Karachi Board of Secondary
Education the capacity of Deputy Head Examiner and Sindh Board of Technical
Education.

His entire career path revolves around computer science; either he was a student or a
teacher. He got a chance to polish his skills of teaching and studying more about
computers at various levels which has given him great confidence in presenting
himself for any senior level position of transferring his knowledge to the youth.

He has not stopped, he is continuing with his education at the higher levels. It is his
second semester of MPhil computer studies from a well-known university of Pakistan;
The Institute of Business & Technology.

Inqilab Patel knows a lot of methods of teaching computers and has developed tutorial
notes, worksheets and assignments for my students. He also maintains a website
(www.ruknuddin.com) which is specifically designed for the support of those who want
to excel in GCSE computer science. He also regularly contributes material to CIE
teacher support website, for which he receives appreciation from different people
across the world.

He has also received various training in innovative and special methods of teaching
this subject.
Page | 4

Disclaimer
This workbook is developed by combining different materials related to Cambridge
IGCSE & O Level Computer Science 0478 & 2210. It is combination of work
developed by me and the resources, which are available in different web sites, books,
magazines, past papers and guides, just to facilitate students and teachers in
preparation for examinations.

Examination questions and marking schemes used in this workbook are taken from
CIE (Cambridge International Examinations)

Note

Study of at least one of the following books, is compulsory for solving this workbook.
Page | 5

Paper 1
Theory of Computer Science
Page | 6

Chapter 4

Computer Architecture
1.3.2 Computer architecture and the fetch-execute cycle

Have Revised
Have Read
To Revise

Learning Outcome
Prepared
To Read

1.3.2: Computer architecture and the fetch-execute cycle

Show understanding of the basic Von Neumann model for a
computer system and the stored program concept (program
instructions and data are stored in main memory and instructions are
fetched and executed one after another)
Describe the stages of the fetch-execute cycle
Page | 7

Courtesy to http://web.eecs.utk.edu/research/cs100modules/module1/index.html
http://inqilabpatel.com/fetchexecute.html

Von Neumann Architecture

The idea about how computers should be built was proposed by John von Neumann in
1945.
Von Neumann gave an idea how to build computer. This idea is also called the von
Neumann Architecture or Model.
A computer should have input/output devices, Arithmetic Logic
Unit (ALU), Control Unit (CU) and computer memory (storage
device).
Firstly programs should be stored in computer‟s memory
(storage devices).
From storage devices programs should be loaded into CPU
(ALU & CU) for execution.
This is still the basis for computers today.
Examiner Comments on Question to explain Stored
Program Concept
This question appeared to be very challenging for candidates. Many candidates described
the fetch execute cycle. It would be helpful if candidates understood that the stored program
concept is a specific infrastructure for the central processing unit and not the fetch execute
cycle. It would be encouraging to see candidates demonstrate a more confident level of
knowledge of the stored program concept.

Input/output (I/O) Devices

The Input/output (I/O) components of a computer are hardware devices that are responsible
for getting data from the computer to the user or from the user to the computer.
Page | 8
Data going from the user to the computer is called "input." The two main input devices are
the mouse and the keyboard.
Output devices are used to transmit data from the computer's memory to the user. The two
output devices almost every computer system has are the monitor and the printer.
Memory Unit
Computer has several types of memory. Memory unit in the Von Neumann model is the
main memory, also called RAM or Random Access Memory.
Main memory is used by the computer for storing a program and its data while the program
is running. What distinguishes a computer from a calculator is the ability to run a stored
program; main memory allows the computer to do that.
RAM can be thought of as a sequence of boxes, called cells, each of which can hold a
certain amount of data.
The remaining three components of the von Neumann model of a computer are found
inside the Processor.
Control Unit
The control unit controls the sequencing and timing of all operations. It contains a "clock,"
that is actually a quartz crystal that vibrates million times per second. The clock emits an
electronic signal for each vibration. Each separate operation is synchronized to the clock
signal. For example 1st pc operates at 4.7 MHz means 4.7
million instructions per second.
The functions of CU are given below:
 Interprets and carries out instruction of program.
 Selects program statements from memory.
 Moves these instructions to instruction registers
 Carries out instructions
 Directs flow of data between components of
CPU and to and from other devices.
Arithmetic & Logic Unit (ALU)
Arithmetic unit perform arithmetical operations like +, -, *,
and / while logical unit are to compare two quantities.
Logical operations are important in computer programming.
ALU can be thought of as being similar to a calculator, except that, in addition to normal
math, it can also do logical (true/false) operations.
The functions of ALU are given below:
Page | 9
 The arithmetic unit carries out arithmetic like addition, division.
 The logic unit enables the processor to make comparison like =, <, > and logical
decisions like AND, OR, NOT.
 The arithmetic logic unit carries out communication with peripheral devices.
 It also carries out bit shifting operation.
Register:
Registers are Immediate Access Store (IAS) located on the CPU, and used temporarily for
storing data. Because the registers are close to the ALU, they are made out of fast memory,
efficiently speeding up calculations.
There are 14 registers. Some examples are

a) Program Counter (PC) - an incrementing counter that keeps track of the next memory
address of the instruction that is to be executed once the execution of the current
instruction is completed.
b) Memory Address Register (MAR) - the address in main memory that is currently being
read or written
c) Memory Buffer/Data Register (MBR/MBR) - a two-way register that holds data fetched
from memory (and ready for the CPU to process) or data waiting to be stored in memory
d) Current Instruction register (CIR) - a temporary holding ground for the instruction that
has just been fetched from memory
e) Accumulator Register (ACC)is used for storing data for ALU to process and the results
those are produced by the ALU.

Buses: ''The set of wires used to travel signals to and from CPU and different components
of computer is called Bus.''
Bus is a group of parallel wires that is used as a communication path. As a wire
transmits a single bit so 8-bits bus can transfer 8 bits (1 byte) at a time and 16-bits bus can
transfer 16 bits (2 bytes) and so on. There are three types of buses according to three types
of signals, these are:
a) Data Bus: ''The buses which are used to transmit data between CPU, memory and
peripherals are called Data Bus.''
b) Address Bus: ''The buses which are connecting the CPU with main memory and used
to identify particular locations (address) in main memory where data is stored are called
Address Buses.''
Page | 10
c) Control Bus: The wires which are used to transmit the control signals (instructions)
generated by Control Unit to the relevant component of the computer.
Example Question
Q 4.1)(a) One of the key features of von Neumann computer architecture is the use of
buses.

This bus carries signals used to

Address bus coordinate the computer‟s activities

Control bus This bi-directional bus is used to

exchange data between processor,
memory and input/ output devices
Data bus
This uni-directional bus carries signals
relating to memory addresses between
processor and memory
Three buses and three descriptions are shown below.
Draw a line to connect each bus to its correct description.
Q 4.2)

The diagram above shows a simplified form of processor architecture.

Name the three buses labelled A, B and C.
A ...............................................................................................................................................
B ...............................................................................................................................................
C ............................................................................................................................................... [3]
Page | 11
Fetch-Execute Cycle:
At its core, all the computer ever does is, execute one instruction in memory after another,
over and over. Although there are many different possible (assembly language) instructions
that the computer can execute, the basic steps involved in executing an instruction are
always the same, and they are called the instruction cycle.
1. Fetch the instruction (transfer the instruction from main memory to the decoder)
2. Decode the instruction (from machine language)
3. Execute the instruction (e.g., add, divide, load, store...)
4.Store the result (for instructions like ADD, place the 'answer' in the specified register.)
The control unit guides the computer's components through this cycle to execute one
instruction.

When that instruction is done, the cycle starts all over again with the next instruction.
Registers/circuits involved

The circuits used in the CPU during the cycle are:

 Program Counter (PC) - an incrementing counter that keeps track of the next
memory address of the instruction that is to be executed once the execution of the
current instruction is completed.
 Memory Address Register (MAR) - the address in main memory that is currently
being read or written
 Memory Buffer Register (MBR) - a two-way register that holds data fetched from
memory (and ready for the CPU to process) or data waiting to be stored in memory
 Current Instruction register (CIR) - a temporary holding ground for the instruction
that has just been fetched from memory
Page | 12
 Accumulator Register (ACC)is used for storing data for ALU to process and the
results those are produced by the ALU.
 Control Unit (CU) - decodes the program instruction in the CIR, selecting machine
resources such as a data source register and a particular arithmetic operation, and
coordinates activation of those resources
 Arithmetic logic unit (ALU) - performs mathematical and logical operations

Q 4.3 (a) Explain how the width of the data bus and system clock speed affect the
performance of a computer system.
Width of the data bus
........................................................................................................................
Clock speed
............................................................................................................................[3]
(b) The table shows six stages in the von Neumann fetch-execute cycle.
Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand
column. [6]
Sequence
Description of stage
number
the instruction is copied from the Memory Data Register (MDR) and placed
in the Current Instruction Register (CIR)
the instruction is executed
the instruction is decoded
the address contained in the Program Counter (PC) is copied to the
Memory Address Register (MAR)
the value in the Program Counter (PC) is incremented so that it points to
the next instruction to be fetched
the instruction is copied from the memory location contained in the Memory
Address Register (MAR) and is placed in the Memory Data Register (MDR)

Marking Scheme
Width of the data bus
 the width of the data bus determines the number of bits that can be simultaneously
transferred
 increasing the width of the data bus increases the number of bits/amount of data that
can be moved at one time (or equivalent)
Page | 13
 hence improving processing speed as fewer transfers are needed
 By example: e.g. double the width of the data bus moves 2x data per clock pulse
Clock speed
 determines the number of cycles the CPU can execute per second
 increasing clock speed increases the number of operations/number of fetch-execute
cycles that can be carried out per unit of time
 however, there is a limit on clock speed because the heat generated by higher clock
speeds cannot be removed fast enough
Register notation
To describe the cycle we can use register notation. This is a very simple way of noting all
the steps involved. In all cases brackets e.g. [PC], means that the contents of the thing
inside the brackets are loaded. In the case of the first line, the contents of the program
counter are loaded into the Memory Address Register.

MAR  [PC]
MBR  [Memory] ; PC [PC] +1 (Increment the PC for next cycle at the same time)
CIR  [MBR]
CIR sends instruction to Decoder of control unit
Decoder decodes
Or ACC [MBR]
ACC sends data to ALU
ALU executes
Detailed description of Fetch-Decode-Execute Cycle
To better understand what is going on at each stage we'll now look at a detailed description:

The contents of the Program Counter, the address of the next instruction to be executed, is
placed into the Memory Address Register
Page | 14

The address is sent from the MAR along the address bus to the Main Memory. The
instruction at that address is found and returned along the data bus to the Memory Buffer
Register. At the same time the contents of the Program Counter is increased by 1, to
reference the next instruction to be executed.

The MBR loads the Current Instruction Register with the instruction to be decoded by
decoder of control unit or the MBR loads Accumulator with the data to be executed.

The instruction is decoded and executed using the ALU if necessary.

The Cycle starts again!
Q 4.4) Complete the following diagrams showing each step of the fetch decode execute
cycle:
Page | 15

Practice Questions
Q 4.5) Describe what differs a computer with a calculator
.... .............. ................................................................................................................
.................................. ............................................................................................ [1]
Q 4.6) Differentiate an ALU with a calculator.
.... .............. ................................................................................................................
.................................. ............................................................................................ [1]

Q 4.7) Von Neumann gave the idea how computer should be built.
a) Describe the purpose of each of the following parts of a processor:
(i) Control unit
.... .............. ................................................................................................................
.................................. ............................................................................................ [1]

(ii) Arithmetic & Logic unit

.... .............. ................................................................................................................
.................................. ............................................................................................ [1]
Page | 16

(iii) Register
.... .............. ................................................................................................................
.................................. ............................................................................................ [1]

b) Draw and label the diagram of von Neumann architecture.

Q 4.8) Draw the diagram and describe the stages of fetch-execute cycle.

Description of fetch-execute cycle:

…………………….....................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
................................................................................................................... [6]
Q 4.9) Jo buys a notebook computer which has a 3MHz quad-core central processing unit
(CPU).
Page | 17

(a) State the purpose of the CPU.

.... .............. ................................................................................................................
.................................. ............................................................................................ [1]
(b) Describe what is meant by
3MHz CPU
.......................................................................................................................................
................................................................................................................................ [2]
quad-core CPU
.......................................................................................................................................
.......................................................................................................................................
................................................................................................................................. [2]
Q 4.10) The sequence of operations shows, in register transfer notation, the fetch stage of
the fetch-execute cycle.
1 MAR[PC]
2 PC [PC] + 1
3 MDR [[MAR]]
4 CIR [MDR]
• [register] denotes contents of the specified register or memory location
• step 1 above is read as “the contents of the Program Counter are copied to the Memory
Address Register”
(i) Describe what is happening at step 2.
....................................................................................................................................
……………………….................................................................................................. [1]
(ii) Describe what is happening at step 3.
......................................................................................................................................
......................................................................................................................................
………………………………………............................................................................ [1]
(iii) Describe what is happening at step 4.
.....................................................................................................................................
……………………….............................................................................................. [1]
Page | 18
Q 4.11) (a) Describe basic Von Neumann processor architecture. [3]
....................................................................................................................................
………………………..................................................................................................
....................................................................................................................................
……………………….................................................................................................. [1]
(b) At a particular point in a program, the program counter (PC) contains the value 200.
(i) State the expected value contained in the PC after the instruction held at location 200has
been fetched
.....................................................................................................................................
Explain your answer.
.....................................................................................................................................
……………………….............................................................................................. [1]
After the instruction is processed, the value in the PC is 180.
Explain why the value has changed to 180
.....................................................................................................................................
……………………….............................................................................................. [1]
Q 4.12) The sequence of operations below shows the fetch stage of the fetch-execute cycle
in register transfer notation.
1. MAR ← [PC]
2. PC ← [PC] + 1
3.MDR ← [[MAR]]
4. CIR ← [MDR]
Note:
• [register] denotes the contents of the specified register
• Step 1 above is read as „The contents of the Program Counter are copied to the
Memory Address Register‟.
(i) Explain what is happening at step 4. [1]
.....................................................................................................................................
……………………….............................................................................................. [1]

(ii) Explain what is happening at step 3. [1]

.....................................................................................................................................
……………………….............................................................................................. [1]
Page | 19
Q 4.13) One of the buses found in a typical microprocessor architecture is the control bus.
Describe its purpose.
.....................................................................................................................................
……………………….............................................................................................. [1]
Q 4.14) (i) One of the buses found in a typical microprocessor architecture is the control
bus. Describe its purpose.
.....................................................................................................................................
………………………......................................................................................................
Give one example of a control signal used.
.............................................................................................................[2]
(ii) Name and describe two other buses used in a typical microprocessor architecture.
1 .....................................................................................................................................
2 .................................................................................................................................[4]
Q 4.15) The steps in the fetch stage of the fetch-execute cycle are shown in the first
column using register transfer notation.
(i) Describe what happens at each stage of the fetch cycle. [4]
Register transfer
Description
notation
..............................................................................
MAR [PC]
..............................................................................
..............................................................................
PC [PC] + 1
.............................................................................
..............................................................................
MDR [[MAR]]
.............................................................................
..............................................................................
CIR [MDR]
..............................................................................
Page | 20
(ii) The contents of some special-purpose registers change as the program is executed.
Complete the trace table for the fetching of the first program instruction (867A):
• Show how the contents of the registers change.
• Put a tick in the address bus and/or data bus column to show when there is a signal
change on each bus.[5]
Special purpose registers
Buses
(Contents shown in hex)
Fetch stage
Address Data
PC MAR MDR CIR
bus bus
58
MAR  [PC]
PC  [PC] + 1
MDR [[MAR]]
CIR  [MDR]
Q 4.16) The trace table below is used to show how the contents of the special-purpose
registers change as the program is executed.
The steps in the fetch stage of the fetch-execute cycle are shown in the first column using
register transfer notation. Complete the trace table for the fetching of the first program
instruction (2150):
• Show the changing contents of the registers
• Put a tick in the Address bus/Data bus column to show when the signals on
that bus change. [5]
Special purpose registers
Buses
(Contents shown in hex)
Fetch-execute stage
Address Data
PC MAR MDR CIR
bus bus
7A
MAR  [PC]
PC  [PC] + 1
MDR [[MAR]]
CIR  [MDR]
Page | 21
(b) The following table is to show the steps in the fetch stage of the fetch-execute cycle.
Complete the table. [4]
Fetch-execute stage Description
The contents of the Program Counter are copied to the Memory
...............................
Address Register.
...........................................................................................
PC [PC] + 1
……...................................................................................
The Memory Address Register contains an address. Copy the
...............................
contents of this address to the Memory Data Register.
...........................................................................................
CIR [MDR]
...........................................................................................

Q 4.17) The following text includes a description of four stages of the fetch-execute cycle.
Use the terms below to complete the text:
Memory Data Register (MDR), Memory Address Register (MAR), Program Counter
(PC), Current Instruction Register(CIR), address, data bus, main memory,
address bus.
The program instructions are stored in a continuous block of .................. .
The Program Counter stores the ........................................ of the next instruction to be
fetched. Stage 1: The contents of the Program Counter are copied to the
........................................... .Stage 2 The contents of the .................................. are then
incremented. Stage 3 The value in the Memory Address Register is loaded to
the................................... .The data value found at this address is loaded on to
the.................................... and copied to the ........................................... .Stage 4 The
contents of the Memory Data Register are copied to the............................... and. The
instruction can now be decoded and executed. [6]
Page | 22
Topical Questions from Past Papers
Q 4.1) Summer 2015 P11
7 (a) One of the key features of von Neumann computer architecture is the use of buses.
Three buses and three descriptions are shown below.
Draw a line to connect each bus to its correct description.
This bus carries signals used to
Address bus coordinate the computer‟s activities

Control bus This bi-directional bus is used to

exchange data between processor,
memory and input/ output devices

Data bus
This uni-directional bus carries signals
relating to memory addresses between
processor and memory

(b) The seven stages in a von Neumann fetch-execute cycle are shown in the table below.
Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand
column. The first one has been done for you.

Stage Sequence
number
the instruction is then copied from the memory location contained in the
MAR (memory address register) and is placed in the MDR (memory
data register)
the instruction is finally decoded and is then executed
the PC (program counter) contains the address of the next instruction to 1
be fetched
the entire instruction is then copied from the MDR (memory data
register) and placed in the CIR (current instruction register)
the address contained in the PC (program counter) is copied to the
MAR (memory address register) via the address bus
the address part of the instruction, if any, is placed in the MAR (memory
address register)
the value in the PC (program counter) is then incremented so that it
points to the next instruction to be fetched
Page | 23
Examiner’s Comments on Question 7 (a) and (b)
Part (a) was answered very well with most candidates able to gain two marks.
In part (b) very few candidates gained full marks despite the range of responses they could have given.
Most candidates demonstrated a need to improve their knowledge of the fetch-execute cycle. Many
candidates gained just one mark for the incrementation of the program counter. Some candidates gained
three marks for identifying some correct stages.
Q 4.2) Winter 2015 P13
3 A section of computer memory is shown below:

Address Content
1000 0000 0110 1110
1000 0001 0101 0001
1000 0010 1000 1101
1000 0011 1000 1100
`

1000 1100
1000 1101
1000 1110
1000 1111

(a) (i) The contents of memory location 1000 0001 are to be read.
Show the contents of the Memory Address Register (MAR) and the Memory Data Register
(MDR) during this read operation: [2]
MAR

MDR

(ii) The value 0111 1001 is to be written into memory location 1000 1110.
Show the contents of the MAR and MDR during this write operation: [2]
MAR

MDR
Page | 24
(iii) Show any changes to the computer memory following the read and write operations in
part (a)(i) and part (a)(ii). [1]

Address Content
1000 0000 0110 1110
1000 0001 0101 0001
1000 0010 1000 1101
1000 0011 1000 1100
`

1000 1100
1000 1101
1000 1110
1000 1111
(b) Name three other registers used in computers.
1 .........................................................................................................................................
2 .........................................................................................................................................
3 ................................................................................................................................... [3]
(c) The control unit is part of a computer system.
What is the function of the control
unit?..........................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
.............................................................................................................................
....................................................................................................................................... [3]
Examiners’ Comments Question 3 (a), (b) and (c)
In part (a) some candidates were able to recognise and select the correct address and contents. Candidate need to make
sure they read the whole question before answering as some had not noted the correct memory location provided in the
question. Some candidates were able to provide the correct contents of the second set of registers, but some candidates
did not manage to recognise how a section of memory worked and could not provide a correct answer to the question.
In part (b) some candidates could provide three correct registers, but many could only provide one or two.
In part (c) many candidates demonstrated limited knowledge of the workings of the control unit. Most were vague in
their description and needed specific detail about how the unit operates.
Page | 25

Q 4.3) Winter 2015 P11

3 (b) Two features of Von Neumann architecture are the use of registers and the use of
buses. Give the names of two registers and two buses.
Registers
1: .......................................................................................................................................
.............................................................................................................................................
2: .........................................................................................................................................
............................................................................................................................................

Buses
1 ..........................................................................................................................................
..........................................................................................................................................
2: .........................................................................................................................................
........................................................................................................................................[4]
Examiners’ Comments Question 3(a) and (b)
In part (a) most candidates were able to correctly identify that cookies detect if a viewer has previously viewed a
webpage. Some candidates incorrectly thought that cookies generate website pop ups.
In part (b) many candidates were able to provide at least one correct register and one correct bus.
Page | 26

Q 4.4) Winter 2016 P12

6 Four computer terms and eight descriptions are shown below.
Draw lines to connect each computer term to the correct description(s). [4]

Computer term Description

Arithmetic and logic Data can be read but not altered
unit (ALU)

Carries out operations such as addition

and multiplication
Control unit
Stores bootstrap loader and BIOS

Fetches each instruction in turn

Random access
memory (RAM)
Carries out operations such as AND, OR,
NOT

Stores part of the operating system

currently in use

Read only memory Stores data currently in use

(ROM)

Manages execution of each instruction

Examiner Report
The full range of marks was seen from candidates in this question on terms and descriptions. Some
candidates only connected a single line from each computer term. The question stated to draw lines,
candidates should note this type of question means that there may be more than one line that can be drawn to
connect terms to description. If a question states to draw a line, this is when only a single line should be drawn
from each term to a description.
Page | 27

Q 4.5) Winter 2016 P11 & 13

1 To process an instruction, a central processing unit (CPU) goes through a cycle that has
three main stages.
Name each stage in this cycle.
Stage 1 ................................................................................
Stage 2 ................................................................................
Stage 3 ................................................................................ [3]
Examiner Report Question 1
Some candidates could correctly identify the three stages of processing an instruction, some managed to
identify fetch and execute, but not decode. Some could not identify any correct stages. The most common
incorrect answer given by candidates was input, process, output. This was not a specific enough answer for
candidates to gain the marks.
Q 4.6) Summer 2017 P11
6 Signals are sent to and from the components of a processor using buses.
Identify and describe the purpose of two different buses.
Bus 1 ....................................................................
Purpose ..............................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
........................................
Bus 2 ....................................................................
Purpose ...........................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
........................................ [6]

Examiner Report Question 6

Most candidates correctly identify two buses. Many candidates gained further marks by stating what the bus transported. It would have
been beneficial if candidates provided further detail about what the bus transported would be used for.
Page | 28
Q 4.7) Summer 2017 P12
1 Name three different buses that are used in the fetch-execute cycle.
Bus 1 .................................................................................................................................
Bus 2 .................................................................................................................................
Bus 3 ........................................................................................................................... [3]

Examiner Comment on Q 1
Many candidates provided three correct busses. The most common incorrect answer was candidates providing fetch, decode and
execute, which demonstrated a misunderstanding of the question.

Q 4.8) Winter 2017 P12

6 Selma writes the following four answers in her Computer Science examination.
State which computer terms she is describing.
“It is a signal. When the signal is received it tells the operating system that an event has
occurred.”
Selma is describing ..............................................................................................................
“It takes source code written in a high level language and translates it into machine code. It
translates the whole of the source code at once.”
Selma is describing ..............................................................................................................
“The part of the central processing unit (CPU) that carries out calculations.”
Selma is describing ..............................................................................................................
“When data is transmitted, if an error is detected in the data received a signal is sent to ask
for the data to be retransmitted. This continues until the data received is correct.”
Selma is describing .......................................................................................................... [4]
Page | 29

Q 4.9) Winter 2017 P13

4 Six components of a computer system and six descriptions are shown.

Draw a line to match each component with the most suitable description. [5]
Component Description
Used to connect together the
Arithmetic Logic Unit (ALU)
internal components of the CPU.

Used to carry out calculations on

Buses
data.

Used to temporarily hold data and

Control Unit (CU)
instructions during processing.

Immediate Access Store Used to allow interaction with the

(IAS) computer.

Used to hold data and

Input/Output instructions before they are
processed.

Used to manage the flow of data

Registers
through the CPU.
Page | 30

Q 4.10) March 2018 P12 (India)

10 The table shows a segment of primary memory from a Von Neumann model computer.
Address Contents
10001 11001101
10010 11110001
10011 10101111
10100 10000110
10101 00011001
10110 10101100
The program counter contains the data 10010.
(a) (i) State the data that will be placed in the memory address register (MAR).

.......................................................................................................................................[1]
(ii) State the data that will be placed in the memory data register (MDR).

.......................................................................................................................................[1]
(b) Describe the stored program concept when applied to the Von Neumann model.
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
............................................................................................................................................[4]
Comments on Question 10
(a) (i) and (ii) Most candidates provided a correct response and demonstrated an excellent
level of understanding.
(b) This question appeared to be very challenging for candidates. Many candidates
described the fetch execute cycle. It would be helpful if candidates understood that the
stored program concept is a specific infrastructure for the central processing unit and not
the fetch execute cycle. It would be encouraging to see candidates demonstrate a more
confident level of knowledge of the stored program concept.
Page | 31

Q 4.11) Summer 2018 P11

5 Six components of the Von Neumann model for a computer system and six descriptions
are given. Draw a line to match each component to the most suitable description.
Page | 32

Q 4.12) Summer 2018 P12

6 Kelvin correctly answers an examination question about the Von Neumann model.
Eight different terms have been removed from his answer.
Complete the sentences in Kelvin‟s answer, using the list given. Not all items in the list
need to be used.
• accumulator (ACC)
• address bus
• arithmetic logic unit (ALU)
• control unit (CU)
• data bus
• executed
• fetches
• immediate access store (IAS)
• memory address register (MAR)
• memory data register (MDR)
• program counter (PC)
• saved
• transmits
The central processing unit (CPU) .................................................................................... the
data and instructions needed and stores them in the
.............................................................................. to wait to be processed. The
.................................................................................... holds the address of the next
instruction. This address is sent to the ....................................................................................
The data from this address is sent to the .............................................................................. .
The instruction can then be decoded and ............................................................................. .
Any calculations that are carried out on the data are done by the
.................................................................................... . During calculations, the data is
temporarily held in a register called the ............................................................................[8]
Page | 33

Marking Schemes
Q 4.1) Summer 2015 P11

Q 4.3) Winter 2015 P11

Q 4.4) Winter 2016 P12

Q 4.2) Winter 2015 P13

Q 4.5) Winter 2016 P11 & 13

Page | 34

Q 4.6) Summer 2017 P11

Q 4.11) Summer 2018 P11

Q 4.7) Summer 2017 P12

Q 4.8) Winter 2017 P12

Q 4.9) Winter 2017 P13

Q 4.12) Summer 2018 P12

Q 4.10) March 2018 P12 (India)