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Priyanka - Junior JavaScript Developer

This document is a resume for Priyanka Kamashetty summarizing her education and experience. She has a Master's degree in Computer Engineering from Illinois Institute of Technology and a Bachelor's degree in Electronics and Communication from Vishveswariah Technological Institute in India. Her technical skills include web development languages like JavaScript, CSS, and Node.js as well as hardware design skills in Verilog, VHDL, and ASIC design. Her work experience includes positions as a Web Developer and Design Verification Engineer. She has also conducted research and academic projects in areas like digital circuit design, CPU architecture, and infrared remote control systems.

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Madhav Garikapati
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132 views

Priyanka - Junior JavaScript Developer

This document is a resume for Priyanka Kamashetty summarizing her education and experience. She has a Master's degree in Computer Engineering from Illinois Institute of Technology and a Bachelor's degree in Electronics and Communication from Vishveswariah Technological Institute in India. Her technical skills include web development languages like JavaScript, CSS, and Node.js as well as hardware design skills in Verilog, VHDL, and ASIC design. Her work experience includes positions as a Web Developer and Design Verification Engineer. She has also conducted research and academic projects in areas like digital circuit design, CPU architecture, and infrared remote control systems.

Uploaded by

Madhav Garikapati
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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PRIYANKA KAMASHETTY 21017 Green Hill Rd, Farmington Hills, MI-48335

Mobile (773)666-3467 Email: [email protected]

EDUCATION

Illinois Institute of Technology (IIT), Chicago, IL August 2014


Master of Science in Computer Engineering GPA 3.29/4.00

Vishveswariah Technological Institute (VTU), Gulbarga, India May 2012


Bachelor of engineering in Electronics and communication GPA 3.87/4.00
TECHNICAL SKILLS

• Javascript, CSS, HTML/HTML5, jQuery, Node.js, Parse, Google App Scripts, AngularJs, REACT
• RTL Coding - Verilog and VHDL
• ASIC Design Flow (Synthesis , SPICE simulation, Formal verification, Timing Analysis)
• Physical Design and Verification (Design Rule Checking (DRC), Layout versus Schematic (LVS), and Parasitic
Extraction)
• MatLab, Assembly Language Programming in Microprocessors and Microcomputers, OpenCV

WORK EXPERIENCE

Web Developer - Silveus Financial Feb 2015-May2017


• Developed and designed UI for the Silveus Financial’s nCompass app and created secure login for the clients
• Maintained already existing code and created custom CSS grid system to ensure cross compatibility
• Assisted in development of back end features in Node.js and C sharp

Design Verification Engineer - Scalable Systems Research Labs Oct 2014-Jan 2015
• Design and design verification of certain digital ASIC components and building blocks:
• MIPS64 core and uncore components
• Internal control processor network
• Design Verification Environment setup and test case creation for above building blocks.

Internet Lab Developer at IIT Online - Illinois Institute of Technology Jan 2013-Jan 2014
• Capturing high-quality video frames using "Topaz" and synchronizing them with videos using streaming tool
"Accordent"
• Responsible for developing, processing and publishing course videos for online viewing

RESEARCH WORK

Under Professor Jafar Saniie Ph.D (Digital circuits on chip design) Aug 2013-Jan 2014

• Alphanumeric detection by UAV using openCv on c++

ACADEMIC PROJECTS
RTL Level Power Optimization May 2014
• Optimization of the given circuit using splitting of the memory word and operand isolation
• Achieved the optimization using cadence
CAD Tool design for static timing analysis using TCL/TK and C Dec 2013
• Analyzed circuit slack time and implemented using C programming
• Designed and implemented a CAD tool using TCL/TK

Simulation of CPU, Cache, Bus and Memory Data path May 2013
• This project involved the implementation of CPU, Memory and cache operation for certain instructions from the
RISC architecture with specific importance provided with the timing information between the cache and
memory and the CPU execution (in VHDL)
• Designed a testbench with various instructions and debugged to get desired output.

Carry Ripple Adder Implementation using Data Driven Dynamic Logic May 2013
• Designed and implemented a 4- bit carry ripple carry adder using data driven dynamic logic (D3L) and split
path data driven logic (SPD3L) and 45nm technology node in VHDL

Design and Synthesis of multi-operand addition Nov 2012

• Designed a 4 bit 8 operand adder using structural coding in VHDL


• Implemented the adder using different topologies like carry ripple adder and carry save adder
• Synthesis of the circuit was done using synopsis design compiler and layout was done using cadence encounter

Design and simulation of 2-stage operational amplifier Dec 2012


• Designed a 2 stage CMOS operational amplifier using IBM 0.18microm process technology
• Performed simulation of the design using PSPICE

PC Browsing using Television Remote May 2012


• Developed a project which is used to control the various electronic devices and home appliances using a TV
remote which is universal
• Used Visual basics to program the micro controller and decoded the received 14 bit signal from the Infrared
Receiver ( checked the results on an oscilloscope) using Infrared remote as a transmitter

ACTIVITIES

• Part -time teaching experience for high school students in the courses of Physics and Mathematics
• Best outgoing student - Academics for 2012 from PDA, VTU
• Member of the organizing team at university fest "Nirvana 2012" as a host
• Worked as a Co-editor and author of several articles for academic magazine - "Egnite"
• Volunteer for remote connection interface

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