Declaration

This is to certify that Report entitled “ Implementation of calculator using FPGA” submitted by me
in partial fulfillment of the requirement for the award of six weeks summer training programme under
the super vision of Ms. Vemu Sulochana ,Project Engineer ,ACSD(CDAC) comprises only our
original work and due acknowledgement has been made in the text to all other material used.

Date : 28/11/2019 Submitted by:

Saurabh Kumar
 Acknowledgement

Before I get into the thick of things, I would like to add a few words of appreciation for
the people who have been a part of this project right from its inception. The writing of
this project has been one of the significant academic challenges that I have faced and
without the support, patience and guidance of the people involved, it would not have been
possible to accomplish this task. It is to them I owe our deepest gratitude.

It gives me immense pleasure in presenting the project report on

“Implementation of calculator using FPGA”.

It has been my privilege to have a project guide who has assisted me from the
commencement of the project. The success of the project is a result of sheer hard work
and determination put in by us and our Project Guide. I, hereby take this opportunity to
add a special note of thanks for Ms.Vemu Sulochana(Project Engineer) who undertook
to act as our mentor despite her many other academic commitments. Without her insight,
support and energy, this project would neither have kick-started, nor would have reached
fruitfulness.
 Abstract

This report describes the project “Implementation of calculator using FPGA”. This
calculator performs six different types of tasks namely- Addition, Subtraction, division,
multiplication, square root of a number and square of a number. This calculator is a 4 bit
calculator. A calculator consists of an input bus and an output bus. The input bus
receives all the data for the calculator, operands and operators are all input through
this one bus. The output bus transmits the result of operation.The basic idea behind the
design is to eliminate tedious computations and algebraic manipulations that
discourages many students and allow them to solve problems and appreciate the power
an value of mathematics in the world today.
 Table of Contents

S.N. Content Page

No.
1 Declaration 1

2 Acknowledgement 2

3 Abstract 3

4 Introduction 5-6

5 VLSI Design Flow 7-8

6 Design Simulation and Synthesis 8-10

7 Introduction to FPGA: Spartan 3,3E and 6 11-

14
8 4-bit Full Adder 15-
17
9 4-bit Full Substractor 18-
21
10 4-bit Booth Multiplier 22-
26
11 4-bit Restoring Divider 27-
34
12 VHDL Code 4-bit Calculator 35-
38
13 Results: Simulation 41-
42
14 Implementation using FPGA 42
15 Implementation on Spartan 3
 INTRODUCTION

VLSI is the field which involves packing more and more logic devices into smaller and
smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now
be put into a small space few millimetres across! This has opened up a big opportunity to
do things that were not possible before. VLSI circuits are everywhere ... your computer,
your car, your brand new state-of the-art digital camera, the cell-phones, and what have
you. All this involves a lot of expertise on many fronts within the same field, which we
will look at in later sections

Need, Scope and use

VHDL is a language for describing digital electronic systems. It arose out of the United
States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in
1980. VHSIC Hardware Description Language (VHDL) was developed, and
subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers
(IEEE) in the US.

Need

VHDL is designed to fill a number of needs in the design process.

1) It allows description of the structure of a design that is how it is decomposed into sub-
designs, and how those sub designs are interconnected.

2) It allows the specification of the function of designs using familiar programming

language forms.

3) As a result, it allows a design to be simulated before being manufactured, so that

designers can quickly compare alternatives and test for correctness without the delay and
expense of hardware prototyping.

1
Scope

VHDL is suited to the specification, design and description of digital electronic hardware.

System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-
software split. Simulation at this level is usually stochastic, and is concerned with
modeling performance, throughput, queuing and statistical distributions. VHDL has been
used in this area with some success, but is best suited to functional and not stochastic
simulation.

Digital

VHDL is suitable for use today in the digital hardware design process, from specification
through high-level functional simulation, manual design and logic synthesis down to
gate-level simulation. VHDL tools usually provide an integrated design environment in
this area.VHDL is not suited for specialized implementation-level design verification
tools such as analog simulation, switch level simulation and worst case timing
simulation. VHDL can be used to simulate gate level fan-out loading effects providing
coding

2
 VLSI Design Flow

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC)by

combining thousands of transistors into a single chip .The VLSI IC circuits design flow is
shown in the Fig.1. The various levels of design are numbered and the blocks show
processes in the design flow. Specifications comes first, they describe abstractly, the
functionality, interface, and the architecture of the digital IC circuit to be designed.
Behavioral description is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications. RTL description is
done using HDLs. This RTL description is simulated to test functionality. From here
onwards we need the help of EDA tools

3
Design Simulation and Design Synthesis

Synthesis

Is the process of translating a design description to another level of abstraction, i.e., from
behavior to structure. We achieved synthesis by using a Synthesis tool like Foundation
Express which outputs a net list. It is similar to the compilation of a high level
programming language like C into assembly code

4
Simulation

Simulation is the execution of a model in a software environment. During design

creation/verification, a design is captured in an RTL-level (behavioral) VHDL source
file. After capturing the design, you can perform a behavioral simulation of the VHDL
file to verify that the VHDL code is correct. The code is then synthesized into a gate-
level (structural) VHDL net list. After synthesis, you can perform an optional pre-layout
structural simulation of the design. Finally, an EDIF net list is generated for use in
Designer and a VHDL structural post-layout net list is generated for timing simulation in
a VHDL simulator.

Design Creation/Verification

VHDL Source Entry

Enter your VHDL design source using a text editor or a context-sensitive HDL editor.
Your VHDL design source can contain RTL-level constructs.

Behavioral Simulation

Perform a behavioral simulation of your design before synthesis. Behavioral simulation

verifies the functionality of your VHDL code. Typically, you use zero delays and a
standard VHDL test bench to drive simulation.

Synthesis

After you have created your behavioral VHDL design source, you must synthesize it.
Synthesis transforms the behavioral VHDL file into a gate-level netlist and optimizes the
design for a target technology.

Simulation
5
Then simulator will check functionality. It means that design and code should be working
according to truth table or not. Simulation is just testing the system at software level
where as real testing is at hardware level.

6
 Introduction to FPGA : SPARTAN 3, SPARTAN 3E, SPARTAN 6

Xilinx

Xilinx Inc. is an American technology company, primarily a supplier of programmable

logic devices. It is known for inventing the field-programmable gate array (FPGA) and as
the first semiconductor company with a fabless manufacturing model.

Founded in Silicon Valley in 1984, the company is headquartered in San Jose, USA, with
additional offices in Longmont, USA; Dublin, Ireland; Singapore; Hyderabad, India;
Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.

Major FPGA product families include Virtex (high-performance), Kintex (mid-range)

and Artix (low-cost), and the retired Spartan (low-cost) series. Major computer software
includes Xilinx ISE and Vivado Design Suite.

Spartan family

The Spartan series targets low cost, high-volume applications with a low-power footprint
e.g. displays, set-top boxes, wireless routers and other applications.

The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, dual-oxide process
technology. The Spartan-6 was marketed in 2009 as a low-cost option for automotive,
wireless communications, flat-panel display and video surveillance applications.

7
Spartan 3E FPGA Family

 Spartan-3:

Introduction The Spartan®-3 family of Field-Programmable Gate Arrays is specifically

designed to meet the needs of high volume, cost-sensitive consumer electronic
applications. The eight-member family offers densities ranging from 50,000 to 5,000,000
system gates. The Spartan-3 family builds on the success of the earlier Spartan-IIE family
by increasing the amount of logic resources, the capacity of internal RAM, the total
number of I/Os, and the overall level of performance as well as by improving clock
management functions. Numerous enhancements derive from the Virtex®-II platform
technology. These Spartan-3 FPGA enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per dollar than was previously
8
possible, setting new standards in the programmable logic industry. Because of their
exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer
electronics applications, including broadband access, home networking,
display/projection and digital television equipment. The Spartan-3 family is a superior
alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA
programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.

 Spartan-6:

General Description

The Spartan®-6 family provides leading system integration capabilities with the lowest
total cost for high-volume applications. The thirteen-member family delivers expanded
densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of
previous Spartan families, and faster, more comprehensive connectivity. Built on a
9
mature 45 nm low-power copper process technology that delivers the optimal balance of
cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-
register 6-input lookup table (LUT) logic and a rich selection of built-in system-level
blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices,
SDRAM memory controllers, enhanced mixed-mode clock management blocks,
SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI
Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device
DNA protection. These features provide a lowcost programmable alternative to custom
ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution
for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive
embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for
Targeted Design Platforms that deliver integrated software and hardware components that
enable designers to focus on innovation as soon as their development cycle begins.

10
 FULL ADDER

Full Adder is the adder which adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to
create a byte-wide adder and cascade the carry bit from one adder to the another.

Full
Adder

The output carry is designated as C-OUT and the normal output is designated as S.

Full Adder Truth Table:

Full Adder Truth Table

11
With the truth-table, the full adder logic can be implemented. You can see that the output S is an XOR
between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-OUT will only
be true if any of the two inputs out of the three are HIGH.

So, we can implement a full adder circuit with the help of two half adder circuits. At first, half adder will
be used to add A and B to produce a partial Sum and a second half adder logic can be used to add C-IN
to the Sum produced by the first half adder to get the final S output.

Full Adder Logic Circuit

If any of the half adder logic produces a carry, there will be an output carry. So, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit
shown below.

The implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol
is mostly used to represent the operation. Given below is a simpler schematic representation of a one-bit
full adder.

Full Adder Design Using Half Adders

12
With this type of symbol, we can add two bits together, taking a carry from the next lower order of
magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit
operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add
two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit
blocks.

VHDL CODE:
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bit4adder is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
u :in std_logic;
so : out STD_LOGIC_vector(7 downto 0));

end bit4adder;

architecture structural of bit4adder is

signal t1,t2,t3: std_logic;

component fulladder is
port(a,b,cin:in std_logic;
s, cout : out std_logic );
end component;

signal s:STD_LOGIC_vector(3 downto 0);

signal vo:STD_LOGIC_vector(3 downto 0);
signal v: STD_LOGIC;

begin
I1: fulladder port map (a(0),b(0),u,s(0),t1);
I2: fulladder port map (a(1),b(1),t1,s(1),t2);
I3: fulladder port map (a(2),b(2),t2,s(2),t3);
I4: fulladder port map (a(3),b(3),t3,s(3),v);

13
vo<= "000" & v;
so<= vo & s ; --output so

end structural;

14
 FULL SUBTRACTOR

Full subtractor is an electronic device or logic circuit which performs subtraction of two binary digits. It is a
combinational logic circuit used in digital electronics. Many combinational circuits are available in integrated
circuit technology namely adders, encoders, decoders and multiplexers. In this article, we are going to discuss full
subtractor construction using half subtractor and also the terms like truth table.

FULL SUBTRACTOR BLOCK DIAGRAM

FULL SUBTRACTOR USING LOGIC GATE

15
Full Subtractor Truth Table

This subtractor circuit executes a subtraction between two bits, which has 3- inputs (A, B and Bin) and
two outputs (D and Bout). Here the inputs indicate minuend, subtrahend, & previous borrow, whereas
the two outputs are denoted as borrow o/p and difference. The following image shows the truth table of
full-subtractor.

Outputs
Inputs
Subtrahend (B) Borrow (Bin)  Difference (D)
Minuend (A) Borrow (Bout)

0 0
0 0 0

0
0 1 1 1
0 1 0 1
1

16
 1
0 1 1 0

1
0 0 1 0

0
1 0 1 0

1
1 0 0 0

1 1
1 1 1

VHDL CODE:
----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity bit4subst is

Port ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);

u :in std_logic;

so : out STD_LOGIC_vector(7 downto 0));

end bit4subst;

17
architecture structural of bit4subst is

signal r,m,so12: std_logic_vector(3 downto 0);

signal so1: std_logic_vector(7 downto 0);

component bit4adder is

Port ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);

u :in std_logic;

so : out STD_LOGIC_vector(7 downto 0));

end component;

begin

m(0)<=not b(0);

m(1)<=not b(1);

m(2)<=not b(2);

m(3)<=not b(3);

r<= "0001";

so12<= so1(3) & so1(2) & so1(1) & so1(0) ;

I1: bit4adder port map (m,r,'0',so1);

I2: bit4adder port map (a,so12,u,so);

--s=difference

18
--v=carry

--v=0;negative

--v=1;positive

end structural;

BOOTH MULTIPLIER

Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement
representation in efficient way, i.e., less number of additions/subtractions required. It
operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a
string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to
2^m.
As in all multiplication schemes, booth algorithm requires examination of the multiplier
bits and shifting of the partial product. Prior to the shifting, the multiplicand may be added to
the partial product, subtracted from the partial product, or left unchanged according to following
rules:
1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1’s in the multiplier
2. The multiplicand is added to the partial product upon encountering the first 0 (provided
that there was a previous ‘1’) in a string of 0’s in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.

19
VHDL CODE:
----------------------------------------------------------------------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity booth_multiplier is

20
 Port ( x : in STD_LOGIC_vector(3 downto 0);

y : in STD_LOGIC_vector(3 downto 0);

z : out STD_LOGIC_vector(7 downto 0));

end booth_multiplier;

architecture Behavioral of booth_multiplier is

signal A,S,P: STD_LOGIC_vector(10 downto 0);

signal P1,P2,P3,P4,P5,P1_shift,P2_shift,P3_shift,P4_shift,P5_shift: STD_LOGIC_vector(10 downto 0);

signal u,v: STD_LOGIC_vector(4 downto 0);

begin

u<= '0' & x;

v<= '0' & y;

A(10 downto 6)<= u; --multiplicand(M)

A(5 downto 0)<=(others=>'0');

S(10 downto 6)<= not u + "0001"; --(-M)

S(5 downto 0)<=(others=>'0');

P(10 downto 6)<=(others=>'0'); --ACC & multiplier(Q) & Q_1

P(5 downto 1)<= v;

P(0)<='0';

21
P1<=P when (P(1 downto 0)="00" or P(1 downto 0)="11")else

P+A when P(1 downto 0)="01" else

P+S when P(1 downto 0)="10";

P1_shift(9 downto 0)<=P1(10 downto 1);

P1_shift(10)<=P1(10);

P2<=P1_shift when (P1_shift(1 downto 0)="00" or P1_shift(1 downto 0)="11")else

P1_shift+A when P1_shift(1 downto 0)="01" else

P1_shift+S when P1_shift(1 downto 0)="10";

P2_shift(9 downto 0)<=P2(10 downto 1);

P2_shift(10)<=P2(10);

P3<=P2_shift when (P2_shift(1 downto 0)="00" or P2_shift(1 downto 0)="11")else

P2_shift+A when P2_shift(1 downto 0)="01" else

P2_shift+S when P2_shift(1 downto 0)="10";

P3_shift(9 downto 0)<=P3(10 downto 1);

P3_shift(10)<=P3(10);

P4<=P3_shift when (P3_shift(1 downto 0)="00" or P3_shift(1 downto 0)="11")else

P3_shift+A when P3_shift(1 downto 0)="01" else

P3_shift+S when P3_shift(1 downto 0)="10";

22
P4_shift(9 downto 0)<=P4(10 downto 1);

P4_shift(10)<=P4(10);

P5<=P4_shift when (P4_shift(1 downto 0)="00" or P4_shift(1 downto 0)="11")else

P4_shift+A when P4_shift(1 downto 0)="01" else

P4_shift+S when P4_shift(1 downto 0)="10";

P5_shift(9 downto 0)<=P5(10 downto 1);

P5_shift(10)<=P5(10);

z<= P5_shift(8 downto 1);

end Behavioral;

23
 RESTORING DIVISION

A division algorithm provides a quotient and a remainder when we divide two number. They
are generally of two type slow algorithm and fast algorithm. Slow division algorithm are
restoring, non-restoring, non-performing restoring, SRT algorithm and under fast comes
Newton–Raphson and Goldschmidt.
In this article, will be performing restoring algorithm for unsigned integer. Restoring term is due
to fact that value of register A is restored after each iteration.

Here, register Q contain quotient and register A contain remainder. Here, n-bit dividend is
loaded in Q and divisor is loaded in M. Value of Register is initially kept 0 and this is the
register whose value is restored during iteration due to which it is named Restoring.

24
25
Let’s pick the step involved:
 Step-1: First the registers are initialized with corresponding values (Q = Dividend, M =
Divisor, A = 0, n = number of bits in dividend)
 Step-2: Then the content of register A and Q is shifted right as if they are a single unit
 Step-3: Then content of register M is subtracted from A and result is stored in A
 Step-4: Then the most significant bit of the A is checked if it is 0 the least significant bit
of Q is set to 1 otherwise if it is 1 the least significant bit of Q is set to 0 and value of
register A is restored i.e the value of A before the subtraction with M
 Step-5: The value of counter n is decremented
 Step-6: If the value of n becomes zero we get of the loop otherwise we repeat from step
2
 Step-7: Finally, the register Q contain the quotient and A contain remainder
Examples:
Perform Division Restoring Algorithm
Dividend = 11
Divisor = 3

N M A Q OPERATION

4 00011 00000 1011 initialize

00011 00001 011_ shift left AQ

00011 11110 011_ A=A-M

00011 00001 0110 Q[0]=0 And restore A

3 00011 00010 110_ shift left AQ

00011 11111 110_ A=A-M

00011 00010 1100 Q[0]=0

2 00011 00101 100_ shift left AQ

00011 00010 100_ A=A-M

00011 00010 1001 Q[0]=1

1 00011 00101 001_ shift left AQ

26
 N M A Q OPERATION

00011 00010 001_ A=A-M

00011 00010 0011 Q[0]=1

Remember to restore the value of A most significant bit of A is 1. As that register Q contain the
quotient, i.e. 3 and register A contain remainder 2.

VHDL CODE:
----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity restoring_division is

Port ( x : in STD_LOGIC_vector(3 downto 0); --dividend

y : in STD_LOGIC_vector(3 downto 0); --divisor

quotient : out STD_LOGIC_vector(3 downto 0);

remainder: out STD_LOGIC_vector(3 downto 0));

end restoring_division;

architecture Behavioral of restoring_division is

27
signal A,S,P: STD_LOGIC_vector(7 downto 0);

signal P44,P444,P33,P333,P22,P222,P11,P111,P1,P2,P3,P4,P1_shift,P2_shift,P3_shift,P4_shift:
STD_LOGIC_vector(7 downto 0);

begin

A(7 downto 4)<= y; --divisor(y)(M)

A(3 downto 0)<=(others=>'0');

S(7 downto 4)<= not y + "0001"; --(-M)

S(3 downto 0)<=(others=>'0');

P(7 downto 4)<=(others=>'0'); --ACC & dividend(Q)

P(3 downto 0)<= x;

Process (P,S,P1_shift,P1,P11)

begin

P1_shift(7 downto 1)<=P(6 downto 0);

P1_shift(0)<= '0';

P1<= P1_shift + S;

P11<= P1(7 downto 1) & not P1(7);

28
if(P1(7) = '1')then

P111<=P11+A;

else

P111<=P11; --P12

end if;

end process;

process(P111,S,P2_shift,P2,P22)

begin

P2_shift(7 downto 1)<=P111(6 downto 0);

P2_shift(0)<= '0';

P2<= P2_shift + S;

P22<= P2(7 downto 1) & not P2(7);

if(P2(7) = '1')then

P222<=P22+A;

else

P222<=P22; --P12

end if;

end process;

process(P222,S,P3_shift,P3,P33)

29
begin

P3_shift(7 downto 1)<=P222(6 downto 0);

P3_shift(0)<= '0';

P3<= P3_shift + S;

P33<= P3(7 downto 1) & not P3(7);

if(P3(7) = '1')then

P333<=P33+A;

else

P333<=P33; --P12

end if;

end process;

process(P333,S,P4_shift,P4,P44)

begin

P4_shift(7 downto 1)<=P333(6 downto 0);

P4_shift(0)<= '0';

P4<= P4_shift + S;

P44<= P4(7 downto 1) & not P4(7);

if(P4(7) = '1') then

P444<=P44+A;

else

P444<=P44; --P12

30
end if;

end process;

quotient<= P444(3 downto 0);

remainder<= P444(7 downto 4);

end Behavioral;

31
 VHDL CODE BIT-4 CALCULATOR

--------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity bit4calculator is

Port ( x : in STD_LOGIC_vector(3 downto 0);

y : in STD_LOGIC_vector(3 downto 0);

c : in STD_LOGIC; --carry

s : in STD_LOGIC_vector(1 downto 0); --select

z : out STD_LOGIC_vector(7 downto 0)); --output

end bit4calculator;

architecture structural of bit4calculator is

component bit4adder is

Port ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);

32
 u :in std_logic;

so : out STD_LOGIC_vector(7 downto 0));

end component;

component bit4subst is

Port ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);

u :in std_logic;

so : out STD_LOGIC_vector(7 downto 0));

end component;

component booth_multiplier is

Port ( x : in STD_LOGIC_vector(3 downto 0);

y : in STD_LOGIC_vector(3 downto 0);

z : out STD_LOGIC_vector(7 downto 0));

end component;

component restoring_division is

Port ( x : in STD_LOGIC_vector(3 downto 0); --dividend

y : in STD_LOGIC_vector(3 downto 0); --divisor

quotient : out STD_LOGIC_vector(3 downto 0);

33
 remainder: out STD_LOGIC_vector(3 downto 0));

end component;

component bit8mux4x1B is

Port ( a,b,c,d : in STD_LOGIC_vector(7 downto 0);

s : in STD_LOGIC_vector(1 downto 0);

y : out STD_LOGIC_vector(7 downto 0));

end component;

signal z1,so1,so2,t3,t2,t1,t0 :STD_LOGIC_vector(7 downto 0);

signal quotient,remainder :STD_LOGIC_vector(3 downto 0);

begin

I1:bit4adder port map (x,y,c,so1);

I2:bit4subst port map (x,y,c,so2);

I3:booth_multiplier port map (x,y,z1);

I4:restoring_division port map (x,y,quotient,remainder);

t3<= so1;

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t2<= so2;

t1<=z1;

t0<=quotient & remainder;

I5:bit8mux4x1B port map (t3,t2,t1,t0,s,z); --first time 2 times same s given;

end structural;

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 RESULTS
Timing Report:

Clock Information:
Clock Signal Clock buffer (FF name) Load
CLK BUFGP 38
clk251 BUFG 70
Asynchronous Control Signals Information:
Clock Signal Clock buffer (FF name) Load
RST IBUF 72

Timing Summary:
Speed Grade: -4
Minimum period: 10.319ns (Maximum Frequency: 96.909MHz)
Minimum input arrival time before clock: 2.444ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found

Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 7.350ns (frequency: 136.054MHz)
Total number of paths / destination ports: 1400 / 77
Delay: 7.350ns (Levels of Logic = 9)
Source: counter_1s_8 (FF)
Destination: delay_count_0 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: counter_1s_8 to delay_count_0
Total 7.350ns (3.971ns logic, 3.379ns route)
(54.0% logic, 46.0% route)

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Timing constraint: Default period analysis for Clock 'clk251'
Clock period: 10.319ns (frequency: 96.909MHz)
Total number of paths / destination ports: 6022 / 102
Delay: 10.319ns (Levels of Logic = 13)
Source: vPos_3 (FF)
Destination: RGB_0 (FF)
Source Clock: clk251 rising
Destination Clock: clk251 rising
Data Path: vPos_3 to RGB_0
Total 10.319ns (4.865ns logic, 5.454ns route)
(47.1% logic, 52.9% route)

Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'

Total number of paths / destination ports: 1 / 1
Offset: 2.444ns (Levels of Logic = 2)
Source: sensor (PAD)
Destination: current_state_FSM_FFd2 (FF)
Destination Clock: CLK rising
Data Path: sensor to current_state_FSM_FFd2
Total 2.444ns (1.575ns logic, 0.869ns route)
(64.4% logic, 35.6% route)

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk251'

Total number of paths / destination ports: 5 / 5
Offset: 7.165ns (Levels of Logic = 1)
Source: VSYNC (FF)
Destination: VSYNC (PAD)
Source Clock: clk251 rising
Data Path: VSYNC to VSYNC
Total 7.165ns (6.364ns logic, 0.801ns route)
(88.8% logic, 11.2% route)

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 Simulation

Implementation on FPGA

Steps taken for implementation of the code on Spartan 3:

 Set the code to be implemented on hardware as ‘Top Module’.
 Change design settings of XC3S1500 as given for Spartan 3.
 Add new source in the selected file.
 Select ‘Implementation constraints file’.
 Keep the file name same as the name of the code selected for ease of access.
 Write ‘net’ input for input written in the primary code and ‘loc =’ ‘pin number’ for choosing 
location of the board.
 Check synthesize-RST.
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 Then implement design.
 Generate programming file.
 Then configure target device.
 A new window pops up.
 Select Boundary Scan.
 Right click on the white space and the click on initialize chain.
 A .bit file would be created of the code we are implementing on Spartan 3.
 Right click on the device added and click program.
 The program is uploaded on the hardware and code is ready to run.

Implementation using SPARTAN 3

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