Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By

Application Nischita

Figure 22.2 :General wireless communication model

We shall concentrate on the receiver model for wireless communication.

Receiver :

The receivers can be categorized as analog and digital receivers.

Analog receiver:
Radio receivers have been around for about one hundred years. While there have been
dramatic advances in component technology since the crystal radio, and revolutionary
improvements in system architecture such as the superheterodyne circuit, receivers have
relied primarily on analog devices for the RF signal path.
During the last 25 years receivers have been equipped with features such as digital
readouts for frequency display, and digitally
digitally-controlled phase-locked
locked loop synthesizers to
replace the older LC local oscillators.
Nevertheless, these recei
receivers
vers still employ analog signal processing and radio
receivers are existing since several years. There have been numerous advances in the
technology
nology used since then. Figure 2.3 shown below is of an analog receiver.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

Figure 2.3 :Generalized analog receiver

Digital receivers:
Digital receiver technology has now replaced many of the traditional analog
techniques of radio reception. However, the same basic principles of signal theory apply as
well. Widespread use of radio transmissions of digital data now supports booming markets
for cell phones, pagers, wireless LANs, satellite communication and HDTV, to name just a
few. Here, the benefits of digital receivers can really shine. Digital data transmission employs
dozens of different schemes for encoding phase, amplitude and frequency, each scheme
targeted for a specific application. On the receiving side, demodulation tasks for the DSP
processor include channel equalization, symbol tracking, frame detection, convolution, error
correction, decoding, and decompression.
No approach other than digital signal processing could possibly handle these tasks.
Because they are inherently programmable, as new modulation standards are invented, digital
receiver systems can often be upgraded by loading new software routines instead of replacing
expensive hardware. The other major benefit of digital receiver systems is the economy of
scale for high channel count systems. While it may still be cheaper to use an analog receiver
in our communication device, a cell phone base station takes full advantage of low cost per
channel, low power, improved accuracy and stability, high reliability, reconfigurability and
fast switching characteristics offered by digital receiver technology.
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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

Figure 2.4 : Generalized digital receiver

As seen from the analog and digital receiver figures, we infer that the digital receiver
architecture is more complicated, then, what makes us consider digital receivers over analog
counterparts? The simplest of answers would be because of the improvement of some of the
critical parameters such as signal to noise(S/N) ratio , sensitivity, selectivity, and adjacent
channel rejection(ACR)

Now, briefing about one of the main components of a digital receiver – Filter.
Filters: Filters are systems which perform operations on signal to enhance or diminish
certain properties of the signal. For example, a filter can function by accepting an input
signal and blocking pre-specified frequency components and passing the input signal sans the
unwanted components as the output

The filters can be analog or digital.

 Analog filter operates on continuous time signal with analog components

 A digital filter takes a digital input, gives a digital output and consists of digital
components.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

The most common filters being classified based on the acceptance or rejection of
certain frequency components. They are low pass filter, high pass filter, band pass and band
stop filters.

Let us concentrate on the digital counterpart. In a typical digital filtering application,

input samples are read from an A/D converter, the mathematical operations dictated by the
required filter type are performed , and the result is output to the successive component of the
larger system.
Digital filters are a vital part of Digital System Processing(DSP). The popularity of
DSP is because of its remarkable performance, which is one of the key reasons for opting it.
Digital filters are far superior in the level of performance that can be achieved compared to
that of analog filter. This makes an impressive difference on how the filtering problems are
tackled by each kind of filters.
Digital filters can be divided into two categories: Finite Impulse Response [FIR]
filters and Infinite Impulse Response [IIR] filters.

A finite impulse response [FIR] filter is a filter structure that is used to implement
almost any sort of frequency response digitally. A FIR filter is usually implemented using a
series of delays, multipliers and adders to create the filter’s output.

Although FIR filters, in general, require higher taps than IIR filters to obtain similar
frequency characteristics, FIR filters are widely used because they have linear phase
characteristics guarantee stability and are easy to implement with multipliers, adders and
delay elements.

Another component important in the digital filter is a Decimator.

To describe a Decimator, we shall describe an interpolator first.
Interpolator: An increase in the sampling rate by an integer factor L can be
accomplished by interpolating L-1 new samples between successive values of the signal. The
term interpolation refers to the process of converting a sampled digital signal to a higher
sampling rate using various digital filtering techniques. The component performing this

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

process is an Interpolator. This process is usually done at the transmitter side of the
communication system to increase the transmission frequency of the signal.

Decimator: Decimation is a technique for reducing the number of samples in

a discrete-time signal. The component which implements this technique is referred to as
a decimator.

Decimation is a two-step process:

1. Low-pass anti-aliasing filter

2. Downsampling
The mainstream concept of reconfigurability of the FIR filter, extracted from the
literature survey, has been explained in further chapters of this book.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

CHAPTER 3

3 DESCRIPTION OF THE PROJECT

In this chapter we shall give a brief description about the solution approach to the
problem definition stated in the section 1.2 with the existing and proposed architecture setup.

3.1 Building blocks of the Project setup

As stated in the section 1.3, we aim to design a 3g standard wireless filter which can
be made reconfigurable to facilitate lesser power consumption by the filter with the support
of components such as decimator , High Pass Filter (HPF), Signal Power Measurement
(SPM) unit. The reduction of power consumption of the 3G filter in turn increases the battery
life of the terminal which uses this.
This can be achieved by two similar approaches

 Implementation of reconfigurable FIR filter by introducing a control unit that shaves

the taps (multipliers) based on the content of ACI

 Implementation of reconfigurable FIR filter as stated above and replacing the

decimator prior to the reconfigurable filter.

Representing these approaches in a system level block diagram, gives us an overview of the

placement of the filter in a receiver system.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By
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Approach 1

Figure 3.1 ::System Level Block Diagram with Approach 1

Approach 2

Figure 3.2 ::System Level Block Diagram with Approach 2

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In commercial filter, there exists filters with the fixed number of taps. Utilization of
all the taps gives us an excellent performance. But, not all situations require all the taps to
work to give a good performance. At times, usage of only few taps are sufficient. And usage
of all the taps at such instances will be unnecessary.

To alleviate this problem, the FIR filter chips providing variable-length taps have
been used in many application fields.

Multipliers are one of the critical components of many high performance systems
such as FIR filters, microprocessors, digital signal processors, etc. Multiplier being the
slowest element in a system, the system’s performance is generally dependent on the
performance of this critical element. The reason for multiplier being the slowest element is
due to its complex structure which consists of several transistors or switches. For example we
shall consider a Booth Multiplier which performs operations such as shifting, adding and
subtraction. Every step in this process requires one of these operations to be performed due to
which the multiplier is very active throughout the process. This leads to an enormous
amount of power consumption. Excess switching activity can also cause humongous power
consumption. Therefore power reduction in this key component is necessary.

The approach 2 also reduces the switching activity by reducing the frequency of
operation of the filter by a factor 4 (decimation factor: 4) , thereby reducing the speed and
power consumption of the filter,

The approach 2 is fairly complex compared to the approach 1 but the second
approach is very enticing in terms of the power consumption. Therefore, the approach 2 is
considered for this project.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

Now let us consider the block diagram of the existing architecture of the filter-decimator
combination

Input Output
FIR DECIMATOR
FILTER

Figure 3.3 :Existing architecture of the filter-decimator combination

The figure 3.3 shows the existing architecture of the filter-decimator combination
which consists of a FIR filter followed by a decimator. The filter, as the name suggests,
filters the unwanted component of its input signal and allows the rest. The most abrupt reason
to decimate is simply to reduce the sampling rate i.e by removing the interpolated ‘0’s done
at the transmitter side. This is performed so that the successive systems operating at a lower
sampling rate can input the decimated signal. But a much more common reason for
decimation is to reduce the cost of processing such as the calculations done to implement a
DSP and can be the memory required to implement a DSP is usually directly proportional to
the sampling rate, so lower the sampling rate in a cheaper the implementation.

The decimator is placed after the FIR filter because the FIR filter implementation
requires the previous and the current samples for the calculation and decimating before the
filtering would alter the required results.

Now we shall move on to the proposed architecture of the reconfigurable filter.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By
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Figure 3.4: Proposed architecture of the filter

filter-decimator
decimator combination

Figure 3.4 show the proposed architecture. In comparison to the figure 3.7 we can see
that the decimator is placed prior to the FIR filter and components such as HPF and a control
unit have been added. The decimator here is placed prior to FIR filter such that it decimates
de
the unwanted components of the signal and improves the performance of the filter although
not altering the properties of the filter thereby ensuring the proper operation of the filter.

The table 3.1 gives us details about the 3G Specifications bas

based
ed on International Mobile
Telephony IMT-2000

Table 3.1: 3G Specifications based on International Mobile Telephony IMT

IMT--2000

Parameter Value

Frame length 10ms

Number of slots / frame 15

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