SERVICE MANUAL & TROUBLESHOOTING GUIDE FOR

7170

BY： Richard Wang

TESTING TECHNOLOGY DEPARTMENT / TSSC
JUL. 2001
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CONTENTS

1. Hardware Engineering Specification-------------------------------------------------------------------------------- 3

Specification--------------------------------------------------------------------------------
1.1 Introduction------------------------------------------------------------------------------------------------------------------------------ 3
1.2 Hardware System----------------------------------------------------------------------------------------------------------------------- 4
1.3 System Power Management---------------------------------------------------------------------------------------------------------- 34
1.4 Firmware - System BIOS & Keyboard BIOS------------------------------------------------------------------------------------- 37
1.5 Periperal Component------------------------------------------------------------------------------------------------------------------ 39

2. System Assembly & Disassembly----------------------------------------------------------------

Disassembly-------------------------------------------------------------------------------------
--------------------- 43
2.1 System View ------------------------------------------------------------------------------------------------------------------------------ 43
2.2 System Disassembly -------------------------------------------------------------------------------------------------------------------- 46

3. Definition & Location Connectors / Switches Setting ----------------------------------------------------------- 65

3.1 7170 Main Board ------------------------------------------------------------------------------------------------------------------------ 65
3.2 7170 DC Power Board ----------------------------------------------------------------------------------------------------------------- 68
3.3 7170 ESB Board ------------------------------------------------------------------------------------------------------------------------- 69
3.4 7170 Touch Pad Board ----------------------------------------------------------------------------------------------------------------- 69

4. Definition & Location Of Major Components----------------------------------------------------------------

Components---------------------------------------------------------------------
----- 70
4.1 7170 Main Board ------------------------------------------------------------------------------------------------------------------------ 70

5. Pin Descriptions Of Major Components ---------------------------------------------------------------------------

--------------------------------------------------------------------------- 72
5.1 Pentium III/Celeron µPGA2 CPU -------------------------------------------------------------------------------------------------- 72
5.2 VIA VT8603 Twister North Bridge Controller ---------------------------------------------------------------------------------- 78
5.3 VIA VT8231 Sorth Bridge Controller --------------------------------------------------------------------------------------------- 88

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CONTENTS

------------------------------------------------------------------------------------------------- 100
6. System Block Diagram -------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------- 101
7. Maintenance Diagnostic -----------------------------------------------------------------------------------------------
7.1 Introduction ----------------------------------------------------------------------------------------------------------------------------- 101
7.2 Error Codes ----------------------------------------------------------------------------------------------------------------------------- 102
7.3 Diagnostic Tools ------------------------------------------------------------------------------------------------------------------------ 108
7.4 Circuit ------------------------------------------------------------------------------------------------------------------------------------ 108

8. Trouble Shooting --------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------- 109
8.1 No Power --------------------------------------------------------------------------------------------------------------------------------- 110
8.2 No Display ------------------------------------------------------------------------------------------------------------------------------- 118
8.3 VGA Controller Failure -------------------------------------------------------------------------------------------------------------- 121
8.4 Memory Test Error -------------------------------------------------------------------------------------------------------------------- 123
8.5 Keyboard ( K/B ) , Touch-Pad ( T/P ) , ESB Test Error ----------------------------------------------------------------------- 125
8.6 CD-ROM Drive Test Error ---------------------------------------------------------------------------------------------------------- 127
8.7 Hard Drive Test Error ---------------------------------------------------------------------------------------------------------------- 129
8.8 USB Port Test Error ------------------------------------------------------------------------------------------------------------------ 131
8.9 PIO Port Test Error ------------------------------------------------------------------------------------------------------------------- 133
8.10 Audio Failure -------------------------------------------------------------------------------------------------------------------------- 135

9. Spare Parts List ----------------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------- 137

10. System Explode View -------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------- 146

11. Circuit Diagram --------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------- 147

12. Reference ----------------------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------------- 175
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1. Hardware Engineering Specification

1.1. Introduction
1.1.1. General Description
This document describes the system hardware engineering specification for 7170 portable notebook computer system.
The 7170NB is a excellently high performance and highly portable platform.

1.1.2. System Overview

The Architecture of 7170NB is based on PCI - ISA structure. It provides a high performance platform on PCI bus up
to 33MHz and is fully compatible with IBM PC/AT specification which have standard hardware peripheral interface and
supports AGP 4X(133MHz). 7170NB adopts Intel Celeron 128K integrated level 2 cache in a FC-PGA package which have
an excellent ability of code execution for multimedia applications operating at 700/733/766 and 800MHz & Intel Pentium Ⅲ
CPU , 256K integrated level 2 cache in a FC-PGA package which have an excellent ability of code execution for multimedia
applications operating at 800/866/933/1G and 1.33GHz
The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy
configuration through CMOS ROM setup which is built in system BIOS software and can be pop-up by pressing F2 at
system start up or warm reset. System also provides LEDs to display system status, such as HDD, FDD, CD-ROM, NUM
LOCK, CAP LOCK, SCROLL LOCK, AC Power indicator and battery present, capacity & charging, email/Blue-tooth status
7170NB system is equipped with one 2.5”, hard disk drive(supports Ultra DMA33/66), one 5 1/4" 24x CD-ROM
drive(DVD optional), one USB floppy, one 56kbps Fax/Modem, one 10/100 Mb LAN, one PCMCIA sockets, internal
keyboard, Touch pad with scroll-up/down buttons, two stereo speakers, TFT LCD panel, one FIR, PIO/TV-OUT, one VGA
connector for CRT and one PS/2 port for external keyboard or mouse. System also provides in-system flash ROM
programming for easy future upgrade.
A full set of software drivers and utilities are available to allow advanced operating system such as Windows 98 ,
Windows 98SE ,Window NT ,Window2000, Windows ME and Windows XP to take full advantages of the hardware
capabilities. Features such as bus mastering IDE, Windows 98-ready Plug & Play, Advanced Power Management (APM)
with application restart, software-controlled power shutdown.
Following chapters will describe more detail for each individual sub-systems and functions. 3
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1 .2 . H a rd w a r e S y stem
1 .2 .1 S y ste m b lo c k
Int. MIC
USB Mini
CRT 2/1 MODEM 1394 PS2 PRINTER TV-OUT ACIN

FIR

FAN POWER
CPU ON/OFF
Q-KEY BOARD
LAN
PCMCIA
D/D BOARD
CDROM

SODIMMx2

T-PAD

HDD MDC

MINI-PCI BATTERY

SPKR LEDs EMAIL/ SPKR

L-OUT VOLUME LID
Blue- MIC L-IN
Tooth

T-PAD BOARD
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1.2.2 System parts

CPU : Intel Celeron (700/733/766/800MHz) with FC-PGA package OR
Intel Pentium Ⅲ (800EB/866/933/1000/1133MHz) with FC-PGA package
Space reserve for VIA CyrixIII

CORE LOGIC :
VIA VT8603 (North Bridge : 66/100/133 SOCKET 370 CPU
Integrated S3 Savage4 AGP4X Graphics Core with LVDS Interface
Memory Controller Supporting PC100/PC133 SDRAM
VIA VT8231(South Bridge) : PC99 Compliant PCI to ISA Bridge
Integrated Super-IO (LPT, COM)
Integrate Fast Ethernet
AC97 Audio, USB, RTC
UltraDMA-33/66 Master Mode PCI-EIDE Controller for HDD,
DROM/DVD
ACPI, EPM, SMBus, Temperature Monitor

PCMCIA Controller : TI PC4410(PCMCIA) + TPS2211(Power Switch)

1394 Controller : TI PC4410(MAC) + TSB41AB1(PHY)

FIR Controller : NS 97338VJG

Embedded Controller : Hitachi H8/3437S

Audio System : Codec RealTek ALC200 (or Crystal CS4299) PQFP + Amp. TI TPA0202

FIR Module : HP HSDL-3600#007 IR module

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Thermal Sensor : AD1021 (or Genesys Logic GL528SM)

Memory System : Two 144 pin SO-DIMM (PC100/PC133 64/128/256MB)

Flash Memory (BIOS) : 28F020(2M bit)

56.6K FAX/MODEM RJ11 : 30 pin MDC board

LAN RJ45 : VT8231(MAC) + LSI80227(PHY)

Mini PCI : Wireless LAN/ Modem

Other Function : Reserve Blue Tooth function

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1.2.3 CPU
Intel Celeron Processor for the FC-PGA370 socket

Available at 800/ 766/ 733/ 700/ 733/ 700/ 667/ 633/ 600/ 566 /533 /533/ 500/ 466/ 433/ 400/ 366/ 333
/ 300 MHz core frequencies with 128KB level-two cache (on die). (300/ 266 MHz core frequencies
without level-two cache).

Intel’s latest Celeron processors in the FC_PGA package are manufactured using the advanced 0.18
micron technology.

Binary compatible with applications running on previous members of the Intel microprocessor line.

Dynamic execution microarchitecture.

Operates on a 66MHz, transaction-oriented system bus.

Specifically designed for uni-processor based Value PC systems, with the capabilities of MMX
technology.

Power Management capabilities.

Optimized for 32-bit applications running on advanced 32-bit operating systems.

Integrated high performance 32KB instruction and data, nonblocking, level-one cache : separate 16KB
instruction and 16KB data caches.

Integrated thermal diode.

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Pentium Ⅲ Processor for the FC-PGA370 socket

Available in 1.133G/ 1.0G/ 933/ 866/ 800EB/ 733/ 667,600EB/ 533EB MHz for 133 MHz system
bus.

Available in 850/ 800/ 750/ 700/ 650/ 600E/ 550E and 550E MHz for 100 MHz system bus.

System bus frequency at 100 MHz and 133 MHz(“E” denotes support for Advanced Transfer Cache
and Advanced system buffering ;”B” denotes support for a 133MHz System bus where both bus
frequencies are available for order per each given core

Available in versions that incorporate 256KB Advanced Transfer Cache(on-die, full speed Level 2(L2)
cache with Error Correcting Code(ECC))

Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and dedicated internal high-speed Cache bus.

Internet Streaming SIMD Extensions for enhanced video ,sound and 3D performance

Binary compatible with applications running on previous members of the Intel microprocessor line.

Dynamic execution micro architecture.

Intel Processor Serial Number.

Power Management capabilities

System Management mode

Multiple low-power states.

Optimized for 32-bit applications running on advanced 32-bit operating system.

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Flip Chip pin Grid Array (FC-PGA) packaging technology ;FC-PGA processors deliver high
performance with improved handling protection and socketability.

Integrated high performance 16KB instruction and 16KB data, nonblocking, level one cache.

256 KB Integrated Full Speed level two cache allows for low latency on read/store operations.

Double Quad Word Wide (256bit) cache data bus provides extremely high throughput on read/store
operations.

8-way cache associativity provides improved cache hit rate on reads/store operations.

Error-correcting code for Systen Bus data.

Enables systems which are scaleable for up to two processor.

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1.2.4 Core Logic Controller :

1.2.4.1 VIA Twister VT8603 (with Mobile VGA Savage4)

CPU Interface
 Socket 370 support for Intel Pentium III, Pentium II, and Celeron processors
66/100/133 MHz CPU FrontSide Bus (FSB)
 Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions
Five outstanding transactions (four In-Order Queue (IOQ) plus one output latch)
Dynamic deferred transaction support

Advanced High-Performance DRAM Controller

DRAM interface runs synchronous (66/66, 100/100, 133/133) mode or pseudo
-synchronous (66/100, 100/66,
100/133,133/100) mode with FSB
Concurrent CPU, AGP, and PCI access
Supports SDRAM and VCM SDRAM memory types
Support 3 DIMMs or 6 banks for up to 1.5 GB of DRAM (256Mb DRAM technology)
64-bit data width
Supports maximum 8-bank interleave (8 pages open simultaneously); banks are allocated based on LRU
SDRAM X-1-1-1-1-1-1-1 back-to-back accesses

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Integrated Savage4 2D/3D/Video Accelerator
– Optimized Shared Memory Architecture (SMA)
– 8 to 32 MB frame buffer using system memory
– Floating point triangle setup engine
– Single cycle 128-bit 3D architecture
– 8M triangles/second setup engine
– 140M pixels/second trilinear fill rate
– Full internal AGP 4x performance
– S3 DX7 texture compression (S3TCÔ)
– Next generation, 128-bit 2D graphics engine
– High quality DVD video playback
– Flat panel monitor support
– 2D/3D resolutions up to 1920x1440

3D Rendering Features
– Single-pass multiple textures
– Anisotropic filtering
– 8-bit stencil buffer
– 32-bit true color rendering
– Specular lighting and diffuse shading
– Alpha blending modes
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– Massive 2K x 2K textures
– MPEG-2 video textures
– Vertex and table fog
– 16 or 24-bit Z-buffering
– Sprite anti-aliasing, reflection mapping, texture morphing, shadows, procedural textures and atmospheric effects

2D Hardware Acceleration Features

– ROP3 Ternary Raster Operation BitBLTs
– 8, 16, and 32 bpp mode acceleration

Motion Video Architecture

– High quality up/down scaler
– Planar to packed format conversion
– Motion compensation for full speed DVD playback
– Hardware subpicture blending and highlights
– Multiple video windows for video conferencing
– Contrast, hue, saturation, brightness and gamma controls
– Digital port for NTSC/PAL TV encoders

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Extensive LCD Support
– 36-bit DSTN/TFT flat panel interface with 256 gray shade support
– Integrated 2-channel 110 MHz LVDS interface
– Support for all resolutions up to 1280x1024
– ZV-Port Interface
– Panel power sequencing
– Hardware Suspend/Standby control

Flat Panel Monitor Support
– 12-bit TFT flat panel interface to TMDS encoders
– Digital Visual Interface (DVI) 1.0 compliant

Concurrent PCI Bus Controller
– PCI 2.2 compliant, 32-bit 3.3V PCI interface with 5V tolerant inputs
– Supports up to 5 PCI masters
– PCI to system memory data streaming support
– Delay transaction from PCI master accessing DRAM
– Symmetric arbitration between Host/PCI bus for optimized system performance

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Advanced System Power Management Support
– Dynamic power down of SDRAM (CKE)
– Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus
– PCI and AGP bus clock run and clock generator control
– VTT suspend power plane preserves memory data
– Suspend-to-DRAM and self-refresh power down
– Low-leakage I/O pads
– ACPI 1.0 and PCI Bus Power Management 1.1 compliant

Full Software Support
– Drivers for major operating systems and APIs: [Windows 9x, Windows NT 4.0, Windows 2000, Direct3D,
DirectDraw and DirectShow, OpenGL ICD for Windows 9x, NT, and 2000]
– North Bridge/Chipset and Video BIOS support

Additional Features
– 250 MHz RAMDAC with Gamma Correction
– 12-bit interface to external TV encoder
– I 2 C Serial Bus and DDC Monitor Communications
– 2.5V Core and Mixed 3.3V/5V Tolerant and GTL+ I/O

35 x 35mm PBGA package with 552 balls

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1.2.4.2 South Bridge VIA VT8231

Inter-operable with VIA and other Host-to-PCI Bridges
– Combine with VT82C694X for a complete 66 / 100 / 133 MHz Socket370 AGP 4x system (Apollo
Pro133A)
– Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket370 system with integrated 2D/3D
graphics (Apollo ProMedia)
– Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI/AGP system

Integrated Peripheral Controllers
– Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability
– Integrated USB Controller with two root hub and four function ports
– Dual channel UltraDMA-33 / 66 master mode EIDE controller
– AC-link interface for AC-97 audio codec and modem codec
– HSP modem support
– Integrated SoundBlasterPro / DirectSound compatible digital audio controller

Integrated Legacy Functions
– Integrated Keyboard Controller with PS2 mouse support
– Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm
for ACPI
– Integrated Bus Controller including DMA, timer, and interrupt controller
– Serial IRQ for docking and non-docking applications
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– Flash EPROM, 32Mbit (4Mbyte) EPROM and combined BIOS support
– Fast reset and Gate A20 operation

Fast Ethernet Controller
– High performance PCI master interface with scatter / gather and bursting capability
– Standard MII interface to Ethernet or HomePNA PHYceiver
– 1 / 10 / 100 MHz full and half duplex operation
– Transmit data buffer byte alignment for low CPU utilization
– Separate 2K byte FIFOs for receive and transmit of full Ethernet packets
– Flexible dynamically loadable EEPROM algorithm
– Physical, Broadcast, and Multicast address filtering using hashing function
– Flexible wakeup events: link status change, magic packet, unicast physical address match, predefined pattern
match
– Software controllable power down

UltraDMA-33 / 66 / 100 Master Mode PCI EIDE Controller
– Dual channel master mode PCI supporting four Enhanced IDE devices
– Transfer rate up to 100MB/sec to cover up to PIO mode 4, multi-word DMA mode 2, and UltraDMA mode 5
– Thirty-two levels (doublewords) of prefetch and write buffers per channel
– Dual DMA engine for concurrent dual channel operation
– Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 / 98 / 2000 compliant
– Full scatter gather capability
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– Support ATAPI compliant devices including DVD devices
– Support PCI native and ATA compatibility modes
– Complete software driver support

Integrated Super IO Controller
– Supports IR port, parallel port, and floppy disk controller functions
– Serial Port Programmable character lengths (5,6,7,8)
Even, odd, stick or no parity bit generation and detection
Programmable baud rate generator
Independent transmit/receiver FIFOs Modem Control
Plug and play with 96 base IO address and 12 IRQ options
– Fast IR (FIR) port
IrDA 1.0 SIR and IrDA 1.1 FIR compliant
IR function through the second serial port
Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR
– Multi-mode parallel port
Standard mode, ECP and EPP support
Dynamic and static switch between parallel port pinout and FDC pinout
Plug and play with 192 base IO address, 12 IRQ and 4 DMA options
– Floppy Disk Controller
16 bytes of FIFO
Data rates up to 1Mbps
Perpendicular recording driver support
Two FDDs with drive swap support
Plug and play with 48 base IO address, 12 IRQ and 4 DMA options 17
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SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller
– Dual full-duplex Direct Sound channels between system memory and AC97 link
– PCI master interface with scatter / gather and bursting capability
– 32 byte FIFO of each direct sound channel
– Host based sample rate converter and mixer
– Standard v1.0 or v2.0 AC97 Codec interface for single or cascaded AC97 Codec’s from multiple vendors
– Loopback capability for re-directing mixed audio streams into USB and 1394 speakers
– Hardware SoundBlaster Pro for Windows DOS box and real-mode DOS legacy compatibility
– Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware
– Hardware assisted FM synthesis for legacy compatibility
– Direct two game ports and one MIDI port interface
– Complete software driver support for Windows-95/98/2000 and Windows-NT

MC97 HSP Modem Controller
– PCI bus master interface with scatter / gather and burst capability
– Standard AC97 codec interface for MC or AMC codec
– Wake on ring in APM or ACPI mode through AC97 link
– Supported by most HSP modem vendors

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Universal Serial Bus Controller
– USB v.1.1 and Intel Universal HCI v.1.1 compatible
– Eighteen level (doublewords) data FIFO with full scatter and gather capability
– Root hub and four function ports
– Integrated physical layer transceivers with optional over-current detection status on USB inputs
– Legacy keyboard and PS/2 mouse support

System Management Bus Interface
– One master / slave SMBus and one slave-only SMBus
– Host interface for processor communications
– Slave interface for external SMBus masters

Voltage, Temperature, Fan Speed Monitor and Controller
– Five universal input channels for voltage or temperature sensing
– Two fan-speed monitoring channels
– Input channel for thermal diode in Intel™ high speed Pentium II™ / Pentium III™ CPUs
– Programmable control, status, monitor and alarm for flexible desktop management
– External thermister or internal bandgap temperature sensing
– Automatic clock throttling with integrated temperature sensing
– Internal core VCC voltage sensing
– Flexible external voltage sensing arrangement (any positive supply and battery)

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Sophisticated PC99-Compatible Mobile Power Management
– Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
– ACPI v1.0 Compliant
– APM v1.2 Compliant
– CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
– PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
– Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
– Multiple suspend power plane controls and suspend status indicators
– One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
– Normal, doze, sleep, suspend and conserve modes
– Global and local device power control
– System event monitoring with two event classes
– Primary and secondary interrupt differentiation for individual channels
– Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close
for system wake-up
– Multiple internal and external SMI sources for flexible power management models
– One programmable chip select and one microcontroller chip select
– Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
– Thermal alarm on either external or any combination of three internal temperature sensing circuits
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– Hot docking support
– I/O pad leakage control

Plug and Play Controller
– PCI interrupts steerable to any interrupt channel
– Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI
– Steerable DMA channels for integrated parallel, and soundblaster pro controllers
– One additional steerable interrupt channel for on-board plug and play devices
– Microsoft Windows 2000 TM , Windows ME TM ,Windows 98SE TM , Windows 98 TM , Windows NT TM ,
Windows 95 TM and plug and play
BIOS compliant

Built-in NAND-tree pin scan test capability

0.30um, 3.3V, low power CMOS process

Single chip 27x27 mm, 376 pin BGA

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1.2.5 PCMCIA/1394 Link Controller: PCI4410

The PCI4410 supports the following features:
- A 209-ball MicroStar Ball Grid Array (GHK) package
- 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
- Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
- Single PC Card or CardBus slot with hot insertion and removal
- Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
- Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
- Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
- Pipelined architecture allows greater than 130M bps sustained throughput from CardBus-to-PCI and
fromPCI-to-CardBus
- Interface to parallel single-slot PC Card power interface switches like the TI TPS2211
- Up to five general-purpose I/Os
- Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
- Two I/O windows and two memory windows available to the CardBus socket
- Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space
- Intel 82365SL-DF and 82365SL register compatible
- Distributed DMA (DDMA) and PC/PCI DMA
- 6-Bit DMA on the PC Card socket
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- PCI Bus Lock (LOCK)
- Advanced Submicron, Low-Power CMOS Technology
- Internal Ring Oscillator

1.2.6 LAN PHY: LSI80227

features:
- Single Chip 100Base-TX / FX/10Base-T Physical Layer Solution
- 3.3V Version of SEEQ 80221
- Dual Speed - 10/100 Mbps
- Half And Full Duplex
- MII Interface To Ethernet Controller
- MI Interface For Configuration & Status
- Optional Repeater Interface
- AutoNegotiation: 10/100, Full/Half Duplex
- Meets All Applicable IEEE 802.3 Standards
- On Chip Wave Shaping - No External Filters Required
- Adaptive Equalizer
- Baseline Wander Correction
- Interface to External 100Base-T4 PHY
- LED Outputs: Link/Activity/ Collision/ Full Duplex/ 10/100/ User Programmable 23
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- Many User Features And Options
- Few External Components
- 3.3V Supply with 5V Tolerant I/O
- 64L TQFP

1.2.7 Embedded Controller : Hitachi H8/3437S

CPU
- Two-way general register configuration
Eight 16-bit registers or Sixteen 8-bit registers
- High-speed operation
Maximum clock rate : 16Mhz at 5V

Memory
- Include 32KB ROM and 1KB RAM

16-bit free-running timer
- One 16-bit free-running counter
- Two output-compare lines
- Four input capture lines

8-bit timer ( 2 channels )
- Each channel has one 8-bit up-counter , two time constant registers

PWM timer (2 channels)
- Resolution :1/250
- Duty cycle can be set from 0 to 100%
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I2C bus interface ( one channel )
- Include single master mode and slave mode

Host interface ( HIF)
- 8-bit host interface port
- Three host interrupt requests ( HIRQ1,11,12)
- Regular and fast A20 gate output

Keyboard controller
- Controls a matrix-scan keyboard by providing a keyboard scan function with wake-up interrupts
- And sense ports

A/D converter
- 10-bit resolution
- 8 channels : single or scan mode (selectable )

D/A converter
- 8-bit resolution
- 2 channels

Interrupts
- Nine external interrupt lines : NMI# , IRQ0 to 7#
- 26 on-chip interrupt sources

Power-down modes
- Sleep mode
- Software standby mode
- Hardware standby mode
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A single chip microcomputer

On-chip flash memory

Maximum 64-kbyte address space

Support three PS/2 port for external keyboard ,mouse and internal track pad.

Support SMI,SCI trigger input:

Cover switch

Battery charging control

Smart Battery monitoring

Control D/D system on/off

Fan control and LED indicator serial interface

100pin TQFP

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1.2.8 Audio System
1.2.8.1 AC97 CODEC : ALC200 (or CS4299) -PQFP

AC ’97 2.1 Compatible

Industry Leading Mixed Signal Technology

20-bit Stereo Digital-to-Analog Converter and 18-bit Ste-reo Analog to Digital Converter with Sample

Rate Conversion

Four Analog Line-level Stereo Inputs for Connection from LINE IN, CD, VIDEO, and AUX

Two Analog Line-level Mono Inputs for Modem Sub-system and Internal PC Beeper

Mono Microphone Input Switchable from Two External Sources

High Quality Differential CD Input

Dual Stereo Line-level Outputs

Extensive Power Management Support

Meets or Exceeds Microsoft’s ® PC 98 and PC 99 Audio Performance Requirements

3D Stereo Enhancement

Sample Rate Converters

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combined with driver software and an AC’97 CODEC provides a complete high quality
audio solution,
Feature Include:
- MPU-401 interface
- FM synthesizer
- Game Port (disable in 7170 NB system)
- MIDI port. (disable in 7170 NB system)
- MODEM
- CD-ROM
- User-Defined GPIO
- Volume Control: Rotary VR
- Stereo BTL 2x1 W Amplifiers(TPA0202) With 8 Ohm Load.
- 16 Bit Stereo ADC & DAC For Record And Play Back
- Programmable Sample Rates From 4kHz To 44.1kHz For Record And Playback
- Microphone in * 1 (3.5 mm phone-jack)
- Headphone out * 1: stereo (3.5mm phone-jack) (disable in 7170 NB system)
- Built-in Speaker * 2 (1w, 8 ohm)
- Built-in Microphone * 1

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1.2.9 IR Module : HSDL-3600#007

Fully Compliant to IrDA 1.1 Specifications
- 115.2 kb/s to 4 Mb/s operation
- excellent nose-to-nose operation

Compatible with ASK, HP-SIR

IEC825-Class 1 Eye Safe

Wide Operating Voltage Range
- 2.7 V to 5.25 V

Small Module Size
- 4.0 x 12.2 x 5.1 mm (HxWxD)

Complete Shutdown
- TXD, RXD, PIN diode

Low Shutdown Current
- 10 nA typical

Adjustable Optical Power Management
- Adjustable LED drive-current to maintain link integrity

Single Rx Data Output
- FIR Select pin switch to FIR

Integrated EMI Shield
- Excellent noise immunity

Edge Detection Input
- Prevents the LED from long turn-on time

Interface to various Super I/O and Controller Devices

Designed to Accommodate Light Loss with Cosmetic Window

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1.2.10 Memory System

1.2.12.2 Main memory
SO-DIMM
- Two SO-DIMM sockets on Mother Board for expansion
- Supports JEDEC specification : 144 SO-DIMM socket
- Supports 3.3V PC100/PC133 SDRAM DIMM
- 2 banks on each socket

The memory subsystem supports two 3.3V 144-pin SO-DIMM sockets for totally up to 512MB of Main memory.
Here are some main memory system essential characteristics:
144-pin SO DIMM socket 2
Memory Voltage 3.3V ± 10%
Memory Module Type 64MB/128MB/256MB
Banks on DIMM 4
Bank Ordering Auto ordering by BIOS
Memory type selection Auto-detect by BIOS
Mixed type DRAM support Yes

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1.2.11 Mass Storage Sub-system

7170NB system is an two spindles NB. There are one removable 2.5" hard disk drive and 24X CD-ROM or
DVD or CDRW installed in it. This IDE interface is compliant with ATA specification and UltraDMA 33/66MB.

1.2.12 I/O Interface

- One standard parallel port with Output only/Bi-direction/ECP/EPP functions
- One serial ports, for FIR/MIR/SIR/SHARP ASK
COM port assignment COM2: IR / RS-232 / Disable
- One external CRT connector for CRT display
- One PS/2 interface for external KB, mouse or other PS2 devices
- One CARDBUS sockets support type II.
- Two USB V1.1 connector
- One DC Jack for Adapt in
- One MODEM RJ-11 phone jack for PSTN line and one RJ-45 for 10/100 base LAN.
- Dual stereo line level speaker outputs
- Microphone input and one internal microphone.
- Tunable volume by variable resistor
- One Mini-PCI socket support Type IIIA.

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1.2.13 Special Feature Function2
1.2.13.1. Hot Key Function
Keys Combination Feature Meaning

Fn + F5 Display switch Rotate display mode in LCD only, CRT only and
simultaneously display and TV output.
Fn + F6 Brightness down Decreases the LCD brightness
Fn + F7 Brightness up Increase the LCD brightness
Fn + F8 Contrast down Decrease the LCD contrast
Fn + F9 Contrast up Increase the LCD contrast
Fn + F10 Enable/Disable battery Toggle battery low beep warming on/off
warming beep
Fn + F11 Panel on/off Toggle Display ( panel , CRT,TV ) On/Off
Fn + F12 Suspend to Dram/HDD Force the computer into either suspend to HDD or
suspend to DRAM mode depending on BIOS setup

1.2.13.2. Flash ROM (BIOS)

7170 NB system utilizes the state-of-the-art Flash EEPROM technology. User can upgrade the system BIOS in
the future just running the program from MiTAC.

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1.2.13.3. LED Indicators
System has nine status LED indicators to display system activity which include below LCD panel unit and above
keyboard:

1. Three LED indicators below LCD panel unit:

From left to right that indicate AC POWER, BATTERY POWER and BATTERY STATUS

• AC POWER: This LED lights green when the notebook is being powered by AC, and flash (on 1 second, off
1 second ) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or
powered by batteries, or when Suspend to Disk.
• BATTERY POWER: This LED lights green when the notebook is being powered by batteries, and flashes
(on 1 second, off 1 second ) when Suspend to DRAM is active using battery power. The LED is off when the
notebook is off or powered by AC, or when Suspend to Disk.
• BATTERY STATUS : During normal operation, this LED stays off as long as the battery is charged. When
the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second.
When AC is connected, this indicator glows green if the battery pack is fully charged, or orange (amber) if the
battery is being charged.
• Five LED indicators in front of palm rest:
From left to right that indicates CD-ROM/MO, HARD DISK DRIVE, , NUM LOCK, CAPS LOCK and
SCROLL LOCK.
• Email/ Blue-Tooth LED indicators in front of palm rest:
The left side green LED flashing means new mail coming. Otherwise the LED is always OFF. The right side
red LED ON means Blue-Tooth module turn ON.

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 7170 N/B MAINTENANCE

1.3 System Power Management

1.3.1 System Management Mode
7170NB system has built in several power saving modes to prolong the battery usage for mobile purpose. User can
enable and configure different degrees of power management modes via ROM CMOS setup ( booting by pressing F2
key). Following are the descriptions of the SMM and power management modes supported.
1.3.1.1. Full-On Mode
In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.

1.3.1.2. Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology will be clock throttling.
This can save battery power without loosing much computing capability.
The CPU power consumption and temperature is lowered in this mode.

1.3.1.3. Standby Mode

For more power saving, it turns of f the peripheral component. In this mode, the following is the status of each
device.
- CPU : stop grant
- VGA: software suspend
- LCD : backlight off
- HDD: spin down
- FDD : standby
- FDD : standby

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 7170 N/B MAINTENANCE
1.3.1.4. Suspend Mode
The most chipsets of the system is entering power down mode for more power saving.
Suspend to RAM :
CPU: off
N.B: off
S.B: partial off
VGA: Suspend
PCMCIA: Standby
Audio: off
Suspend to HDD :
All devices are stopped clock and power-off, only EC is lived if battery or ac still plug in .At this time ,
system status is saved in HDD. All system status will be restored when toggle power button system powered on
again.

1.3.1.5. Other Power Management Functions

1.3.1.5.1. HDD & Video access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU
state depending on the application. When the VGA activity monitoring is enabled, the performance of the
system will have some impact.
1.3.1.5.2. Cover Switch
System automatically provides power saving on monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover . There are three functions to be chosen.

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 7170 N/B MAINTENANCE

1.3.2 Other Power Management Functions

1.3.2.1. HDD & Video access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU
state depending on the application. When the VGA activity monitoring is enabled, the performance of the
system will have some impact.
1.3.2.2. Cover Switch
System automatically provides power saving on monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover . There are three functions to be chosen.
1. Switch to CRT
2. Panel Off
3. Suspend --- Depend on BIOS setting ( STR or STD)
1.3.2.3. Battery Warning
System also provides battery capacity monitoring and gives user a warning so that users have chance to save
their data before battery dead. Also , this function protects system from mal-function while battery capacity is low.
1.3.2.4. Battery Warning State
7170 NB system provides battery management function and gives warning while battery is in It’s low power
state. When the battery capacity is below 9% (Battery Warning State), system will generate beep for every 4
seconds (System beeps only if BIOS setup enable Battery Warning Beeping). When hearing the beeping, it is
recommended that user should plug in AC adapter to get power from external source, or stop working and
save his data file to prevent disastrous results.
1.3.2.5. Battery Dead State
W hen the battery voltage level reach 11 volts, system will shut down automatically in order to extend the
battery packs' life.

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 7170 N/B MAINTENANCE

1.3.3. Fan Power on/off Management

The fan is always on except suspend power off to cool the CPU temperature down.

1.4 Firmware - System BIOS & Keyboard BIOS

7170NB use Phoenix BIOS as the system firmware and keyboard firmware .For further detail information regarding
the firmware , please refer to 7170NB software document.
(refer software engineer spec)

1.4.1 SYSTEM RESOURCE

1.4.1.1 PCI INT MAP
INT DEVICE
INTA CARDBUS
INTB (VGA in North Bridge)
INTC MINI PCI
INTD USB/ MINI PCI(REV)
1394/ LAN

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1.4.1.2 PCI BUS MASTER REQUEST
REQ DEVICE
REQ0 CARDBUS
REQ1 No Used
REQ2 VGA (in North Bridge)
REQ3 MINI PCI
REQ4 LAN

1.4.1.3 IDSEL
AD BUS DEVICE
AD11 VGA (in North Bridge)
AD17 MINI PCI
AD21 CARDBUS
AD28 South Bridge
AD29 LAN

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 7170 N/B MAINTENANCE

1.5 Peripheral Component

1.5.1 LCD
UNIPAC UB133X01-2 TFT XGA
- pixels : 1024(H) By 768(V)
- screen size : 13.3inch
- colors : 262k(3x6 bit)
- interface : LVDS single cannel
- lump : CCFL
- D/C for panel : 3.3V
- Power Consumption : 3.66W(typ)
- Weight : 500g (typ)
- Lamp starting voltage : 925 Vrms (typ)

1.5.2 Internal Keyboard

IBM 106 key compatible keyboard layout
Key pitch : 19mm
Length : 300mm
Thickness : 5.3mm
Keycap pull off force : >= 800g
MAX. keytop depressing force :
~To withstand 5 Kgf at the center of keytop for 1 minute.
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 7170 N/B MAINTENANCE
Keytop Strength :
~To withstand 1Kgf at X and Y directions for 5 sec.
Power Requirement :
~The keyswitch shall require DC 6V at 0.3 mA maximum.
Contact Resistance :
~ The contact resistance is 500 ohm maximum at 200g force.
Operating Temperature : -10 to 60 degree C
High Temperature Storage : 65 degree C.
Window95 applied

1.5.3 Floppy Disk Drive

- Please use external USB Floppy Disk Device.

1.5.4 Touch Pad

Synaptics (4 buttons):
- Model TM41P-350
- Vcc : 5V +- 0.5
- Icc(max) : 4 mA
- Interface : PS/2
- X/Y position resolution : 1000 points/inch
- Dimension : 65mm x 49mm x 4.6mm

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 7170 N/B MAINTENANCE
- Effective area : 60mm x 44 mm
- Operating Temp. : 0 - 60 degree C
- Storage Humidity : 5 - 95 %,
- Storage Temp. : -40 - + 65 degree C
- ESD : 15KV applied to front surface

1.5.5 CD-ROM or DVD-ROM or CD-RW Drive

- Disk speed: X24/higher speed CD-ROM or X8 speed DVD-ROM or CD-RW.
- Host interface: IDE/ATAPI
- Ejection: Manual eject using the eject button/Automatically eject using the tray

1.5.6 HDD
- Support Ultra DMA
- 2.5” , 8.45/9.5 mm height
- Formatted Storage Capacity 10/20 GB

1.5.7 LED Indicators

Upper LEDs on D/D board
- AC. POWER, BATTERY POWER, CHARGER STATUS,
Lower LEDs on M/B board
- HARD DISK DRIVE, CD-ROM, NUM LOCK, CAPS LOCK, SCROLL LOCK and Emial/Blue-tooth status..

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 7170 N/B MAINTENANCE

1.5.8 IR port
- HSDL-3600#007 IR Module
- Meet IrDA Physical Layer Specification
- 1 cm to 1 Meter Operating Distance
- 30 degree Viewing Angle (± 15 degree )
- Support Two Channels - 2.4 Kb/s to 115.2Kb/s and 1.15Mb/s to 4.0 Mb/s

1.5.9 CMOS Battery

- VARTA CR2032 non-chargeable lithium battery
- Put in battery holder, can be replaced
- Nominal voltage : 3V
- Nominal capacity : 65mAh
- Recommended continuous Drain : 0.2 mA
- Recommended Pulse Drain : 12 mA
- Weight : 3.2 g

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2. System Assembly & Disassembly

2.1 System View

2.1.1 Front View

Stereo Speaker Set
 Device Indicators
 Mail-Received Button/Indicator
 Microphone Connector
 Audio Input Connector
 Audio Output Connector
 Volume Control
 Top Cover Latch

2.1.2 Left-Side View

Kensington Lock
 Ventilation Openings
 RJ-45 Connector
 PC Card Slot
 Hard Disk Drive

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2. System Assembly & Disassembly

2.1.3 Right-Side View

Battery Pack
 CD-ROM/DVD-ROM Drive
 IR Port

2.1.4 Rear View

Power Connector
 S-Video Output Connector
 Parallel Port
 PS/2 Port
 IEEE 1394 Port
 RJ-11 Connector
 USB Ports
 VGA Port
Ventilation Openings

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2. System Assembly & Disassembly

2.1.5 Top-Open View

LCD Screen
 Ventilation Openings
 Microphone
 Keyboard
 Touchpad
 Power Button
 Easy Start Buttons
 Battery Charge Indicator
Battery Power Indicator

AC Power Indicator

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 7170 N/B MAINTENANCE
2. System Assembly & Disassembly
2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.

2.2.1 Battery Pack

2.2.2 Keyboard
Modular Components 2.2.3 CPU
2.2.4 HDD Module
2.2.5 CD/DVD-ROM Drive
2.2.6 SO-DIMM

NOTEBOOK 2.2.7 Mini-PCI Card

2.2.8 LCD Assembly
LCD Assembly Components 2.2.9 LCD Panel
2.2.10 Inverter Board
2.2.11 System Board
Base Unit Components
2.2.12 Touchpad
2.2.13 Modem Card
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 7170 N/B MAINTENANCE
2. System Assembly & Disassembly

2.2.1 Battery Pack

Disassembly
1. Carefully put the notebook upside down.
2. Slide the release lever to the “unlock” ( ) position (
), then slide and hold the release lever outwards and
pull the battery pack out of the compartment (). (Figure 2-1)

Figure 2-1

Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected
when you hear a clicking sound.
2. Slide the release lever to the “lock” ( ) position.

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2. System Assembly & Disassembly

2.2.2 Keyboard
Disassembly
1. Open the top cover. Install a small rod, such as a straightened paper clip, into the eject hole near the power
connector of the notebook. (Figure 2-2)

Figure 2-2 Figure 2-3

2. Push the rod firmly and slide the LED panel to the left (
). Then lift the LED panel up from the left side ().
(Figure 2-3)

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2. System Assembly & Disassembly

3. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-4)

Figure 2-4

Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Replace the LED panel.

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2. System Assembly & Disassembly

2.2.3 CPU
Disassembly
1. Remove the LED panel and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly.)
2. Remove four screws fastening the heatsink and disconnect the fan’s power cord to free the heatsink from the CPU
module. (Figure 2-5)

• Figure 2-5 Figure 2-6

3. Insert a minus screwdriver 101 (JIS standard) into the “OPEN” hole of the socket, and push the screwdriver
toward the CPU to free the CPU. Now you can take out the CPU from the socket. (Figure 2-6)

Reassembly
1. Align the arrowhead corner of the CPU with the beveled corner of the socket, and insert the CPU pins
into the holes. Insert the flat screwdriver into the “CLOSE” hole of the socket, and push the screwdriver
toward the CPU to secure the CPU in place.
2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU
and secure with four screws.
3. Replace the keyboard and LED panel.
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2. System Assembly & Disassembly

2.2.4 HDD Module

Disassembly
1. Carefully put the notebook upside down.
2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-7)

Figure 2-7 Figure 2-8

3. Remove five screws to separate the hard disk drive from the metal shield. (Figure 2-8)

Reassembly
1. To install the hard disk drive, place it in the bracket and secure with five screws.
2. Slide the HDD module into the compartment and secure with one screw.

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2. System Assembly & Disassembly

2.2.5 CD/DVD-ROM Drive

Disassembly
1. Remove the LED panel and keyboard. (See section 2.2.2 Disassembly.)
2. Remove two screws locking the CD/DVD-ROM drive. (Figure 2-9)

Figure 2-9 Figure 2-10

3. Use the screwdriver to push the metal pad to the right and the CD/DVD-ROM drive will pop out. Hold the
CD/DVD-ROM drive and slide it outwards carefully. (Figure 2-10)

Reassembly
1. Push the CD/DVD-ROM drive into the compartment.
2. Secure the CD/DVD-ROM drive with two screws.
3. Replace the keyboard and LED panel.
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2. System Assembly & Disassembly

2.2.6 SO-DIMM
Disassembly
1. Carefully put the notebook upside down.
2. Remove three screws to access the SO-DIMM socket.
3. Pull the retaining clips outwards (
) and remove the SO-DIMM (). (Figure 2-11)

Figure 2-11

Reassembly
1. To install the SO-DIMM, match the SO-DIMM's notched part with the socket's projected part
and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the
retaining clips lock the SO-DIMM into position.
2. Replace three screws to lock the SO-DIMM socket cover.
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2. System Assembly & Disassembly

2.2.7 Mini PCI Card

Disassembly
1. Carefully put the notebook upside down.
2. Remove three screws to access the Mini PCI socket.
3. Pull the retaining clips outwards and remove the Mini PCI card. (Figure 2-12)

Figure 2-12

Reassembly
1. To install the Mini PCI card, match the notched part of the Mini PCI card with the socket's projected part
and firmly insert the Mini PCI card into the socket at 20-degree angle. Then push down until the
retaining clips lock the Mini PCI card into position.
2. Replace three screws to lock the SO-DIMM socket cover.

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2. System Assembly & Disassembly

2.2.8 LCD Assembly

Disassembly
1. Carefully put the notebook upside down and remove three screws to access the Mini PCI socket.
2. Disconnect the antenna from the connector on the Mini PCI socket. (Figure 2-13)

Figure 2-13 Figure 2-14

3. Open the top cover. Remove the LED panel, keyboard, and heatsink . (See section 2.2.2 and 2.2.3
Disassembly.)
4. Pull out the antenna from the CPU compartment.
5. Remove the two hinge covers. (Figure 2-14)

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 7170 N/B MAINTENANCE
2. System Assembly & Disassembly

6. Disconnect the LCD cable from the system board, and remove four screws of the hinges. Now you can separate
the LCD assembly from the base unit. (Figure 2-15)

Figure 2-15

Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws on the hinges.
2. Reconnect the antenna to the connector on the Mini PCI socket.
3. Reconnect the LCD cable to the system board.
4. Replace the heatsink, keyboard and LED panel.two hinge covers.
5. Replace two hinge covers.

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2. System Assembly & Disassembly

2.2.9 LCD Panel

Disassembly
1. Remove the LCD assembly. (See section 2.2.8 Disassembly.)
2. Remove the four rubber pads and four screws on the corners of the panel. (Figure 2-16)

Figure 2-16 Figure 2-17

3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out.
Repeat the process until the frame is completely separated from the housing.
4. Remove the two screws on two sides and two screws on the lower part of of the LCD panel, and disconnect the
cable from the inverter board. (Figure 2-17)

Reassembly
1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board.
2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads.
3. Replace the LCD assembly. (See section 2.2.8 Reassembly.)
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2. System Assembly & Disassembly

2.2.10 Inverter Board

Disassembly
1. Remove the LCD assembly and detach the LCD frame (see instructions in previous two sections).
2. To remove the inverter board on the bottom of the LCD assembly, disconnect the cable and
remove one screw. (Figure 2-18)

Figure 2-18

Reassembly
1. Fit the inverter board back into place and secure with one screw.
2. Reconnect the cable.
3. Replace the LCD frame. (See section 2.2.9 Reassembly.)
4. Replace the LCD assembly. (See section 2.2.8 Reassembly.)

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2. System Assembly & Disassembly

2.2.11 System Board

Disassembly
1. Remove the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
(See the Disassembly parts in previous sections.)
2. Remove thirteen screws on the bottom of the notebook. (Figure 2-19)

Figure 2-19 Figure 2-20

3. Remove the speaker assembly from the notebook. (Figure 2-20)

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 7170 N/B MAINTENANCE
2. System Assembly & Disassembly

4. Remove two screws on the rear side of the notebook. Then remove three screws fastening the base unit cover and
one screw in the CPU compartment. (Figure 2-21)

Figure 2-21 Figure 2-22

5. Remove two screws fastening the LED board. (Figure 2-22)

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2. System Assembly & Disassembly

6. Lift up the base unit cover and disconnect the touchpad cable. (Figure 2-23)

Figure 2-23 Figure 2-24

7. Remove three screws from the base. (Figure 2-24)

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2. System Assembly & Disassembly

8. Disconnect two cables from the system board and lift up the base unit to access the system board. (Figure 2-25)

Figure 2-25

Reassembly
1. Reconnect two cables to the system board.
2. Replace three screws fastening the base unit.
3. Reconnect the touchpad cable and replace the base unit cover.
4. Replace two screws fastening the LED board.
5. Replace one screw in the CPU compartment and three screws fastening the base unit cover.
5. Replace two screws on the rear side of the notebook.
6. Replace the speaker assembly.
7. Replace thirteen screws on the bottom of the notebook.
8. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
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2. System Assembly & Disassembly

2.2.12 Touchpad
Disassembly
1. Remove the base unit cover. (See steps 1-6 in section 2.2.11 Disassembly.)
2. Remove the six screws to lift up the touchpad holder and touchpad panel. (Figure 2-26)

Figure 2-26

Reassembly
1. Replace the touchpad holder and touchpad panel, and secure with six screws.
2. Assemble the notebook. (See section 2.2.11 Reassembly.)

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2. System Assembly & Disassembly

2.2.13 Modem Card

Disassembly
1. Disassemble the notebook to access the system board. (See section 2.2.11 Disassembly.)
2. Remove the two screws fastening the modem card. (Figure 2-27)

Figure 2-27 Figure 2-28

3. Disconnect the cable from the modem card. (Figure 2-28)

Reassembly
1. Reconnect the cable to the modem card and secure the modem card with two screws.
2. Assemble the notebook. (See section 2.2.11 Reassembly.)

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 7170 N/B MAINTENANCE
3. Definition & Location Connectors / Switches Setting
3.1 7170 Main Board ( Side A-1 )
J4 J26, J27 J2 J3 J1

J1 : PS2 Connector. ( SH17 )
J8 J10
J6
J2 : RJ11 Phone Jack. ( SH18 )
J9 J7

J3 : IEEE 1394 Connector. ( SH14 )

J4 : External VGA Connector. ( SH9 )

J6 : Modem Daughter Board To RJ11 Connector. ( SH18 )

J11
J7 : Main Board To DC Power Board Connector. ( SH22 )
J12

J8 : LCD Panel Module Connector. ( SH9 )
SW1

J9 : Easy Start Button Connector. ( SH17 )
J15 J13

J10 : Main Board To DC Power Board Connector. ( SH22 )

J509
J11 : RJ45 LAN Connector. ( SH18 )

J14

J12 : CPU FAN Connector. ( SH17 )
J20
J18 J16
J13 : CD-
CD-ROM Device Connector. ( SH12 )

J14 : PCMCIA Card Bus Connector. ( SH14 )

J17
J30
J15 : Internal Keyboard Connector. ( SH17 )

J21 SW4
J22
SW3
J23 J24 J25 VR1
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 7170 N/B MAINTENANCE
3. Definition & Location Connectors / Switches Setting
3.1 7170 Main Board ( Side A-2 )
J4 J26, J27 J2 J3 J1

J16 : Battery Connector. ( SH21 )

J8 J10
J6
J17 : Touch Pad Connector. ( SH15 )
J9 J7

J18 : Modem Daughter Board AC-
AC-Link Connector. ( SH18 )

J20 : Hard Disk Connector. ( SH12 )

J21,J22 : L,R Internal Speaker Connector. ( SH13 )

J11
J23 : External Micro Phone Jack. ( SH13 )
J12

J24 : Line In. ( SH13 )

SW1

J25 : Line Out Phone Jack. ( SH13 )
J15 J13

J26,J27 : USB Port Connector. ( SH15 )

J509
J30 : Internal Micro Phone Jack. ( SH13 )

J14

VR1 : Volume Control. ( SH13 )
J20
J18 J16
SW1 : Panel Type Select. ( SH6 )

SW3 : E-
E-Mail Button. ( SH17 )
J17
J30
SW4 : Cover Switch. ( SH17 )

J21 SW4
J22
SW3
J23 J24 J25 VR1
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 7170 N/B MAINTENANCE
3. Definition & Location Connectors / Switches Setting
3.1 7170 Main Board ( Side B )

J501 : 144 Pin SO-
SO-DIMM Extension Memory Socket. ( SH8 )

J502 : 144 Pin SO-

SO-DIMM Extension Memory Socket. ( SH8 )

J503 : QTC Connector. ( SH19 )

J505 : RTC Battery Connector. ( SH12 )

VGA Connect. RJ11. Parallel Port Power Jack

PS/2 Connect. TV OUT.

J502 J501

USB Port
J505
J503
IEEE 1394
Connect.

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3. Definition & Location Connectors / Switches Setting
3.2 7170 DC Power Board ( Side A )

J1 J4
J5

PJ2

J1 : Parallel Port Connector. ( SH3 )
J3
PJ1
J3 : Inverter Board Connector. ( SH2 )

J4 : Power Jack Board Connector. ( SH2 )

J5 : TV Out Connector. ( SH3 )

PJ1 : DC Power Board To Main Board Connector. ( SH2 )

PJ2 : DC Power Board To Main Board Connector. ( SH2 )

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3. Definition & Location Connectors / Switches Setting

3.3 7170 ESB Board ( Side A,B )

J501 : Easy Start Button Connector.
SW1 SW2 SW3 SW4 SW5 SW6

SW1 : Programmable Easy Start Button Switch.

SW2 : Programmable Easy Start Button Switch.

J501

SW3 : Programmable Easy Start Button Switch.

SW4 : Programmable Easy Start Button Switch.

SW5 : Programmable Easy Start Button Switch.

SW6 : Programmable Easy Start Button Power Switch.

3.4 7170 Touch Pad Board ( Side A,B )

J501 : Touch Pad Board To Touch Pad Connector.

J502 : Touch Pad Board To Main Board Connector.

J1
SW1 : Scroll Up Button Switch.

SW2 : Left Button Switch.

J501
SW2 SW1 SW3
SW3 : Right Button Switch.
J502

SW4 : Scroll Down Button Switch.
SW4

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 7170 N/B MAINTENANCE
4. Definition & Location Major Components
4.1 7170 Main Board ( Side A )

U1 : PIII/Celeron
PIII/Celeron FC-
FC-PGA 370-
370-Pin Socket. ( SH4 )

U2 : GL528SM Thermal Recorder. ( SH4 )

U1

U6 : 93C468 Serial EEPROM. ( SH11 )

U8 : 28F020-
28F020-PLCC Flash ROM BIOS. ( SH15)
U2

U10 : NM24C02N. ( SH14 )

U12 : VT8231 South Bridge. ( SH10 )

U25
PU4

U16 : ALC200 Audio Codec.
Codec. ( SH13 )

U18 : TPA0202 Audio Amplifier. ( SH13 )

U21
U19 : 74VHV164. ( SH9 )
J509 U8
U21 : PCI 4410GHK PCMCIA Card Bus Controller. ( SH14 )
U10
U6

U25 : LSI 80227. ( SH18 )
U12

PU4 : SC 1401CSS. ( SH20 )

U16 U18
U19

70
 7170 N/B MAINTENANCE
4. Definition & Location Major Components
4.1 7170 Main Board ( Side B )

U500 : TSB 41AB1 1394 PHY. ( SH14 )

U501 : TWINSTER North Bridge. ( SH6 )

?U
U500 U511

U502 : H8/34347 Micro Controller. ( SH17 )

U503 : ICS9248-
ICS9248-195 Clock Generator. ( SH16 )
PU501
PU500
U505 : SN74CBTD3384 Level Shift. ( SH17)
PU502

U511 : CH7005C TV Encoder. ( SH9 )
PU504
U501
U1

PU504 : MAX1717. ( SH20 )
?U
U2

PU6 : TL594C PWM. ( SH22 )

U3
U5?

U4
U502
PU508 U503 J502 J501
U505

J505
J503
? U508

71
 7170 N/B MAINTENANCE
5. Pin Descriptions Of Major Components
5.1 Pentium III/Celeron µPGA2 CPU-1
Alphabetical Signal Reference
Signal Name I/O Signal Description Signal Name I/O Signal Description
A[35:3]# I/O The A[35:3]# (Address) signals define a 2 36 -byte physical memory BERR# I/O The BERR# (Bus Error) signal is asserted to indicate an
GTL+ address space. When ADS# is active, these signals transmit the GTL+ unrecoverable error without a bus protocol violation. It may be driven
address of a transaction; when ADS# is inactive, these signals by either system bus agent and must be connected to the appropriate
transmit transaction information. These signals must be connected to pins/balls of both agents, if used. However, the mobile Pentium III
the appropriate pins/balls of both agents on the system bus. The processors do not observe assertions of the BERR# signal.
A[35:24]# signals are protected with the AP1# parity signal, BERR# assertion conditions are defined by the system configuration.
and the A[23:3]# signals are protected with the AP0# parity signal. Configuration options enable the BERR# driver as follows:
On the active-to-inactive transition of RESET#, each processor bus • Enabled or disabled
agent samples A[35:3]# signals to determine its power-on • Asserted optionally for internal errors along with IERR#
configuration. See Section 4 of this document and the PentiumII • Asserted optionally by the request initiator of a bus transaction after
Processor Developer’s Manual for details. it observes an error
A20M# I If the A20M# (Address-20 Mask) input signal is asserted, the • Asserted by any bus agent when it observes an error in a bus
1.5V processor masks physical address bit 20 (A20#) before looking up a transaction
Tolerant line in any internal cache and before driving a read/write transaction BINIT# I/O- The BINIT# (Bus Initialization) signal may be observed and driven
on the bus. Asserting A20M# emulates the 8086 processor's address GTL+ by both system bus agents and must be connected to the appropriate
wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only pins/balls of both agents, if used. If the BINIT# driver is enabled
supported in Real mode. during the power-on configuration, BINIT# is asserted to signal any
ADS# I/O The ADS# (Address Strobe) signal is asserted to indicate the validity bus condition that prevents reliable future information.
GTL+ of a transaction address on the A[35:3]# signals. Both bus agents If BINIT# is enabled during power-on configuration, and BINIT# is
observe the ADS# activation to begin parity checking, protocol sampled asserted, all bus state machines are reset and any data which
checking, address decode, internal snoop or deferred reply ID match was in transit is lost. All agents reset their rotating ID for bus
operations associated with the new transaction. This signal must be arbitration to the state after reset, and internal count information is
connected to the appropriate pins/balls on both agents on the system lost. The L1 and L2 caches are not affected.
bus. If BINIT# is disabled during power-on configuration, a central agent
AERR# I/O The AERR# (Address Parity Error) signal is observed and driven by may handle an assertion of BINIT# as appropriate to the Machine
GTL+ both system bus agents, and if used, must be connected to the Check Architecture (MCA) of the system.
appropriate pins/balls of both agents on the system bus. AERR# BNR# I/O- The BNR# (Block Next Request) signal is used to assert a bus stall by
observation is optionally enabled during power-on configuration; if GTL+ any bus agent that is unable to accept new bus transactions. During a
enabled, a valid assertion of AERR# aborts the current transaction. bus stall, the current bus owner cannot issue any new transactions.
If AERR# observation is disabled during power-on configuration, a Since multiple agents may need to request a bus stall simultaneously,
central agent may handle an assertion of AERR# as appropriate to the BNR# is a wired-OR signal that must be connected to the appropriate
error handling architecture of the system. pins/balls of both agents on the system bus. In order to avoid wire-OR
AP[1:0]# I/O The AP[1:0]# (Address Parity) signals are driven by the request glitches associated with simultaneous edge transitions driven by
GTL+ initiator along with ADS#, A[35:3]#, REQ[4:0]# and RP#. AP1# multiple drivers, BNR# is activated on specific clock edges and
covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is sampled on specific clock edges.
high if an even number of covered signals are low and low if an odd BP[3:2]# I/O The BP[3:2]# (Breakpoint) signals are the System Support group
number of covered signals are low. This allows parity to be high when GTL+ Breakpoint signals. They are outputs from the processor that indicate
all the covered signals are high. AP[1:0]# should be connected to the the status of breakpoints.
appropriate pins/balls on both agents on the system bus. BPM[1:0]# I/O The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and
BCLK I The BCLK (Bus Clock) signal determines the system bus frequency. GTL+ performance monitor signals. They are outputs from the processor
2.5V Both system bus agents must receive this signal to drive their outputs that indicate the status of breakpoints and programmable counters
Tolerant and latch their inputs on the BCLK rising edge. All external timing used for monitoring processor performance.
parameters are specified with respect to the BCLK signal.
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5.1 Pentium III/Celeron µPGA2 CPU-2

Alphabetical Signal Reference

Signal Name I/O Signal Description Signal Name I/O Signal Description
BPRI# I The BPRI# (Bus Priority Request) signal is used to arbitrate for DBSY# I/O- The DBSY# (Data Bus Busy) signal is asserted by the agent
GTL+ ownership of the system bus. It must be connected to the appropriate GTL+ responsible for driving data on the system bus to indicate that the data
pins/balls on both agents on the system bus. Observing BPRI# active bus is in use. The data bus is released after DBSY# is deasserted. This
(as asserted by the priority agent) causes the processor to stop issuing signal must be connected to the appropriate pins/balls on both agents
new requests, unless such requests are part of an ongoing locked on the system bus.
operation. The priority agent keeps BPRI# asserted until all of its DEFER# I The DEFER# (Defer) signal is asserted by an agent to indicate that
requests are completed and then releases the bus by deasserting GTL+ the transaction cannot be guaranteed in-order completion. Assertion
BPRI#. of DEFER# is normally the responsibility of the addressed memory
BREQ0# I/O The BREQ0# (Bus Request) signal is a processor Arbitration Bus agent or I/O agent. This signal must be connected to the appropriate
GTL+ signal. The processor indicates that it wants ownership of the system pins/balls on both agents on the system bus.
bus by asserting the BREQ0# signal. DEP[7:0]# I/O The DEP[7:0]# (Data Bus ECC Protection) signals provide optional
During power-up configuration, the central agent must assert the GTL+ ECC protection for the data bus. They are driven by the agent
BREQ0# bus signal. The processor samples BREQ0# on the active- responsible for driving D[63:0]#, and must be connected to the
to-inactive transition of RESET#. appropriate pins/balls on both agents on the system bus if they are
BSEL[1:0] I The BSEL[1:0] (Select Processor System Bus Speed) signal is used to used. During power-on configuration, DEP[7:0]# signals can be
1.5V configure the processor for the system bus frequency. Table 38 shows enabled for ECC checking or disabled for no checking.
Tolerant the encoding scheme for BSEL[1:0]. The only supported system bus DRDY# I/O The DRDY# (Data Ready) signal is asserted by the data driver on
frequency for the mobile Pentium III processor is 100 MHz. If GTL+ each data transfer, indicating valid data on the data bus. In a multi-
another frequency is used or if the BSEL[1:0] signals are not driven cycle data transfer, DRDY# can be deasserted to insert idle clocks.
with "1" then the processor is not guaranteed to function properly. This signal must be connected to the appropriate pins/balls on both
BSEL[1:0] Encoding agents on the system bus.
BSEL[1:0] System Bus Frequency EDGCTRLP Analog The EDGCTRLP (Edge Rate Control) signal is used to configure the
00 66 MHz edge rate of the GTL+ output buffers. Connect the signal to VSS with
01 100 MHz a 110-Ω, 1% resistor.
10 Reserved FERR# O The FERR# (Floating-point Error) signal is asserted when the
11 133 MHz 1.5V processor detects an unmasked floating-point error. FERR# is similar
CLKREF Analog The CLKREF (System Bus Clock Reference) signal provides a Tolerant to the ERROR# signal on the Intel 387 coprocessor, and it is included
reference voltage to define the trip point for the BCLK signal. This Open- for compatibility with systems using DOS-type floating-point error
signal should be connected to a resistor divider to generate 1.25V drain) reporting.
from the 2.5-V supply. FLUSH# I When the FLUSH# (Flush) input signal is asserted, the processor
CMOSREF Analog The CMOSREF (CMOS Reference Voltage) signal provides a DC 1.5V writes back all internal cache lines in the Modified state and
level reference voltage for the CMOS input buffers. A voltage divider Tolerant invalidates all internal cache lines. At the completion of a flush
should be used to divide a stable voltage plane (e.g., 2.5V or 3.3V). operation, the processor issues a Flush Acknowledge transaction. The
This signal must be provided with a DC voltage that meets the processor stops caching any new data while the FLUSH# signal
VCMOSREF specification from Table 13. remains asserted.
D[63:0]# I/O The D[63:0]# (Data) signals are the data signals. These signals On the active-to-inactive transition of RESET#, each processor bus
GTL+ provide a 64-bit data path between both system bus agents, and must agent samples FLUSH# to determine its power-on configuration.
be connected to the appropriate pins/balls on both agents. The data
driver asserts DRDY# to indicate a valid data transfer.

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5.1 Pentium III/Celeron µPGA2 CPU-3

Alphabetical Signal Reference

Signal Name I/O Signal Description Signal Name I/O Signal Description
GHI# I The GHI# signal controls which operating mode bus ratio is selected INTR I The INTR (Interrupt) signal indicates that an external interrupt has
1.5V in a mobile Pentium III processor featuring Intel SpeedStep 1.5V been generated. INTR becomes the LINT0 signal when the APIC is
Tolerant technology. On the processor featuring Intel SpeedStep technology, Tolerant enabled. The interrupt is maskable using the IF bit in the EFLAGS
this signal is latched when BCLK restarts in Deep Sleep state and register. If the IF bit is set, the processor vectors to the interrupt
determines which of two bus ratios is selected for operation. This handler after completing the current instruction execution. Upon
signal is ignored when the processor is not in the Deep Sleep state. recognizing the interrupt request, the processor issues a single
This signal is a "Don't Care" on processors that do not feature Intel Interrupt Acknowledge (INTA) bus transaction. INTR must remain
SpeedStep technology. This signal has an on-die pull-up to VccT and active until the INTA bus transaction to guarantee its recognition.
should be driven with an Open-drain driver with no external pull-up. LINT[1:0] I The LINT[1:0] (Local APIC Interrupt) signals must be connected to
HIT#, HITM# I/O The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey 1.5V the appropriate pins/balls of all APIC bus agents, including the
GTL+ transaction snoop operation results, and must be connected to the Tolerant processor and the system logic or I/O APIC component. When APIC
appropriate pins/balls on both agents on the system bus. is disabled, the LINT0 signal becomes INTR, a maskable interrupt
Either bus agent can assert both HIT# and HITM# together to indicate request signal, and LINT1 becomes NMI, a non-maskable interrupt.
that it requires a snoop stall, which can be continued by reasserting INTR and NMI are backward compatible with the same signals for
HIT# and HITM# together. the Pentium processor. Both signals are asynchronous inputs.
IERR# O The IERR# (Internal Error) signal is asserted by the processor as the Both of these signals must be software configured by programming
1.5V result of an internal error.Assertion of IERR# is usually accompanied the APIC register space to be used either as NMI/INTR or LINT[1:0]
Tolerant by a SHUTDOWN transaction on the system bus. in the BIOS. If the APIC is enabled at reset, then LINT[1:0] is the
Open- This transaction may optionally be converted to an external error default configuration.
drain signal (e.g., NMI) by system logic. The processor will keep IERR# LOCK# I/O The LOCK# (Lock) signal indicates to the system that a sequence of
asserted until it is handled in software or with the assertion of GTL+ transactions must occur atomically. This signal must be connected to
RESET#, BINIT, or INIT#. the appropriate pins/balls on both agents on the system bus. For a
IGNNE# I The IGNNE# (Ignore Numeric Error) signal is asserted to force the locked sequence of transactions, LOCK# is asserted from the
1.5V processor to ignore a numeric error and continue to execute non- beginning of the first transaction through the end of the last
Tolerant control floating-point instructions. If IGNNE# is deasserted, the transaction.
processor freezes on a non-control floating-point instruction if a When the priority agent asserts BPRI# to arbitrate for bus ownership,
previous instruction caused an error. IGNNE# has no affect when the it waits until it observes LOCK# deasserted. This enables the
NE bit in control register 0 (CR0) is set. processor to retain bus ownership throughout the bus locked operation
INIT# I The INIT# (Initialization) signal is asserted to reset integer registers and guarantee the atomicity of lock.
1.5V inside the processor without affecting the internal (L1 or L2) caches NMI I The NMI (Non-Maskable Interrupt) indicates that an external
Tolerant or the floating-point registers. The processor begins execution at the 1.5V interrupt has been generated. NMI becomes the LINT1 signal when
power-on reset vector configured during power-on configuration. The Tolerant the APIC is disabled. Asserting NMI causes an interrupt with an
processor continues to handle snoop requests during INIT# assertion. internally supplied vector value of 2. An external interrupt-
INIT# is an asynchronous input. acknowledge transaction is not generated. If NMI is asserted during
If INIT# is sampled active on RESET#'s active-to-inactive transition, the execution of an NMI service routine, it remains pending and is
then the processor executes its built-in self test (BIST). recognized after the IRET is executed by the NMI service routine. At
most, one assertion of NMI is held pending. NMI is rising edge
sensitive.

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5.1 Pentium III/Celeron µPGA2 CPU-4

Alphabetical Signal Reference PWRGOOD Relationship at Power On

Signal Name I/O Signal Description The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
PICCLK I The PICCLK (APIC Clock) signal is an input clock to the processor against voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary
2.5V and system logic or I/O APIC that is required for operation of the scan operation.
Tolerant processor, system logic, and I/O APIC components on the APIC bus. Signal Name I/O Signal Description
PICD[1:0] I/O The PICD[1:0] (APIC Data) signals are used for bi-directional serial
REQ[4:0]# I/O The REQ[4:0]# (Request Command) signals must be connected to the
1.5V message passing on the APIC bus. They must be connected to the
GTL+ appropriate pins/balls on both agents on the system bus. They are
Tolerant appropriate pins/balls of all APIC bus agents, including the processor
asserted by the current bus owner when it drives A[35:3]# to define
Open- and the system logic or I/O APIC components. If the PICD0 signal is
the currently active transaction type.
drain sampled low on the active-to-inactive transition of the RESET#
signal, then the APIC is hardware disabled. RESET# I Asserting the RESET# signal resets the processor to a known state
GTL+ and invalidates the L1 and L2 caches without writing back Modified
PLL1, PLL2 Analog The PLL1 and PLL2 signals provide isolated analog decoupling is
(M state) lines. For a power-on type reset, RESET# must stay active
required for the internal PLL. See Section 3.2.2 for a description of
for at least 1 msec after Vcc and BCLK have reached their proper DC
the analog decoupling circuit.
and AC specifications and after PWRGOOD has been asserted. When
PRDY# O The PRDY# (Probe Ready) signal is a processor output used by
observing active RESET#, all bus agents will deassert their outputs
GTL+ debug tools to determine processor debug readiness.
within two clocks. RESET# is the only GTL+ signal that does
PREQ# I The PREQ# (Probe Request) signal is used by debug tools to request
not have on-die GTL+ termination. A 56.2Ω1% terminating resistor
1.5V debug operation of the processor.
connected to VccT is required.
Tolerant
A number of bus signals are sampled at the active-to-inactive
PWRGOOD I PWRGOOD (Power Good) is a 2.5-V tolerant input. The processor
transition of RESET# for the power-on configuration. The
2.5V requires this signal to be a clean indication that clocks and the power
configuration options are described in Section 4 and in the Pentium II
Tolerant supplies (Vcc, VccT, etc.) are stable and within their specifications.
Processor Developer’s Manual.
Clean implies that the signal will remain low, (capable of sinking
Unless its outputs are tri-stated during power-on configuration, after
leakage current) and without glitches, from the time that the power
an active-to-inactive transition of RESET#, the processor optionally
supplies are turned on, until they come within specification. The
executes its built-in self-test (BIST) and begins program execution at
signal will then transition monotonically to a high (2.5V) state. Figure
reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected
26 illustrates the relationship of PWRGOOD to other system signals.
to the appropriate pins/balls on both agents on the system bus.
PWRGOOD can be driven inactive at any time, but clocks and power
RP# I/O The RP# (Request Parity) signal is driven by the request initiator and
must again be stable before the rising edge of PWRGOOD. It must
GTL+ provides parity protection on ADS# and REQ[4:0]#. RP# should be
also meet the minimum pulse width specified in Table 17 (Section
connected to the appropriate pins/balls on both agents on the system
3.7) and be followed by a 1 ms RESET# pulse.
bus.
A correct parity signal is high if an even number of covered signals
PWRGOOD Relationship at Power On are low and low if an odd number of covered signals are low. This
definition allows parity to be high when all covered signals are high.
RS[2:0]# I The RS[2:0]# (Response Status) signals are driven by the response
GTL+ agent (the agent responsible for completion of the current transaction)
and must be connected to the appropriate pins/balls on both agents on
the system bus.

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5.1 Pentium III/Celeron µPGA2 CPU-5

PWRGOOD Relationship at Power On

Signal Name I/O Signal Description Signal Name I/O Signal Description
RSP# I The RSP# (Response Parity) signal is driven by the response agent TDI I The TDI (Test Data In) signal transfers serial test data to the
GTL+ (the agent responsible for completion of the current transaction) 1.5V processor. TDI provides the serial input needed for JTAG support.
during assertion of RS[2:0]#. RSP# provides parity protection for Tolerant
RS[2:0]#. RSP# should be connected to the appropriate pins/balls on TDO O The TDO (Test Data Out) signal transfers serial test data from the
both agents on the system bus. 1.5V processor. TDO provides the serial output needed for JTAG support.
A correct parity signal is high if an even number of covered signals Tolerant
are low, and it is low if an odd number of covered signals are low. Open-
During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high drain
since it is not driven by any agent guaranteeing correct parity. TESTHI I The TESTHI (Test input High) is used during processor test and
RSVD TBD The RSVD (Reserved) signal is currently unimplemented but is 1.5V needs to be pulled high during normal operation.
reserved for future use. Leave this signal unconnected. Intel Tolerant
recommends that a routing channel for this signal be allocated. TESTLO[2:1] I The TESTLO[2:1] (Test input Low) signals are used during processor
RTTIMPEDP Analog The RTTIMPEDP (RTT Impedance/PMOS) signal is used to 1.5V test and needs to be pulled to ground during normal operation.
configure the on-die GTL+ termination. Connect the RTTIMPEDP Tolerant
signal to VSS with a 56.2-Ω, 1% resistor. TESTP Analog The TESTP (Test Point) signals are connected to Vcc and Vss at
SLP# I The SLP# (Sleep) signal, when asserted in the Stop Grant state, opposite ends of the die. These signals can be used to monitor the Vcc
1.5V causes the processor to enter the Sleep state. During the Sleep state, level on the die. Route the TESTP signals to test points or leave them
Tolerant the processor stops providing internal clock signals to all units, unconnected. Do not short the TESTP signals together.
leaving only the Phase-Locked Loop (PLL) still running. The THERMDA, Analog The THERMDA (Thermal Diode Anode) and THERMDC (Thermal
processor will not recognize snoop and interrupts in the Sleep state. THERMDC Diode Cathode) signals connect to the anode and cathode of the on-
The processor will only recognize changes in the SLP#, STPCLK# die thermal diode.
and RESET# signals while in the Sleep state. If SLP# is deasserted, TMS I The TMS (Test Mode Select) signal is a JTAG support signal used by
the processor exits Sleep state and returns to the Stop Grant state in 1.5V debug tools.
which it restarts its internal clock to the bus and Tolerant
APIC processor units. TRDY# I The TRDY# (Target Ready) signal is asserted by the target to indicate
SMI# I The SMI# (System Management Interrupt) is asserted asynchronously GTL+ that the target is ready to receive write or implicit write-back data
1.5V by system logic. On accepting a System Management Interrupt, the transfer. TRDY# must be connected to the appropriate pins/balls on
Tolerant processor saves the current state and enters System Management both agents on the system bus.
Mode (SMM). An SMI Acknowledge transaction is issued, and the TRST# I The TRST# (Test Reset) signal resets the Test Access Port (TAP)
processor begins program execution from the SMM handler. 1.5V logic. The mobile Pentium III processors do not self-reset during
STPCLK# I The STPCLK# (Stop Clock) signal, when asserted, causes the Tolerant power on; therefore, it is necessary to drive this signal low during
1.5V processor to enter a low-power Stop Grant state. The processor issues power-on reset.
Tolerant a Stop Grant Acknowledge special transaction and stops providing
internal clock signals to all units except the bus and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in the Stop Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no affect on the bus clock.
TCK I The TCK (Test Clock) signal provides the clock input for the test bus
1.5V (also known as the test access port).
Tolerant

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5.1 Pentium III/Celeron µPGA2 CPU-6
PWRGOOD Relationship at Power On
Signal Name I/O Signal Description
VID[4:0] O - The VID[4:0] (Voltage ID) pins/balls can be used to support
Open- automatic selection of power supply voltages. These pins/balls are not
drain signals, they are either an open circuit or a short to VSS on the
processor substrate. The combination of opens and shorts encodes the
voltage required by the processor. External to pull-ups are required to
sense the encoded VID. For processors that have Intel SpeedStep
technology enabled, VID[4:0] encode the voltage required in the
battery-optimized mode. VID[4:0] are needed to cleanly support
voltage specification changes on mobile Pentium III processors. The
voltage encoded by VID[4:0] is defined in Table 39. A "1" in this
table refers to an open pin/ball and a "0" refers to a short to VSS. The
power supply must provide the requested voltage or disable itself.
Please note that in order to implement VID on the BGA2 package,
some VID[4:0] balls may be depopulated. For the BGA2 package, a
"1" in Table 39 implies that the corresponding VID ball is
depopulated, while a "0" implies that the corresponding VID ball is
not depopulated.
But on the Micro-PGA2 package, VID[4:0] pins are not depopulated.

77
 7170 N/B MAINTENANCE
5.2 VIA VT8603 Twister North Bridge Controller-1
VT8603 / Twister OVERVIEW
Twister (VT8603) is a high performance, cost-effective and energy efficient SMA chip set for the implementation of
mobile personal computer systems with 66 MHz, 100 MHz and 133 MHz CPU host bus (“Front Side Bus”) frequencies
and based on 64-bit Socket-370 and Slot-1 (Intel Pentium III, Pentium-II and Celeron) super-scalar processors.

78
 7170 N/B MAINTENANCE
5.2 VIA VT8603 Twister North Bridge Controller-2
Twister integrates VIA’s VT82C694X system controller, S3’s Savage4 2D/3D graphics accelerator and S3’s flat panel
interfaces into a single 552 BGA package. The Twister SMA system controller provides superior performance between
the CPU, DRAM and PCI bus with pipelined, burst, and concurrent operation.
Twister supports six banks of DRAMs up to 1.5Gbyte of system memory with 256Mbit DRAM technology. The DRAM
controller supports standard Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible
mix /match manner. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data
buffers at 100/133 MHz. The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M
/32MxN DRAMs. The DRAM controller can run at either the host CPU Front Side Bus frequency (100 / 133 MHz) or
pseudo-synchronous to the CPU FSB frequency (PC100 with the FSB at 133 MHz or PC133 with the FSB at 100 MHz)
with built-in PLL timing control.
Twister supports a 32-bit 3.3 / 5V system bus (PCI) that is synchronous / pseudo-synchronous to the CPU bus. The chip
Also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels
(doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels(doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-
Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition,
advanced features are supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-
back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction
and read caching mechanisms are also implemented for further improvement of overall system performance.
Twister also integrates S3’s Savage graphics accelerator into a single chip. Twister brings mainstream graphics
performance to the Value PC with leading-edge 2D, 3D and DVD video acceleration into a cost effective package. Based
on its capabilities, Twister is an ideal solution for the consumer, corporate mobile users and entry level professionals.
The industry’s first integrated AGP 4X solution, Twister combines AGP 4X performance with S3’s DX6 texture
Compression (S3TC) and massive 2Kx2K textures to deliver unprecedented 3D performance and image quality for the
Value PC mobile market.

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The 352-pin VT8231 BGA PCI-LPC bridge supports four levels (doublewords) of line buffers, type F DMA transfers and
delay transaction to allow efficient PCI bus utilization and (PCI-2.2 compliant). The VT8231 also includes an integrated
Super I/O, integrated DS12885 style real time clock with extended 256 byte CMOS RAM, integrated master mode
enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33 / 66 / 100 for 33 / 66 / 100
MB/sec transfer rate, integrated four USB interface with root hub and two function ports with built-in physical layer
transceivers, Distributed DMA support, integrated AC-97 link for basic audio and HSP based modem functions, integrated
hardware monitoring and OnNow / ACPI compliant advanced configuration and power management interface. The
VT8231 also has an integrated MAC and 10Mbit PHY for LAN connection. It can bypass the internal PHY with external
home PNA with a 1Mbit PHY or a 10/100Mbit PHY through the MII interface.
For sophisticated power management, Twister provides independent clock stop control for the CPU / SDRAM and PCI and
Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the SDRAM
control signals for Suspend-to-DRAM operation. Coupled with the VT8231 south bridge chip, a complete power conscious
PC main board can be implemented with no external TTLs.
High-Performance 3D Accelerator
Featuring a new super-pipelined 128-bit engine, Twister utilizes a single cycle architecture that provides high performance
along with superior image quality. Several new features enhance the 3D architecture, including single-pass multitexturing,
anisotropic filtering, and an 8-bit stencil buffer. Twister also offers the industry’s only simultaneous usage of single-pass
multitexturing and single-cycle trilinear filtering ?enabling stunning image quality without performance loss. Twister
further enhances image quality with true 32-bit color rendering throughout the 3D pipeline to produce more vivid and
realistic images. Twister’s advanced triangle setup engine provides industry leading 3D performance for a realistic user
experience in games and other interactive 3D applications. The 3D engine is optimized for AGP texturing from system
memory.
128-bit 2D Graphics Engine
Twister’s advanced 128-bit 2D graphics engine delivers high-speed 2D acceleration for productivity applications. Several
enhancements have been made to the 2D architecture to optimize SMA performance and to provide acceleration in all color
depths.
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DVD Playback and Video Conferencing
Twister provides the ideal architecture for high quality MPEG-2 based DVD applications and video conferencing. For DVD
playback, Twister’s video accelerator offloads the CPU by performing the planar to packed format conversion and motion
compensation tasks, while its enhanced scaling algorithm delivers incredible full-screen video playback. For video
conferencing, Twister’s multiple video windows enable a cost effective solution.
LCD and Flat Panel Monitor Support
Twister supports a wide variety of DSTN or TFT panels through a 36-bit interface. This includes support for VGA, SVGA,
XGA, SXGA+, UXGA, and UXGA+ TFT color panels with 9-bit, 12-bit, 18-bit (both 1 pixel/clock and 2 pixels/clock), and
24-bit interfaces. Enhanced STN hardware with 256 gray scale support and advanced frame rate control to provide up to 16.7
million colors. In addition, the integrated 2-channel LVDS interface can support another panel. All resolutions are supported
up to 1280x1024. The integrated ZV-Port allows display of video from an external source.
An alternative to the 36-bit panel interface is a 12-bit interface to a TMDS encoder. This interface is Digital Visual Interface
(DVI) 1.0 compliant.

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VT8603 / Twister Pin Descriptions

CPU Interface Signal Name PIN # I/O Signal Description
Signal Name PIN # I/O Signal Description HTRDY# G25 IO Host Target Ready. Indicates that the target of the
HA[31:3]# (see pinout tables) IO Host Address Bus. HA[31:3] connect to the address bus processor transaction is able to enter the data transfer
of the host CPU. During CPU cycles HA[31:3] are phase.
inputs. These signals are driven by the Twister during RS[2:0]# H25, K23 IO Response Signals. Indicates the type of response per the
cache snooping operations. H23 table below:
HD[63:0]# (see pinout tables) IO Host CPU Data. These signals are connected to the RS[2:0]# Response type
CPU data bus. 000 Idle State
001 Retry Response
ADS# J24 IO Address Strobe. The CPU asserts ADS# in T1 of the
010 Defer Response
CPU bus cycle.
011 Reserved
BNR# D26 IO Block Next Request. Used to block the current request
100 Hard Failure
bus owner from issuing new requests. This signal is used
101 Normal Without Data
to dynamically control the processor bus pipeline depth.
110 Implicit Writeback
BPRI# E26 IO Priority Agent Bus Request. The owner of this signal 111 Normal With Data
will always be the next bus owner. This signal has
CPURST# A19 O CPU Reset. Reset output to CPU. External pullup and
priority over symmetric bus requests and causes the
filter capacitor to ground should be provided per CPU
current symmetric owner to stop issuing new
manufacturer’s recommendations.
transactions unless the HLOCK# signal is asserted. The
CPURSTD# E22 O CPU Reset Delayed. CPU reset output delayed by 2T.
Twister drives this signal to gain control of the processor
bus. BREQ0# J25 O Bus Request 0. Bus request output to CPU.
DBSY# H26 IO Data Bus Busy. Used by the data bus owner to hold the Note: Clocking of the CPU interface is performed with HCLK.
data bus for transfers requiring more than one cycle. Note: Internal pullup resistors are provided on all GTL interface pins. If the CPU does not have
DEFER# F26 IO Defer. The Twister uses a dynamic deferring policy to internal pullups, these north bridge internal pullups may be enabled to allow the interface to meet
optimize system performance. The Twister also uses the GTL bus interface specifications (see MA6 strap description).
DEFER# signal to indicate a processor retry response. The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout
DRDY# J23 IO Data Ready. Asserted for each cycle that data is shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX, and NLX) were also
transferred. considered and can typically follow the same general component placement.
HIT# G24 IO Hit. Indicates that a caching agent holds an unmodified
version of the requested line. Also driven in conjunction
with HITM# by the target to extend the snoop window.
HITM# G26 I Hit Modified. Asserted by the CPU to indicate that the
address presented with the last assertion of EADS# is
modified in the L1 cache and needs to be written back.
HLOCK# G23 I Host Lock. All CPU cycles sampled with the assertion
of HLOCK# and ADS# until the negation of HLOCK#
must be atomic.
HREQ[4:0]# E25, F25, IO Request Command. Asserted during both clocks of the
F24, F23 request phase. In the first clock, the signals define the
E24 transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals
carry additional information to define the complete
transaction type.

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DRAM Interface Signal Name PIN # I/O Signal Description

Signal Name PIN # I/O Signal Description SCASA# U22 O Column Address Command Indicator. For support
MD[63:0] (see pinout IO Memory Data. These signals are connected to the SCASB# / CKE3 V25 of up to three synchronous DRAM DIMM slots. “A”
tables) DRAM data bus. SCASC# / CKE1 V24 controls banks 0-1 (module 0), “B” controls banks
MA14 /graphics strap AF25 O/I Memory Address. DRAM address lines / strap 2-3 (module 1) and “C” controls banks 4-5 (module
MA13 /graphics strap AE25 options 2).
MA12 / BA1 /strap, AE24 MA12 strap – Host Freq Select lsb (see MA8 below SWEA# / MWEA U24 O Write Enable Command Indicator. For support of
MA11 / BA0 /strap, AD24 for msb) SWEB#/MWEB#/CKE2 U25 up to three synchronous DRAM DIMM slots. Used
MA10 AE26 MA11 strap – IOQ Level (0=4-level, 1=1-level) SWEC#/ MWEC#/CKE0 U26 as MWE# for FPG/EDO memory. “A” controls
MA9 /strap, AD25 MA9 strap – Clock select (0=Use PLLs, 1=Clocks banks 0-1 (module 0), “B” controls banks 2-3
MA8 /strap, AD26 on XIN/PD10 pins) (module 1) and “C” controls banks 4-5 (module 2).
MA7 /strap, AC24 MA8 strap – Host Freq Select msb (00=66, 01=100, CKE0 / SWEC# U26 O SDRAM Clock Enables. Clock enables for each
MA6 /strap, AC25 10=auto, 11=133) CKE1 / SCASC# V24 DRAM bank for powering down the SDRAM or
MA5 /strap, AC26 MA7 strap – Graphics Test Mode (0=Normal, CKE2 / SWEB# U25 clock control for reducing power usage and for
MA4 / graphics strap, AB24 1=Test) CKE3 / SCASB# V25 reducing heat / temperature in high-speed memory
MA3 / graphics strap, AB25 MA6 strap – GTL Internal Pullups (0=Enable, CKE4 / SRASC# AA26 systems.
MA2 / graphics strap, AB26 1=Disable) CKE5 / SRASB# AA25
MA1 / graphics strap, AB23 MA5 strap – PCI Frequency (0=33 MHz, 1=66
MA0/ graphics strap AA23 MHz)
MA4 strap – Graphics PCI Interrupt (0=Enable,
1=Disable)
MA3 strap – Graphics I/O (0=Enable, 1=Disable)
MA2 strap – Graphics PCI Base Address (0=Map0,
1=Map1)
MA14,13,1,0 – Graphics OEM-Defined Panel Type
(Note: all non-graphics straps default to 0 if not
connected to a strap resistor. See Table 9 for
graphics strap definitions and defaults.)
CS[5:0]# W21, Y22 O Chip Select. (Synchronous DRAM) Chip select of
RAS[5:0]# Y23, Y24 each bank.
Y25, Y26 RAS. (FPG/EDO DRAM)
DQM[7:0] AF23, O Data Mask. (Synchronous DRAM) Data mask of
CAS[7:0]# AD23, each byte lane
W25, W26, CAS. (FPG/EDO DRAM)
AE23,
AF24,
W23, V23
SRASA# AA24 O Row Address Command Indicator. For support of
SRASB# / CKE5 AA25 up to three synchronous DRAM DIMM slots. “A”
SRASC# / CKE4 AA26 controls banks 0-1 (module 0), “B” controls banks
2-3 (module 1) and “C” controls banks 4-5 (module
2).

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PCI Bus Interface Signal Name PIN # I/O Signal Description

Signal Name PIN # I/O Signal Description INTA# W5 O PCI Interrupt Out. An asynchronous active low output
AD[31:0] (see pinout tables) IO Address/Data Bus. The standard PCI address and data used to signal an event that requires handling on behalf
lines. The address is driven with FRAME# assertion and of the internal integrated graphics controller. If MA2 is
data is driven or received in following cycles. strapped high at reset (clearing CR36[0]) no interrupt
CBE[3:0]# AD7, AD9, IO Command/Byte Enable. Commands are driven with will be requested during PCI configuration. The default
AB11, AF12 FRAME# assertion. Byte enables corresponding to drive strength is 24 Ma (other drive strengths may be
supplied or requested data are driven on following selected via CR80[1-0]).
clocks. WSC# AA11 O Write Snoop Complete. Sideband PCI signal (used on
FRAME# AE9 IO Frame. Assertion indicates the address phase of a PCI the planar only in multiprocessor configurations)
transfer. Negation indicates that one more data transfer asserted to indicate that all snoop activity on the CPU
is desired by the cycle initiator. bus initiated by the last PCI-to-DRAM write is complete
IRDY# AC10 IO Initiator Ready. Asserted when the initiator is ready for and that it is safe to send an APIC interrupt message.
data transfer. Basically this signal is always active except when PCI
master write data is not flushed.
TRDY# AD10 IO Target Ready. Asserted when the target is ready for
data transfer.
STOP# AE10 IO Stop. Asserted by the target to request the master to stop
the current transaction.
DEVSEL# AB9 IO Device Select. This signal is driven by the Twister when
a PCI initiator is attempting to access main memory. It is
an input when the Twister is acting as a PCI initiator.
PAR AB10 IO Parity. A single parity bit is provided over AD[31:0]
and C/BE[3:0].
SERR# AF10 IO System Error. The Twister will pulse this signal when it
detects a system error condition.
LOCK# AE5 IO Lock. Used to establish, maintain, and release resource
lock.
PREQ# AC15 I South Bridge Request. This signal comes from the
South Bridge. PREQ# is
the South Bridge request for the PCI bus.
PGNT# AD15 O South Bridge Grant. This signal driven by the Twister
to grant PCI access to the South Bridge.
REQ[3:0]# AD4, AE4, I PCI Master Request. PCI master requests for PCI.
AD5, AC5
GNT[3:0]# AE3, AF3, O PCI Master Grant. Permission is given to the master to
AF4, AB5 use PCI.
REQX# AF2 I PCI Master Request. PCI master request for PCI.
GNTX# AE2 O PCI Master Grant. Permission is given to the master to
use PCI.
PCLK AB15 I PCI Clock. From external clock generator.
PCKRUN# AF15 IO PCI Clock Run. May be used to stop PCI clock.

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LCD Panel Interface TV Encoder Interface

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
FPD[35:0] (see pin table) O Panel Data. Internally pulled down during reset. 8mA is the TVD[11:0] (see pin table) O TV Data. Internally pulled down during reset
default. 16mA is selected via SR3D[6]=1. TVCLK V4 I TV Clock. Input clock from encoder. Internally pulled down.
FPDET AA16 I Panel Detect. If SR30[1]=0, SR30[2] will read 1 if a Flat
Panel is appropriately connected. Must be tied to GND if not TVCLKR K5 O TV Return Clock. Output clock to TV encoder. Internally
used. pulled down.
FPVS G3 O Panel VSYNC. Internally pulled down. TVVS W3 O TV VSYNC. Internally pulled down during reset
FPHS G5 O Panel HSYNC. Internally pulled down. TVHS V5 O TV HSYNC. Internally pulled down during reset
FPDE H3 O Panel Data Enable. Internally pulled down. TVBLK# L1 O TV Blanking. Internally pulled down during reset
FPCLK G4 O Panel Clock. Internally pulled down during reset. 8mA is the
default. 16mA may also be selected. CRT Interface
ENVDD F1 O Enable VDD. This signal is driven high to external logic to Signal Name PIN # I/O Signal Description
initiate a flat panel power up sequence. RSET E3 A Reference Resistor. Tie to GNDRGB through an external 140_
ENVEE H5 O Enable VEE. This signal is driven high to a programmable resistor to control the RAMDAC full-scale current value.
time after ENVDD is driven high during a flat panel power up COMP E4 A Compensation. Tie to VCC25 through a 0.1 µF capacitor.
sequence.
FPGPIO G1 I/O General Purpose Input / Output. RED C2 A Analog Red. Analog red output to the CRT monitor.
BLUE D2 A Analog Blue. Analog blue output to the CRT monitor.
Flat Panel Monitor (DVI) Interface GREEN D3 A Analog Green. Analog green output to the CRT monitor.
Signal Name PIN # I/O Signal Description HSYNC E2 O Horizontal Sync. Output to CRT.
FPD[11:0] (see pin table) O Panel Data. Internally pulled down during reset. 8mA is the VSYNC E1 O Vertical Sync. Output to CRT.
default. 16mA is selected via SR3D[6]=1. This function is
selected on these pins when SR31[4] = 1. LVDS Interface
FPDET AA16 I Panel Detect. If SR30[1]=0, SR30[2] will read 1 if a Flat
Panel is appropriately connected. Must be tied to GND if not Signal Name PIN # I/O Signal Description
used. Y[2:0]P Y5, W4, AA3 A LVDS Data Positive Output.
FPVS G3 O Panel VSYNC. Internally pulled down. Y[2:0]M AA5, Y4, AB3 A LVDS Data Negative Output.
FPHS G5 O Panel HSYNC. Internally pulled down. YCP AB1 A LVDS Clock Positive Output.
FPDE H3 O Panel Data Enable. Internally pulled down. YCM AC1 A LVDS Clock Negative Output.
FPCLK G4 O Panel Clock. Internally pulled down during reset. 8mA is the Z[2:0]P AA4, AC3, AC2 A 2 nd LVDS Data Positive Output.
default. 16 mA may also be selected.
Z[2:0]M AB4, AD3, AD2 A 2 nd LVDS Data Negative Output.
ZV-Port Interface ZCP AD1 A 2 nd LVDS Clock Positive Output.
Signal Name PIN # I/O Signal Description ZCM AE1 A 2 nd LVDS Clock Negative Output.
ZVD[15:0] (see pin table) I ZV-Port Data Bus. Video Input
ZVCLK U3 I ZV-Port Clock.
ZVHS T3 I ZV-Port Horizontal Sync.

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Miscellaneous Functions Clock / Reset Control

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
XIN A2 I Reference Frequency Input. An external 14.318 MHz crystal is HCLK G22 IHost Clock. This pin receives the host CPU clock (66 / 100 / 133
connected between XOUT and this pin. Alternatively, an external MHz). This clock is used by all Twister logic that is in the host
oscillator can be connected. CPU domain.
XOUT A3 O Crystal Output. This pin drives the crystal via an internal PCLK AB15 I PCI Clock. This pin receives a buffered host clock divided-by-2, 3,
oscillator. If an external oscillator is connected to XIN, this pin can or 4 to create 33 MHz. This clock is used by all of the Twister logic
be left unconnected. that is in the PCI clock domain. This clock input must be 33 MHz
SPCLK[2:1] M2, F3 IO Serial Port Clocks. These are the clocks for serial data transfer. maximum to comply with PCI specification requirements and must
SPCLK1 is typically used for I 2C communications. As an output, it be synchronous with the host CPU clock, HCLK, with an
is programmed via CRA0[0]. As an input, its status is read via HCLK:PCLK frequency ratio of 2:1, 3:1, or 4:1 as shown in the
CRA0[2]. In either case the serial port must be enabled by CRA0[4] table below. The host CPU clock must lead the PCI clock by 2.0 ±
= 1. SPCLK2 is typically used for DDC monitor communications. 1.0 nsec.
As an output, it is programmed via CRB1[0]. As an input, its status Typical Clock Frequency Combinations
is read via CRB1[2]. The port is enabled via CRB1[4] = 1. Rx68[1:0] Mode Host Clock AGP Clock PCI Clock
SPDAT[2:1] M3, F2 IO Serial Port Data. These are the data signals used for serial data 00 2x 66 MHz 66 MHz 33 MHz
transfer. SPDAT1 is typically used for I 2C communications. As an 01 3x 100 MHz 66 MHz 33 MHz
output, it is programmed via CRA0[1]. As an input, its status is read 10 4x 133 MHz 66 MHz 33 MHz
via CRA0[3]. In either case the serial port must be enabled by 11 Reserved
CRA0[4] = 1. SPDAT2 is typically used for DDC monitor MCLK J22 O DRAM Clock. Output from internal clock generator to the external
communications. As an output, it is programmed via CRB1[1]. As clock buffer.
an input, its status is read via CRB1[3]. The port is enabled via MCLKF K22 I DRAM Clock Feedback. Input from the external clock buffer.
CRB1[4] = 1. RESET# AE15 I Reset. Input from South Bridge chip. When asserted, this signal
GPOUT AA12 O General Purpose Output. This pin reflects the state of SRD[0]. resets the Twister and sets all register bits to the default value. The
GOP0 C3 O General Output Port. When SR1A[4] is cleared, this pin reflects rising edge of this signal is used to sample all power-up strap
the state of CR5C[0]. options
STPAGP# C4 I Stop AGP. Power management for internal AGP. PWROK AD14 I Power OK. Connect to South Bridge and Power Good circuitry.
AGPBUSY# B4 I/O AGP Busy. Power management for internal AGP. CPURST# A19 O CPU Reset. GTL output level.
STANDBY F4 I Standby. Used to put the integrated graphics controller in the CPURSTD# E22 O CPU Reset Delayed. Reset output delayed by 2T.
standby state.
SUSPEND F5 I Suspend. Used to put the integrated graphics controller in the
suspend state.
SUSST# AC22 I Suspend Status. For implementation of the Suspend-to-DRAM
feature. Connect to an external pullup to disable.

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Power, Ground, and Test

Signal Name PIN # I/O Signal Description
VCC3 (see pin list) P Power for I/O Interface Logic (3.3V ±5%).
VCC25 (see pin list) P Power for Internal Logic (2.5V ±5%).
VCC5 U6 P Power for 5V Input Tolerance (5V ±5%).
VSUS25 AA22 P Suspend Power (2.5V ±5%).
VCCRGB D1 P Power for CRT (2.5V ±5%).
VCCA H21, H22 P Power for Analog (2.5V ±5%)
VCCDAC C1 P Power for DAC Digital Logic (2.5V ±5%)
VCCPLL1 B3 P Power for PLL1 (2.5V ±5%).
VCCPLL2 A5 P Power for PLL2 (2.5V ±5%).
VCCLPLL AB2 P Analog Power for LVDS PLL (2.5V ±5%).
VCCLVDS W1, W2 P Analog Power for LVDS (3.3V ±5%).
VDDD Y2 P Digital Power for LVDS (2.5V ±5%).
GND (see pin table) P Ground
GNDA L21, L22 P Ground for North Bridge Host CPU Clock Circuitry.
Connect to main ground plain through a ferrite bead.
GNDRGB A1 P Connection point for RGB load resistors
GNDDAC B1 P Ground for DAC Analog Circuitry
GNDPLL1 A4 P Ground for PLL1
GNDPLL2 B5 P Ground for PLL2
GNDLPLL Y3 P Ground for LVDS PLL
GNDLVDS Y1, AA1 P Ground for LVDS Analog Circuitry
GNDD AA2 P Ground for LVDS Digital Circuitry
GTLREF E12, E21 P CPU Interface GTL+ Voltage Reference. 2/3 VTT ±2%
PLLTST K24 I PLL Test Input. Pull down with 4.7K resistor for normal
operation.
BISTIN F15 I BIST In. This pin is used for testing and must be left
unconnected or tied high on all board designs.
DFTIN F11 I DFT In. This pin is used for testing and must be left
unconnected or tied high on all board designs.
NC R21, V22, - No Connect. Reserved for future use. Do not connect.
W22, AB22

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VT8231 OVERVIEW
The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports
Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant
PCI /LPC system. The VT8231 includes standard intelligent peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100
standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-family compliant.
b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external Ethernet PHY or
HomePNA PHY. The LAN controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex
operation and has separate 2Kbyte FIFOs for receive and transmit of full ethernet packets. The internal high-performance
PCI interface has scatter / gather and bursting capability and can align bytes in the transmit data buffer to reduce CPU
utilization. The LAN interface can perform address filtering on physical, broadcast, and multicast packets. The interface
can also be configured for system wake up on link status change, receipt of magic packet, unicast physical address match
on incoming packets, and predefined pattern match in the incoming data.
c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support
d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub
with four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and
isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy
keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system
environment.
e) Keyboard controller with PS2 mouse support
f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also
includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
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g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep
states (power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up.
Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus
clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general
purpose I/O, chip select and external SMI.
h) Hardware monitoring subsystem for managing system / motherboard voltage levels, temperatures, and fan speeds
i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port
j) 16550-compatible serial I/O port with “Fast-IR”infrared communications port option.
k) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro
and hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback
capability is also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.
l) Game port and MIDI port
m) Standard floppy disk drive interface
n) ECP/EPP-capable parallel port with floppy disk controller
pinout option
o) Serial IRQ for docking and non-docking applications
p) Plug and Play controller that allows complete steerability
of all PCI interrupts and internal interrupts to any interrupt
channel. One additional steerable interrupt channel is
provided to allow plug and play and reconfigurability of
on-board peripherals for Windows family compliance.

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Pin Descriptions
PCI Bus Interface Signal Name PIN # I/O Signal Description
Signal Name PIN # I/O Signal Description PCKRUN# R5 IO PCI Bus Clock Run. This signal indicates whether the
AD[31:0] (see pin list) IO Address/Data Bus. The standard PCI address and data PCI clock is or will be stopped (high) or running (low).
lines. The address is driven with FRAME# assertion and The VT8231 drives this signal low when the PCI clock
data is driven or received in following cycles. IDSEL is is running (default on reset) and releases it when it stops
internally connected to AD28. the PCI clock. External devices may assert this signal
low to request that the PCI clock be restarted or prevent
C/BE[3:0]# C5, D6, IO Command/Byte Enable. The command is driven with
it from stopping. Connect this pin to ground using a
A8, F10 FRAME# assertion. Byte enables corresponding to
supplied or requested data are driven on following 100Ω resistor if the function is not used. Refer to the
clocks. “PCI Mobile Design Guide” and the VIA “Apollo
MVP4 Design Guide” for more details.
FRAME# F6 IO Frame. Assertion indicates the address phase of a PCI
transfer. Negation indicates that one more data transfer PCIRST# E4 O PCI Reset.
is desired by the cycle initiator. PCISTP#/ GPO6 T4 O PCI Stop.
IRDY# C7 IO Initiator Ready. Asserted when the initiator is ready for CPUSTP#/ GPO5 P4 O CPU Stop.
data transfer.
PREQH# C1 O PCI Request. This signal goes to the North Bridge
STOP# D7 IO Stop. Asserted by the target to request the master to stop
REQ4# input to request the PCI bus for high priority
the current transaction.
access. The internal LAN requests the PCI bus using this
DEVSEL# A7 IO Device Select. The VT8231 asserts this signal to claim
signal, so if the LAN subsystem is used, this signal must
PCI transactions through positive or subtractive
be connected (one of the H/LREQ/GNT 1 and 2 pairs
decoding. As an input, DEVSEL# indicates the response
provided by the VT8231 may be used to implement the
to a VT8231-initiated transaction and is also sampled
fifth PCI slot if desired). If the LAN subsystem is not
when decoding whether to subtractively decode the
used, PREQH# / PGNTH# may optionally remain
cycle.
unconnected.
PAR C8 IO Parity. A single parity bit is provided over AD[31:0]
PGNTH# D3 I PCI Grant. This signal is driven by the North Bridge
and C/BE[3:0]#.
GNT4# signal to grant high priority PCI access to the
SERR# E7 I System Error. SERR# can be pulsed active by any PCI VT8231.
device that detects a system error condition. Upon
PREQL# D2 O PCI Request. This signal goes to the North Bridge
sampling SERR# active, the VT8231 can be
PREQ# input to request the PCI bus for normal priority
programmed to generate an NMI to the CPU.
access.
PINTA-D# B2, B1, I PCI Interrupt Request. These pins are typically
PGNTL# D1 I PCI Grant. This signal is driven by the North Bridge
C3, C2 connected to the PCI bus INTA#-INTD# pins as follows:
PGNT# output to grant normal priority PCI access to the
PINTA# PINTB# PINTC# PINTD#
VT8231.
PCI Slot 1 INTA# INTB# INTC# INTD#
HREQ1#/ GPI10 Y11 I / IO High Priority Request 1. Device 0 Function 4 RxE5[3]
PCI Slot 2 INTB# INTC# INTD# INTA#
= 1.
PCI Slot 3 INTC# INTD# INTA# INTB#
PCI Slot 4 INTD# INTA# INTB# INTC# HGNT1#/ GPO8 W11 O / IO High Priority Grant 1. Device 0 Function 4 RxE5[3] =
PCI Slot 5 INTA# INTB# INTC# INTD# 1.
PCICLK M17 I PCI Clock. PCLK provides timing for all transactions HREQ2#/ GPI11 V11 I / IO High Priority Request 2. Device 0 Function 4 RxE5[3]
on the PCI Bus. = 1.

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PCI Bus Interface CPU Interface

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
HGNT2#/ GPO9 T10 O / IO High Priority Grant 2. Device 0 Function 4 RxE5[3] = 1. CPURST U4 OD CPU Reset. The VT8231 asserts CPURST to reset the CPU
LREQ1#/ GPI12 U10 I / IO Low Priority Request 1. Device 0 Function 4 RxE5[2] = 1. during power-up.
INTR R6 OD CPU Interrupt. INTR is driven by the VT8231 to signal the
LGNT1#/ GPO10 Y10 O / IO Low Priority Grant 1. Device 0 Function 4 RxE5[2] = 1. CPU that an interrupt request is pending and needs service.
LREQ2#/ GPI13 W10 I / IO Low Priority Request 2. Device 0 Function 4 RxE5[2] = 1. NMI T5 OD Non-Maskable Interrupt. NMI is used to force a
LGNT2#/ GPO11 V10 O / IO Low Priority Grant 2. Device 0 Function 4 RxE5[2] = 1. non-maskable interrupt to the CPU. The VT8231 generates
an NMI when either SERR# or IOCHK# is asserted.
INIT V5 OD Initialization. The VT8231 asserts INIT if it detects a
shut-down special cycle on the PCI bus or if a soft reset is
initiated by the register
STPCLK# V6 OD Stop Clock. STPCLK# is asserted by the VT8231 to the
CPU to throttle the processor clock.
SMI# Y5 OD System Management Interrupt. SMI# is asserted by the
VT8231 to the CPU in response to different
Power-Management events.
FERR# U5 I Numerical Coprocessor Error. This signal is tied to the
coprocessor error signal on the CPU. Internally generates
interrupt 13 if active.
IGNNE# T6 OD Ignore Numeric Error. This pin is connected to the “ignore
error” pin on the CPU.
SLP#/ GPO7 U6 OD Sleep (F4 RxE4[4] = 1). Used to put the CPU to sleep. Used
with slot-1 CPUs only. Not currently used with socket-7
CPUs.
A20M# W5 OD A20 Mask. Connect to A20 mask input of the CPU to
control address bit-20 generation. Logical combination of
the A20GATE input (from internal or external keyboard
controller) and Port 92 bit-1 (Fast_A20). See Device 0
Function 0 Rx59[1].
DTD+ L2 Analog CPU DTD (Thermal Diode) Channel Plus. Connect to
I cathode of first external temperature sensing diode.
DTD- L3 Analog CPU DTD (Thermal Diode) Channel Minus. Connect to
I anode of first external temperature sensing diode.
Note: Connect each of the above signals to 4.7KΩ pullup resistors to VCC3.

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Strap Options Advanced Programmable Interrupt Controller (APIC) Interface

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
Strap/SUSA#/ GPO1 P1 I / O CPURST / INIT Polarity WSC#/ GPI14 V4 I / I Internal APIC Write Snoop Complete. F0 Rx58[6] = 1.
H: Slot-1 / Socket-370 / Slot-A / Socket-A Asserted by the north bridge to indicate that all snoop activity on
L: Socket-7 the CPU bus initiated by the last PCI-to-DRAM write is complete
Strap/MCCS#/ GPO17 W6 I / O CPU Frequency Strapping and that it is safe to perform an APIC interrupt.
H: Disable APICD0/ GPO28 W4 O / O Internal APIC Data 0. F0 Rx58[6] = 1.
L: Enable APICD1/ GPO29 Y4 O / O Internal APIC Data 1. F0 Rx58[6] = 1.
Strap/ SA16 Y14 I / IO BIOS ROM Interface
H: LPC APICCLK/ GPI9 Y3 I / I APIC Clock. F0 Rx58[6] = 1.
L: Conventional
Strap/ SA17 T13 I / IO Auto Reboot
H: Disable (recommended)
L: Enable
Note: External strap option values may be set by connecting the indicated external pin to a 4.7K ohm Low Pin Count (LPC) Interface
pullup (for 1 or H) or driving it low during reset with a 7407 TTL open collector buffer (for 0
Signal Name PIN # I/O Signal Description
or L) as shown in the suggested circuit below:
LFRAME# W8 O LPC Frame.
LDRQ#/ GPI15 Y8 I / I LPC Data Request. F0 Rx58[5] = 1 and F4 RxE5[7] = 0.
LAD[3-0] V7,W7,Y7,V8 IO LPC Address / Data.
Note: For LPC control, see Device 0 Function 0 Rx58[5] and Rx59[4-3]
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

Serial EEPROM Interface

Signal Name PIN # I/O Signal Description
EECS# C18 O Serial EEPROM Chip Select.
EECK E16 O Serial EEPROM Clock.
EEDO D17 O Serial EEPROM Data Output.
EEDI E17 I Serial EEPROM Data Input.

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LAN Controller - Media Independent Interface (MII) Universal Serial Bus Interface
Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
MCOL G17 I MII Collision Detect. From the external PHY. USBP0+ B18 IO USB Port 0 Data +
MCRS G16 I MII Carrier Sense. Asserted by the external PHY when the USBP0- A18 IO USB Port 0 Data -
media is active. USBP1+ B19 IO USB Port 1 Data +
MDCK C20 O MII Management Data Clock. Sent to the external PHY as a
timing reference for MDIO USBP2+ B20 IO USB Port 2 Data +
MDIO D18 IO MII Management Data I/O. Read from the MDI bit or written to USBP2- A20 IO USB Port 2 Data -
the MDO bit. USBP3+ C17 IO USB Port 3 Data +
MRXCLK C19 I MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
USBP3- B17 IO USB Port 3 Data -
MRXD[3], D19 I MII Receive Data. Parallel receive data lines driven by the
USBCLK C15 I USB Clock. 48MHz clock input for the USB interface
MRXD[2], D20 I external PHY synchronous with MRXCLK.
MRXD[1], E18 I USBOC0# A17 I USB Port 0 Over Current Detect. Port 0 is disabled if
MRXD[0] E19 I this input is low.
MRXDV E20 I MII Receive Data Valid. USBOC1# D16 I USB Port 1 Over Current Detect. Port 1 is disabled if
this input is low
MRXERR F18 I MII Receive Error. Asserted by the PHY when it detects a data
decoding error. USBOC2#/ LA20/ W13 I / IO/ I / O USB Port 2 Over Current Detect. Port 2 is disabled if
GPI20 / GPO20 this input is low. Device 0 Function 4 RxE4[6] = 0 and
MTXCLK F17 I MII Transmit Clock. Always active 2.5 or 25 MHz clock
Power Management I/O Rx4E[4] = 1
supplied by the PHY.
USBOC3#/ LA21/ Y13 I / IO/ I / O USB Port 3 Over Current Detect. Port 3 is disabled if
MTXD[3], G20 O MII Transmit Data. Parallel transmit data lines synchronized to
GPI21 / GPO21 this input is low. Device 0 Function 4 RxE4[6] = 0 and
MTXD[2], G19 O MTXCLK.
Power Management I/O Rx4E[5] = 1
MTXD[1], G18 O
MTXD[0] F20 O
MTXENA F19 O MII Transmit Enable. Indicates transmit active from the MII
port to the PHY.
The internal LAN controller uses the high priority PCI bus request / grant pair (PREQH# / PGNTH#)
to request PCI bus access from the chipset north bridge.

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System Management Bus (SMB) Interface (I2C Bus) Signal Name PIN # I/O Signal Description
Signal Name PIN # I/O Signal Description PDIOW#/ P20 O EIDE Mode: Primary Device I/O Write. Device write strobe
SMBCK1 R3 IO PSTOP UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host
SMB / I2C Channel 1 Clock. prior to initiation of an UltraDMA burst; negated
SMBCK2/ GPIO27 R1 IO / IO SMB / I2C Channel 2 Clock†. F4 Rx55[3] = 0. by the host before data is transferred in an
SMBDT1 T1 IO UltraDMA burst. Assertion of STOP by the host
SMB / I2Channel 1 Data.
during or after data transfer in UltraDMA mode
SMBDT2/ GPIO26 R2 IO / IO SMB / I2C Channel 2 Data†. F4 Rx55[3] = 0.
signals the termination of the burst.
SMBALRT#/ GPI7 T2 I / I SMB Alert. (System Management Bus I/O space Rx08[3] = SDIOW#/ Y19 O EIDE Mode: Secondary Device I/O Write. Device write strobe
1) When the chip is enabled to allow it, assertion generates SSTOP UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the
an IRQ or SMI interrupt or a power management resume host prior to initiation of an UltraDMA burst;
event. The same pin is used as General Purpose Input 6 negated by the host before data is transferred in an
whose value is reflected in Rx48[6] of function 4 I/O space UltraDMA burst. Assertion of STOP by the host
Note: SMBus #2 is a slave-only device used to supply status for external Alert-On-LAN (AOL) during or after data transfer in UltraDMA mode
signals the termination of the burst.
UltraDMA-33 / 66 Enhanced IDE Interface PDDRQ P19 I Primary Device DMA Request. Primary channel DMA request
Signal Name PIN # I/O Signal Description SDDRQ U17 I Secondary Device DMA Request. Secondary channel DMA request
PDRDY/ N19 I EIDE Mode: Primary I/O Channel Ready. Device ready indicator PDDACK# N20 O Primary Device DMA Acknowledge. Primary channel DMA
PDDMARDY/ UltraDMA Mode: Primary Device DMA Ready. Output flow acknowledge
PDSTROBE control. The device may assert DDMARDY to SDDACK# W20 O Secondary Device DMA Acknowledge. Secondary channel DMA
pause output transfers acknowledge
Primary Device Strobe. Input data strobe (both T14 I Primary Channel Interrupt Request.
IRQ14
edges). The device may stop DSTROBE to pause
input data transfers IRQ15 U14 I Secondary Channel Interrupt Request.
SDRDY/ Y20 I EIDE Mode: Secondary I/O Channel Ready. Device ready indicator
SDDMARDY/ UltraDMA Mode: Secondary Device DMA Ready. Output flow
SDSTROBE control. The device may assert DDMARDY to MIDI Interface
pause output transfers
Signal Name PIN # I/O Signal Description
Secondary Device Strobe. Input data strobe (both
edges). The device may stop DSTROBE to pause MSI G4 I MIDI Serial In
input data transfers MSO J4 O MIDI Serial Out
PDIOR#/ N18 O EIDE Mode: Primary Device I/O Read. Device read strobe
PHDMARDY/ UltraDMA Mode: Primary Host DMA Ready. Primary channel
PHSTROBE input flow control. The host may assert
AC97 Audio / Modem Interface
HDMARDY to pause input transfers
Primary Host Strobe. Output data strobe (both Signal Name PIN # I/O Signal Description
edges). The host may stop HSTROBE to pause ACRST# G2 O AC97 Reset
output data transfers
ACSYNC G1 O AC97 Sync
SDIOR#/ W19 O EIDE Mode: Secondary Device I/O Read. Device read strobe
SHDMARDY/ UltraDMA Mode: Secondary Host DMA Ready. Input flow control. ACSDOUT H3 O AC97 Serial Data Out
SHSTROBE The host may assert HDMARDY to pause input ACSDIN0 H1 I AC97 Serial Data In 0
transfers
ACSDIN1 H2 I AC97 Serial Data In 1
Host Strobe B. Output strobe (both edges). The
host may stop HSTROBE to pause output data ACBITCLK J3 I AC97 Bit Clock
transfers 94
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UltraDMA-33 / 66 Enhanced IDE Interface (continued) Floppy Disk Interface

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
PDCS1# L18 O Primary Master Chip Select. This signal corresponds to DRVDEN0 L17 O Drive Density Select 0.
CS1FX# on the primary IDE connector. DRVDEN1 K17 O Drive Density Select 1.
PDCS3# L19 O Primary Slave Chip Select. This signal corresponds to
CS3FX# on the primary IDE connector. MTR0# K18 O Motor Control 0. Select motor on drive 0.
SDCS1# U18 O Secondary Master Chip Select. This signal corresponds MTR1# J16 O Motor Control 1. Select motor on drive 1
to CS17X# on the secondary IDE connector. DS0# J17 O Drive Select 0. Select drive 0.
SDCS3# U19 O Secondary Slave Chip Select. This signal corresponds to
DS1# K19 O Drive Select 1. Select drive 1
CS37X# on the secondary IDE connector.
PDA[2-0] M20, M18, M19 O Primary Disk Address. PDA[2:0] are used to indicate DIR# K20 O Direction. Direction of head movement (0 = inward motion, 1 =
which byte in either the ATA command block or control outward motion)
block is being accessed. STEP# J18 O Step. Low pulse for each track-to-track movement of the head.
SDA[2-0] V20, V18, V19 O Secondary Disk Address. SDA[2:0] are used to indicate INDEX# L20 I Index. Sense to detect that the head is positioned over the beginning
which byte in either the ATA command block or control of a track
block is being accessed. HDSEL# H19 O Head Select. Selects the side for R/W operations (0 = side 1, 1 = side
PDD[15-0] T17, R17, T18, IO Primary Disk Data 0)
T20, P17, N16, TRK00# H16 I Track 0. Sense to detect that the head is positioned over track 0.
R19, P18, R18,
R20, N17, P16, RDATA# H20 I Read Data. Raw serial bit stream from the drive for read operatrions.
T19, U20, R16, WDATA# J19 O Write Data. Encoded data to the drive for write operations.
T16 WGATE# J20 O Write Gate. Signal to the drive to enable current flow in the write
SDD[15-0]/ W18, V17, Y17, IO Secondary Disk Data / ISA Address head.
SA[15-0] W16, V15, Y15, DSKCHG# H18 I Disk Change. Sense that the drive door is open or the diskette has
W14, T15, U15, been changed since the last drive selection.
U16, V14, W15, WRTPRT# H17 I Write Protect. Sense for detection that the diskette is write protected
Y16, V16, W17, (causes write commands to be ignored)
Y18 See also Parallel Port pin descriptions for optional Floppy Disk interface functionality

Game Port Interface

Signal Name PIN # I/O Signal Description
JAX J1 I Joystick A X-axis
JAY K4 I Joystick A Y-axis
JBX K5 I Joystick B X-axis
JBY J2 I Joystick B Y-axis
JAB1 / GPI28 G3 I Joystick A Button 1. Device 0 Function 0 Rx53[7] = 0.
JAB2 / GPO12 H5 I Joystick A Button 2. Device 0 Function 4 RxE5[4] = 1.
JBB1 / GPI29 F1 I Joystick B Button 1. Device 0 Function 0 Rx53[7] = 0.
JBB2 / GPO13 H4 I Joystick B Button 2. Device 0 Function 4 RxE5[4] = 1.
See Function 0 Rx77[6]
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Serial Port and Infrared Interface Parallel Port Interface

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
TXD B15 O Transmit Data. Serial port transmit data out. PINIT#/ DIR# B12 IO / O Initialize. Initialize printer. Output in standard mode, I/O in
RXD E14 I Receive Data. Serial port receive data in. ECP/EPP mode.
STROBE#/ nc A11 IO / - Strobe. Output used to strobe data into the printer. I/O in
IRTX/ GPO14 R8 O / O Infrared Transmit. IR transmit data out (Function 4 RxE5[5] = ECP/EPP mode.
1) selectable from serial port 1, 2, or 3. E11 IO / O Auto Feed. Output used to cause the printer to automatically
AUTOFD#/
IRRX/ GPO15 U8 I / O Infrared Receive. IR receive data in (Function 4 RxE5[5] = 1) DRVEN0 feed one line after each line is printed. I/O pin in ECP/EPP
selectable to serial port 1, 2, or 3. mode.
IRRX2/ GPIOB T8 I Infrared Receive. IR receive data in (see FIR I/O Rx33 and 34) SLCTIN#/ D12 IO / O Select In. Output used to select the printer. I/O pin in ECP/EPP
RTS# A15 O Request To Send. Indicator that the serial output port is ready STEP# mode.
to transmit data. Typically used as hardware handshake with SLCT/ WGATE# E13 I / O Select. Status output from the printer. High indicates that it is
CTS# for low level flow control. Designed for direct input to powered on.
external RS-232C driver. ACK# / DS1# B14 I / O Acknowledge. Status output from the printer. Low indicates
CTS# B16 I Clear To Send. Indicator to the serial port that an external that it has received the data and is ready to accept new data
communications device is ready to receive data. Typically used ERROR#/ F11 I / O Error. Status output from the printer. Low indicates an error
as hardware handshake with RTS# for low level flow control. HDSEL# condition in the printer.
Designed for input from external RS-232C receiver. BUSY/ MTR1# A14 I / O Busy. Status output from the printer. High indicates not ready to
DTR# A16 O Data Terminal Ready. Indicator that serial port is powered, accept data.
initialized, and ready. Typically used as hardware handshake PE/ WDATA# D13 I / O Paper End. Status output from the printer. High indicates that it
with DSR# for overall readiness to communicate. Designed for is out of paper.
direct input to external RS-232C driver. PD7/ nc, C14 IO / - Parallel Port Data.
DSR# D14 I Data Set Ready. Indicator to serial port that an external serial PD6/ nc, A13 IO / -
communications device is powered, initialized, and ready. PD5/ nc, B13 IO / -
Typically used as hardware handshake with DTR# for overall PD4/ DSKCHG#, C13 IO / I
readiness to communicate. Designed for direct input from PD3/ RDATA#, E12 IO / I
external RS-232C receiver. PD2/ WRTPRT#, A12 IO / I
DCD# D15 I Data Carrier Detect. Indicator to serial port that an external PD1/ TRK00#, C12 IO / I
modem is detecting a carrier signal (i.e., a communications PD0/ INDEX# D11 IO / I
channel is currently open). In direct connect environments, this As shown by the alternate functions above, in mobile applications the parallel port pins can optionally
input will typically be driven by DTR# as part of the DTR/DSR be selected to function as a floppy disk interface for attachment of an external floppy drive using the
handshake. Designed for direct input from external RS-232C parallel port connector (see Super I/O Configuration Index F6[5]).
receiver.
RI# C16 I Ring Indicator. Indicator to serial port that an external modem
Serial IRQ
is detecting a ring condition. Used by software to initiate
operations to answer and open the communications channel. Signal Name PIN # I/O Signal Description
Designed for direct input from external RS-232C receiver SERIRQ V9 I Serial IRQ.
(whose input is typically not connected in direct connect
environments).

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Conventional BIOS ROM / ISA Bus Interface Internal Keyboard Controller

Signal Name PIN # I/O Signal Description Signal Name PIN # I/O Signal Description
LA21/ USBOC3# Y13 O System Address Bus. Allows access to physical MSCK/ IRQ1 N2 IO / I MultiFunction Pin (Internal mouse controller enabled by F0
/ GPI21 / GPO21 W13 O memory devices (e.g., BIOS ROMs) up to 4 Mbytes. Rx51[2])
LA20/ USBOC2# F4 RxE4[6] = 1. Rx51[2]=1 Mouse Clock. From internal mouse controller.
Rx51[2]=0 Interrupt Request 1. Interrupt 1 (external KBC).
/ GPI20 / GPO20
MSDT/ IRQ12 N4 IO / I MultiFunction Pin (Internal mouse controller enabled by F0
SA[19:18], V13, U13, IO System Address Bus. These address lines are used
Rx51[2])
SA17/ strap, T13, to interface to BIOS ROMs but may also be used to Rx51[2]=1 Mouse Data. From internal mouse controller.
SA16/ strap, Y14, implement a subset of the ISA bus if required. Rx51[2]=0 Interrupt Request 12. Interrupt 12 (ext PS2 mouse
SA[15:0]/ W18, V17, Y17, SA[19-16] are connected to ISA bus SA[19-16] ctlr).
SDD[15:0] W16, V15, Y15, directly. SA[19-17] are also connected to LA[19-17] KBCK/ A20GATE M4 IO / I MultiFunction Pin (Internal keyboard controller enabled by F0
W14, T15, U15, of the ISA bus. Rx51[0])
U16, V14, W15, SA17 strap – 0/1 = Enable / Disable Auto Reboot Rx51[0]=1 Keyboard Clock. From internal keyboard controller
Y16, V16, W17, SA16 strap – 0/1 = Disable / Enable LPC ROM Rx51[0]=0 Gate A20. Input from external keyboard controller.
Y18 KBDT/ KBRC N1 IO / I MultiFunction Pin (Internal keyboard controller enabled by F0
Rx51[0])
SD[7-0] T11, R11, U11, IO System Data. SD[7:0] provide the data path for Rx51[0]=1 Keyboard Data. From internal keyboard controller.
U12, Y12, W12, BIOS ROMs and other 8-bit devices residing on the Rx51[0]=0 Keyboard Reset. From external keyboard controller
V12, R12 ISA bus. (KBC) for CPURST# generation
IOR#/ GPI22/ U7 IO I/O Read. Command to ISA I/O slave devices to KBCS#/ ROMCS# T9 O / O Keyboard Chip Select (Rx51[0]=0). To external keyboard
GPO22 indicate that the controller chip.
slave may drive data on to the ISA data bus. F4
RxE4[7] = 1.
IOW#/ GPI23 / T7 IO I/O Write. Command to ISA I/O slave devices to Chip Selects
GPO23 indicate that the slave may latch data from the ISA Signal Name PIN # I/O Signal Description
data bus. F4 RxE4[7] = 1.
MEMR# W9 IO Memory Read. Command to memory slave to ROMCS#/ KBCS# T9 O/O ROM Chip Select (Rx51[0]=1). Chip Select to the BIOS
indicate that it may drive data onto the ISA data bus. ROM. See also Device 0 Rx40[5-4] and Rx41.
MEMW# Y9 IO Memory Write. Command to memory slave to MCCS#/ GPO17/ W6 O / IO Microcontroller Chip Select (Device 0 Function 4
indicate that it may latch data from the ISA data bus. strap RxE4[3] = 0). Asserted during read or write accesses to
I/O ports 62h or 66h.
IRQ1/ MSCK N2 I Interrupt 1 (optional external Keyboard
Strap: 0/1 = Enable / Disable CPU Frequency Strapping
Controller).
PCS0#/ GPO16 Y6 O / IO / IO Programmable Chip Select 0. (Device 0 Function 4
IRQ12/ MSDT N4 I Interrupt 12 (optional external PS2 Mouse
RxE4[2] = 0). Asserted during I/O cycles to programmable
Controller).
read or write ISA I/O port ranges.
IRQ14 T14 I Interrupt 14 (IDE Primary Channel).
PCS1#/ GPI19/ G5 O / I / O Programmable Chip Select 1. (Device 0 Function 4
IRQ15 U14 I Interrupt 15 (IDE Secondary Channel). GPO19 RxE4[5] = 1)
SPKR U9 O Speaker Drive. Output of internal timer/counter 2.

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Hardware Monitoring Signal Name PIN # I/O Signal Description

Signal Name PIN # I/O Signal Description LID/ GPI4 V2 I/I Monitor Input - Notebook Computer Display Lid Open
UIC1 M1 Analog I Universal Input Channel. For temperature / voltage / Closed. Used by the Power Management subsystem to
monitoring. monitor the opening and closing of the display lid of
UIC2 M3 Analog I Universal Input Channel. For temperature / voltage notebook computers. Can be used to detect either
monitoring. low-to-high and/or high-to-low transitions to generate an
SMI#. The VT8231 performs a 200 usec debounce of this
UIC3 M2 Analog I Universal Input Channel. For temperature / voltage
input if Function 4 Rx40[5] is set to 1. (10K PU to VCCS
monitoring.
if not used)
UIC4 L4 Analog I Universal Input Channel. For temperature / voltage
RING#/ GPI3 U3 I/I Monitor Input – Modem Ring. May be connected to
monitoring.
external modem circuitry to allow the system to be
UIC5 L1 Analog I Universal Input Channel. For temperature / voltage
re-activated by a received phone call. (10K PU to VCCS if
monitoring.
not used)
DTD+ L2 Analog I CPU DTD (Thermal Diode) Channel Plus.
BATLOW#/ GPI5 T3 I/I Monitor Input - Battery Low. (10K PU to VCCS if not
DTD- L3 Analog I CPU DTD (Thermal Diode) Channel Minus. used)
VREF K1 O Voltage Reference for Thermal Sensing (2.2V ±5%) CPUMISS/ GPI16 V1 I/I Monitor Input - CPU Missing. Indicates whether the
CPU is plugged in correctly.
FAN1 K2 I Fan Speed Monitor 1. (3.3V only)
AOLGPI/ GPI17/ P3 I/I/I Monitor Input - Awake On LAN External Event. F4
FAN2/ SLPBTN#/ K3 I / I / I / O Fan Speed Monitor 2. (3.3V only) (F4 RxE5[0] = 0) THRM Rx40[7]=1
GPI18/ GPO18 INTRUDER#/ GPI8 F3 I/I Monitor Input – Chassis Intrusion.
DTEST/ GPIOD (30) Y1 O Hardware Monitor Digital Test Out
RSMRST# F2 I Resume Reset. Resets the internal logic connected to the
ATEST/ GPIOC (25) J2 O Hardware Monitor Analog Test Out VCCS power plane and also resets portions of the internal
/ CHSINOUT RTC logic.
SUSA#/ GPO1/ strap P1 O / O / I Suspend Plane A Control (Function 4 Rx54[2]=0).
Asserted during power management POS, STR, and STD
suspend states. Used to control the primary power plane.
(10K PU to VCCS if not used)
Power Management and External State Monitoring
SUSB#/ GPO2 P2 O / O Suspend Plane B Control (Function 4 Rx54[3]=0).
Signal Name PIN # I/O Signal Description Asserted during power management STR and STD
PME#/ GPI6 U1 I/I Power Management Event. (Rx74[1]=0) (1K PU to suspend states. Used to control the secondary power plane.
VCCS if not used) (10K PU to VCCS if not used)
EXTSMI#/ GPI2 W1 IOD / I External System Management Interrupt. When enabled SUSC#/ GPO N3 O / O Suspend Plane C Control. Asserted during power
to allow it, a falling edge on this input causes an SMI# to management STD suspend state. Used to control the
be generated to the CPU to enter SMI mode. (10K PU to tertiary power plane. Also connected to ATX power-on
VCCS if not used) (3.3V only) circuitry.
SMBALRT#/ GPI7 T2 I/I SMB Alert (System Management Bus I/O space Rx08[3]
= 1). When the chip is enabled to allow it, assertion
generates an IRQ or SMI or power management event.
(10K PU to VCCS if not used)
THRM/ AOLGP / P3 I / I / I Monitor Input - Thermal Alarm. (F4 Rx40[7]=0) (1K
GPI17 PU to VCCS if not used)

98
 7170 N/B MAINTENANCE
5.3 VIA VT8231 South Bridge Controller-12

Power Management and External State Monitoring

Signal Name PIN # I/O Signal Description
SUSST1#/ GPO3 N5 O/O Suspend Status 1 (Function 4 Rx54[4] = 0). Typically
connected to the North Bridge to provide information on
host clock status. Asserted when the system may stop the
host clock, such as Stop Clock or during POS, STR, or
STD suspend states. Connect 10K PU to VCCS.
SUSCLK/ GPO4 W2 O/O Suspend Clock (Function 4 Rx55[1]=0). 32.768 KHz
output clock for use by the North Bridge (e.g., Apollo
MVP3 or MVP4) for DRAM refresh purposes. Stopped
during Suspend-to-Disk and Soft-Off modes. Connect
10K PU to VCCS.

Resets, Clocks, and Clock Control

Signal Name PIN # I/O Signal Description
PWRGD E2 I Power Good. Connected to the PWRGOOD signal on the
Power Supply.
PWRBTN# U2 I Power Button. Used by the Power Management subsystem
to monitor an external system on/off button or switch. The
VT8231 performs a 200us debounce of this input if Function
4 Rx40[5] is set to 1. (3.3V only)
SLPBTN#/ FAN2/ K3 I/ I/ IO Sleep Button (Function 4 Rx40[6] = 0). Used by the power
GPIO18 management subsystem to monitor an external system sleep
button or switch. Connect to VCC if not used.
PCIRST# E4 O PCI Reset. Active low reset signal for the PCI bus. The
VT8231 will assert this pin during power-up or from the
control register.
RTCX1 E3 I RTC Crystal Input: 32.768 KHz crystal or oscillator input.
This input is used for the internal RTC and for power-well
power management logic.
RTCX2 F5 O RTC Crystal Output: 32.768 KHz crystal output
OSC T12 I Oscillator. 14.31818 MHz clock signal used by the internal
Timer.
SLOWCLK / R4 O Slow Clock. Frequency selectable if PMU function 4
GPO0 Rx54[1-0] is nonzero (set to 01, 10, or 11).
CPUSTP#/ GPO5 P4 O /O CPU Clock Stop (Function 4 RxE4[0] = 0). Signals the
system clock generator to disable the CPU clock outputs.
Not connected if not used. See also PMU I/O Rx2C[3].
PCISTP#/ GPO6 T4 O /O PCI Clock Stop (Function 4 RxE4[1] = 0). Signals the
system clock generator to disable the PCI clock outputs. Not
connected if not used.

99
 7170 N/B MAINTENANCE
6. System Block Diagram
X500 U1 Pentium III
U2 SH4
U503 SH16 SH4 / Celeron GL528SM
SMBDATA HCLK_CPU CPU Thermal Recorder
SMBCLK NBHCLK FC-PGA
-SUSA
SH9 SO-DIMM Module
DCLKO
-CPUSTP Clock
J8
DCLKI LCD PANEL J501 SH8
USBCLK Generator U501 SH6
SDRAMCLK[0..3]
SH22 SH9 J502
REFCLK0 TWISTER
ICS9248-195 SBPCLK
PCICLK J10 U511
TV S-VIDEO
OSC14M PCPCLK TV-Encoder
North bridge
FS1 MINPCICLK SH9 SDRAMCLK 0~3
14M_TV NBPCLK
J4
CRT 552 BGA
3.3V PCI BUS

J14 J26,J27 SH15

SH14 U21 SH14 USB
PCMCIA / J503 SH13 Line In
PCMCIA/ J20 SH12
SH13
CARDBUS U5 CARDBUS HDD SH10 QTC
U12 Internal
SLOTS CP2211 CONTROLLER
J13 SH12 U18 SPK.
Power Switch PCI 4410 CDROM U16 TPA
VT8231 ALC200 0202
AC Link
Print Port South bridge Line Out
J3 324 mBGA Phone Jack
SH14 U500 IR Module SH18
Internal MIC.
TSB41AB1
1394 PHY J18
U25 RJ-11 Jack External MIC.
RJ45
LSI 80277 M.D.C
SH14 ISA BUS

SH15 PS/2 KBD

PS/2 MOUSE
U8 SH17
SYSTEM
Internal Keyboard U502
BIOS H8/34347
Micro Controller
FAN
Power Button

Touch PAD

100
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic

7.1 Introduction
Every time the computer is turned on ,the system BIOS runs a series of internal checks
on the hardware. This power-on self test (post) allows the computer to detect problems
as early as the power-on stage. Error messages of post can alert you to the problems of
your computer.

If an error is detected during these tests, you will see an error message displayed on
the screen. If the error occurs before the display, then the screen cannot display the
error message. Error codes or system beeps are used to identify a post error that occurs
when the screen is not available.

The value for the diagnostic post(378H) is written at the beginning of the test.
Therefore , if the test fail, the user can determine where the problem occurs by reading
the last value written to post 378H by the PIO debug board plug at PIO port.

101
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.
Phoenix BIOS Function Keys
The following are the special PhoenixBIOS function keys :
F2 Enter SETUP program during POST
Ctrl - Alt <- > Switch to slow CPU speed
Ctrl - Alt <+> Switch to fast CPU speed
The speed switching keys are only operational when speed switching is available.

POST Errors and Beep Codes

Recoverable POST Errors
Whenever a recoverable error occurs during POST, Phoenix BIOS displays an error message describing the
problem.Phoenix BIOS also issues a beep code (one long tone followed by two short tones) during POST if the
video configuration fails (no card installed or faulty) or if an external ROM module does not properly checksum to
zero. An external ROM module (e.g. VGA) can also issue audible errors, usually consisting of one long tone
followed by a series of short tones.

Terminal POST Errors

There are several POST routines that issue a POST Terminal Error and shut down the system if they fail. Before shutting
down the system, the terminal-error handler issues a beep code signifying the test point error, writes the error to port 80h,
attempts to initialize the video, and writes the error in the upper left corner of the screen (using both mono and color
adapters.) 102
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.

The routine derives the beep code from the test point error as follows :

1. The 8-bit error code is broken down to four 2-bit groups (Discard the most significant group if it is 00)
2. Each group is made one-based (1 through 4 )by adding 1.
3. Short beeps are generated for the number in each group example :
Testpoint 01Ah = 00 01 10 10 = 1-2-3-3 beeps

Test Points and Beep Codes

At the beginning of each POST routine, the BIOS outputs the test point error code to I/O address 80h.Use this code during
trouble shooting to establish at what point the system failed and what routine was being performed. Some motherboards
are equipped with a seven-segment LED display that displays the current value of port 80h. For production boards which
do not contain the LED display, you can purchase a card that performs the same function. If the BIOS detects a terminal
error condition, it halts POST after issuing a terminal error beep code (See above) and attempting to display the error code
on upper left corner of the screen and on the port 80h LED display. It attempts repeatedly to write the error to the screen.
This may cause "hash" on some CGA displays. If the system hangs before the BIOS can process the error, the value
displayed at the last test performed. In this case, the screen does not display the error code. The following is a list of the
checkpoint codes written at the start of each test and the beep codes issued for terminal errors. Unless otherwise noted,
these codes are valid for PhoenixBIOS 4.0 Release 6.0.

103
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.

CODE Beeps POST Routine Description CODE Beeps POST Routine Description
02h Verify Real Mode 29h Initialize POST Memory Manager
03h Disable Non-Maskable Interrupt (NMI) 2Ah Clear 512 KB base RAM
04h Get CPU type 2Ch 1-3-4-1 RAM failure on address line xxxx*
06h Initialize system hardware 2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of
08h Initialize chipset with initial POST values memory bus.
09h Set IN POST flag 2Fh Enable cache before system BIOS shadow
0Ah Initialize CPU registers 30h 1-4-1-1 RAM failure on data bits xxxx* of high byte of
0Bh Initialize CPU cache memory bus.
0Ch Initialize caches to initial POST values 32h Test CPU bus-clock frequency
0Eh Initialize I/O component 33h Initialize Phoenix Dispatch Manager
0Fh Initialize the local bus IDE 36h Warm start shut down
10h Initialize Power Management 38h Shadow system BIOS ROM
11h Load alternate registers with initial POST values 3Ah Autosize cache
12h Restore CPU control word during warm boot 3Ch Advanced configuration of chipset registers
13h Initialize PCI Bus Mastering devices 3Dh Load alternate Register with CMOS Values
14h Initialize keyboard controller 42h Initialize interrupt vectors
16h 1-2-2-3 BIOS ROM checksum 45h POST device initialization
17h Initialize cache before memory Autosize 46h 2-1-2-3 Check ROM copyright notice
18h 8254 timer initialization 48h Check video configuration against CMOS
1Ah 8237 DMA controller initialization 49h Initialize PCI bus and device
1Ch Reset Programmable interrupt Controller 4Ah Initialize all video adapters in system
20h 1-3-1-1 Test DRAM refresh 4Bh QuietBoot start (optional)
22h 1-3-1-3 Test 8742 Keyboard controller 4Ch Shadow video BIOS ROM
24h Set ES segment register to 4 GB 4Eh Display BIOS copyright notice
26h Enable A20 line 50h Display CPU type and speed
28h Auto size DRAM 51h Initialize EISA board
104
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.

CODE Beeps POST Routine Description CODE Beeps POST Routine Description
52h Test keyboard 83h Configure non-MCD IDE controllers
54h Set key click if enabled 84h Detect and install external parallel ports
58h 2-2-3-1 Test for unexpected interrupts 85h Initialize PC-compatible PnP ISA devices
59h Initialize POST display service 86h Re-initialize onboard I/O ports
5Ah Display prompt "Press F2 to enter SETUP" 87h Configure Motherboard Configurable Devices
5Bh Display CPU cache (optional)
5Ch Test RAM between 512 and 640 KB 88h Initialize BIOS Data Area
60h Test extended memory 89h Enable Non-Maskable Interrupts (NMIs)
62h Test extended memory address lines 8Ah Initialize Extended BIOS Data Area
64h Jump to User Patch1 8Bh Test and initialize PS/2 mouse
66h Configure advanced cache registers 8Ch Initialize floppy controller
67h Initialize Multi Processor APIC 8Fh Determine number of ATA drives (optional)
68h Enable external and CPU caches 90h Initialize hard-disk controllers
69h Setup System Management Mode (SMM) area 91h Initialize local-bus hard-disk controllers
6Ah Display external L2 cache size 92h Jump to User Patch2
6Bh Load custom defaults (optional) 93h Build MPTABLE for multi-processor boards
6Ch Display shadow-area message 95h Install CD ROM for boot
6Eh Display possible high address for NMB recovery 96h Clear huge ES segment register
70h Display error messages 97h Fixup Multi Processor table
72h Check for configuration errors 98h 1-2 Search for option ROMs. One long, two short
76h Check for keyboard errors beeps on checksum failure
7Ch Set up hardware interrupt vectors 99h Check for SMART Drive (optional)
7Eh Initialize coprocessor if present 9Ah Shadow option ROMs
80h Disable onboard Super I/O ports and IRQs 9Ch Set up Power Management
81h Late POST device initialization 9Dh Initialize security engine (optional)
82h Detect and install external RS232 posts 9Eh Enable hardware interrupts
105
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.

CODE Beeps POST Routine Description CODE Beeps POST Routine Description
9Fh Determine number of ATA and SCSI drives C6h Initialize note dock (optional)
A0h Set time of day C7h Initialize note dock late
A2h Check key lock C8h Force check (optional)
A4h Initialize typematic rate C9h Extended checksum (optional)
A8h Erase F2 prompt D2h Unknown interrupt
AAh Sean for F2 key stroke The following are for boot block in Flash
ACh Enter SETUP E0h Initialize the chipset
AEh Clear Boot flag E1h Initialize the bridge
B0h Check for errors E2h Initialize the CPU
B2h POST done-prepare to boot operating system E3h Initialize system timer
B4h 1 One short beep before boot E4h Initialize system I/O
B5h Terminate QuietBoot (optional) E5h Check force recovery boot
B6h Check password (optional) E6h Checksum BIOS ROM
B9h Prepare Boot E7h Go to BIOS
BAh Initialize DMI parameters E8h Set Huge Segment
BBh Initialize PnP Option ROMs E9h Initialize Multi Processor
BCh Clear parity checkers EAh Initialize OEM special code
BDh Display MultiBoot menu EBh Initialize PCI and DMA
BEh Clear screen (optional) ECh Initialize Memory type
BFh Check virus and back up reminders EDh Initialize Memory size
C0h Try to boot with INT 19 EEh Shadow Boot Block
C1h Initialize POST Error Manager (PEM) EFh System memory test
C2h Initialize error logging F0h Initialize interrupt vectors
C3h Initialize error display function F1h Initialize Run Time Clock
C4h Initialize system error handler F2h Initialize video
C5h PnPnd dual CMOS (optional) F3h Initialize System Management Manager
106
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic
7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board.

CODE Beeps POST Routine Description

F4h Output one beep
F5h Boot to Mini DOS
F6h Clear Huge Segment
F7h Boot to Full Dos
* If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error),
it displays and additional word-bitmap (xxxx) indicating the address
line or bits that failed. For example, "2C 0002" means address line
1 (bit one set) has failed. "2E1020" mean data bits12 and 5 (bits 12
and 5 set) have failed in the lower 16 bits. Note that error 30 cannot
occur on 386SX systems because they have a 16 rather than 32-bit
bus. The BIOS also sends the bitmap to the port-80 LED display.
It fist displays the check point code, followed by a delay, the high-
order byte, anther delay, and then the low-order byte of the error.
It repeats this sequence continuously.

107
 7170 N/B MAINTENANCE
7. Maintenance Diagnostic

7.3 Diagnostic Tools :

LED * 8 OR

PIO CONNECTOR * 1

P/N:411904800001
7.4 CIRCUIT: DESCRIPTION :PWA;PWA-378PORT DEBUG BD
Note:Order it from MIC/TSSC

25 14 PIN1 : STROBE PIN 13 : SLCT

PIO
CONNECTOR 13 1
PIN10: ACK# PIN 16 : INT#

PIN11: BUSY PIN 17 : SELIN#

PIN12: PTERR PIN 14 : AUTOFD#

LED PIN{9:2}: PD{7:0}

108
 7170 N/B MAINTENANCE
8. Trouble Shooting

8.1 No Power

8.2 No Display

8.3 VGA Controller Failure

8.4 Memory Test Error

8.5 Keyboard(K/B) , Touch-pad(T/P) , ESB Test Error

8.6 CD-ROM Drive Test Error

8.7 Hard Drive Test Error

8.8 USB Port Test Error

8.9 PIO Port Test Error

8.10 Audio Failure

109
 7170 N/B MAINTENANCE
8.1 No Power:
When the power button is pressed, nothing happens ,power indicator does not light up.

1. Check AC Adaptor.
2. Check D/D Board. Power Jack

D/D BOARD 22.5V 2.67A

OUTLET

MOTHER BOARD

J509
Please Reference Next Page
For Power Diagram

110
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.
PWR_ON
From H8
SC1402&MAX1632
VCC3
J4 PQ1 ADINP PD1,PD2 Shut Down
ADAPTOR Self SH2 Protector 3.3V DC to DC Convertor
SH2 Discharge Diode SH2
VCC5
From H8 ON5
learning 5V DC to DC Convertor
SH21
PU5 VCC12
J16 D/VMAIN
Discharge P Channel Regulator
Battery MOSFET
Pack SH21 SI4835DY VCC CORE
Vcc Core DC to DC Convertor
PU504
MAX1717 SH20
PD505 VTT
Diode VCC25 VDD5
VTT DC to DC Convertor SH20 PU4
SC1401
Charge

Always PU6
Regulator
SH22
PU505 LP2951
PD5 SH22
SH21
P Channel Choke Protector
MOSFET Diode
SI4835DY

Resistor

PU508
CHARGE Charge
SH22 CV
PU506 SWITCH
CC R Sense Resistor SI4925DY
PWM
Charge IC CC SH22
TL594C

111
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

VDD5
Step1 : Connect Adaptor to ( D/D BD ) J4 & O/P “ALWAYS”.
PR9
Step2 : “ALWAYS” --> PU6 Generate VDD5 & VDD3. PQ4
470K

DTC144WK 3
Step3 : H8 O/P “LEARNING” for Charger Circuitry.
3V Resume Power 5V Resume Power 2
VDD3 VDD5 1 PC22
Step4 : For MOSFET “PQ1” G=0,D<-->S. U4
3 2 0.1U
C24 VOUT VIN 1 50V
Step5 : O/P “ADINP”& “DVMAIN”. 2.2U GND
+80-20%
VCC5
TC55RP3302EMB

PL5
120Z/100M PQ3
G
ALWAYS JS4 8
2 IN PU6 5VTAP 61 S D
SHORT-SMT4 7 SENSE OUT 5
F/B ERR- 4 PC19 SI2301DS
PD505 3 PC20
SW_VDD5 SHUTDN GND
2 0.1U 10U
3
LP2951-02BM 50V 10V
1
ALWAYS BAV70LT1
PL503 PQ1
SI4835DY
120Z/100M 8
J4 3 7
PL504 PF501 2 6
1 1 5
2 120Z/100M
S D ADINP
3 6.5A/32VDC K G To Next Page
PC3 PC503 PR4 PD502 PR5 4
0.1U 0.1U 10K 470K
A RLZ24D PD2
50V A K
VDD5 H8_VDD5 50V DVMAIN
EC31QS03L
+PC11 PC23 PR7 PD504
100U PD1 PC13 1
VCC_CORE 25V 1000P 10K A K PC17 3
PR3 2 ALWAYS
D

EC31QS03L 0.1U 1000P

470K
SH17 LEARNING PR6 PQ501 50V BAV70LT1
G
47K
U502 2N7002
S

PR507
100K
H8-34347

112
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.
PL7
DVMAIN PR504
DVMAIN
PU2 PWR_ON PR519 10

PL8 +PC8 SI4800DY 4 0

DVCC3T 100U
G PC525 PR516
25V
5 D S 1 PR515
0.1U 1K
6 2 1K
VCC3 PL502 7 3
50V
8
BEAD PL1
PL10 PR2 PR517
1M
PC12 .02 ETQP_CDRH125
PR505 1% PU4 4
SI4832DY PU501
100P 32.4K
PL9 PC513 1%
G 1 28
+ 5 D S 1 CSH3 RUN/ON3 PC511
6 2 2 27 0.1U
7 3 CSL3 DH3
8 FB33 26 50V
PC21 PC22
PC15 PR506
100U/H2.8 FB3 LX3
10V 100K 4 25
4.7U 0.1U 1% 12OUT BST3
16V 50V 1000P +RAW_15V 5 24
VDD DL3 JS2 5VALWAYS
6 23
SYNC SHDN
A5 PD501 +RAW_15V 7
TIME/ON5 V+
22 SHORT-SMT3
A K 1
8 21 3
EC11FS2 PL501 GND VL 2 PD503
9 20
+12V PC4 PR514 REF PGND BAW56
PC504 + 10 19
0.1U 100U SKIP DL5
50V 25V 0 11 18
RESET BST5
4 FB5 12
BKL_VMAIN PC10 PC24 17
G FB5 LX5
VCC5 DVCC5T + S 1
0.1U 5 D 13 16 PC510
100U 50V 6 2 CSL5 DH5
0.1U
25V 7 3 14 15 50V
CSH5 SEQ
JS1 8
SI4800DY MAX1632 SSOP28A
PL4 PU1
SHORT-SMT3
PT1 2 4 PC508
PL6 1U
1 3

PR502 PR1 10UH PU3 4

100K IND_CDRH125B
PL5 .02 G
1% 1% 5 D S 1
6 2
+ PC506 7 3
PC6 PC14 8
100U/H2.8
10V SI4832DY
4.7U PR501
16V 0.1U 97.6K
50V 1%
DVMAIN-->PU501-->O/P
+12V & VCC3 & VCC5
113
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

U1 Pentium III
/ Celeron PVID[0:3]
SH4
CPU
FC-PGA
PL13
120Z/100M
DVMAIN DVMAIN-->PU504-->O/P
PC10
PL14 0.01U
PC503 PC504 PC8
+
PC506 PC507 +
PC9 VCC_CORE ( CPU Core )
10U 10U 100U 0.1U 0.1U 100U
120Z/100M 25V 25V 25V 50V 50V 25V
20% 20%
DVCC5T
RP503 10K*4 0
1 8 DVCC5D DVCC5T
PVID3 2 7
PVID2 3 6 PR508 VCC_CORE
PVID1 4 5 PC509 22 PR511 C1
PVID0
PL8
5VALWAYS PD502 PC513
15

0.22U

5
6
7
8

5
6
5
6
7

7
8
7

MA3X701 1U PL9
VCC

VDD

17 1 D PU2 D PU503 D PU501

D4 V+
18
D3 G IR7811A G IR7811A G IR7811A
PD1
19
D2
1 PL10
20 PU504 22 PC514 4 4 4 3
21 D1 BST 2
D0
PR512 0.22U
16V S S S
PL11
10K 16 24 BAW56
A/B DH
PL1

1
2
3

1
2
1
2
3

3
DVCC5T PR15.005 1% PL12
23
PR506 10K 2 LX 0.6UH
PR513 SKP/SDN ETQP6F
PR520

K
8

5
6
7
8

5
6
5
6
7

7
8
100K
14 30% PR16

K
10K DL
PR503 PR507 100K 1% D PU500 D PU502 D PU1
3 PC515 SI4404 SI4404 SI4404 PD500 PD7
100K TIME 13 0.1U G G G EC31QS03L .005 EC31QS03L
220P GND 4 4 4 1%
PC508

A
6 4
CC FB

A
0.22U S S S
9 5 PC1
REF FBS

1
2
3

1
2
1
2
3

3
PC510 DVCC5D PR505 PC6 +
PC2 PC7
8
TON GNDS
11 PC3 4.7U
0.1U
PR509 1K R507 1K 1% 50V 2.5V 16V
10 12 TP558 20%
ILIM VGATE
150U
8.06K MAX1717
1% PR510 QSOP24A PR504
47.5K 169K
1% 1%

114
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

DVMAIN-->PU4-->O/P
DVMAN DVCC3T PC536 PC535 +PC12
0.1U 100U
VCC2.5 & VTT ( CPU Core )
0.01U 50V 25V
PC18 PC17

4
0.1U 4.7U PQ1
50V 16V
PR2 1 MTD20N03HDL
10 DPAK PL500

3
1 2
VCC2.5

K
DVCC5T SHORT-SMT4
PU4 PR521 PC519 + PC521 PD503
1 20 20K
PR517 SYNC PSAVE 0.1U 56U
2 19 1% 50V RLZ2.7B
SHDN RESET 4V

A
10K 3 18
FB ENABLEIO
4 17
VDD1 IOS
5 16 PU3

8
GND GATEIG PR518
6
CSL VDD2
15 18.7K
1%
D1 VTT
7
CSH BST
14 PL3
1 PL2
DVCC5T 8
V5V DH
13 G1 D2 5 PR1 120Z/100M
6 F1 1 2
9 12 7
PC516 PC518 DL PHASE .02
10 11 PC517
2.2UH 1% PR558 + PC11 PC16
0.1U 4.7U PGND0 PGND1 SS1005-2R2NSB
50V 16V 4 10K 150U 0.1U
SC1401CSS 0.1U 2.5V
SSOP20 G2 1% 50V
50V 20%
S2 A
SI4816DY

2
3
PD2 SO8
A K PR557
47.5K
1%
BAS32L

I1
I2

115
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

ADINP
To Next Page Q10
3
R1
BATT_DEAD
1
DTC144TKA
VDD5S
PU5 DVMAIN
SI4835DY
8
3 7
DVMAIN 2 6 DBATT DBATT PR555
1 100K
S D 5

8
G PR548
PR6 VDD5S 475K 3 +
4

1% 1
-BATT_DEAD 2 -
100K VDD5
PR550 PU509A
PR525 PR554 LMV393M

4
SH17
402K PR556 PR553 PC533
10K 1% 100K 324K
D 100K 0.1U

8
PR527 1% 1% 50V
D

PQ502 100K 5 + D PQ508

D -ADEN BAT_T 7 G S 2N7002
2N7002 S G U502 6 -
S
PU509B
S

3 H8-34347 LMV393M

4
PR524 ADINP PR549
PQ503 2 100K
PL7 1%
DTC144WK 169K
1%
120Z/100M
1

PL6 PF1
J16 PR547
120Z/100M VDD5S
1 6.5A/32VDC PC24 PR552
1 2 1% 1M
2 3 301K
3 4 0.1U 1%
4 PR13 0 50V
5
5 PC29 PC25 VDD5S BAT_V
6 PR544
6
1000P 0.01U 4.7K

8
6P/2.5MM/H4
CEN
PR551 PC534 PR545 12.1k
SB-06A-4.0-A2
PR11 100K 3 + -LI_OVP
4.99K 0.1U 1
1% 2 1%
1% 50V 2 -
PQ507 PU507A
BAT_T 1 PR536 4
LMV393M
402K PR535 PC532 To Next Page
SCK431LCSK-5 1% 43.2K 0.1U
3 1% 50V
PC26 PC30 PR12
20K
0.1U 1000P DBATT
50V 1%

116
 7170 N/B MAINTENANCE
8.1 No Power:
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

PU505
PU508

4
8 SI4925DY
Continue… ADINP 3 7 PD5
2 6 PL4 6 3
L5 1 5 L6 L7 A K 5 PR546 PR543

D
S
PQ506

D
PR7 PR8 33UH

G
EC31QS03L

K
10K 10K PC21 8 100K 10K D
SI4835DY PC522 -LI_OVP

4
PD4 + 100U 7 1 S G
PR5 0.1U
EC31QS03L 25V

S
C PQ2 100K 50V 2N7002
B

2
E
PD3 MMBT2222A
K A DBATT
PR522 PR540 PC23
10K BAS32L 11.8K 10U Continue…
MLL34B 1% 25V
PR523 E 20%
B PQ500
C 2IN+
33K MMBT3906L
PR541
D

8.06K PR538 PR539

-LI_OVP D PC525 PU506 1% 453K 210K
G S 9 8 PQ504A

4
PQ501 0.1U 10 E1 C1 7 NDC7002N 1% 1%

4
E2 PWM GND
S

2N7002 50V 11 6
12 C2 RT 5 PR532 PR533 PR537 PQ505A
13 VCC CT 4 121K 1K 1K 3 NDC7002N VADJ1 SH17
14 OUTPUTCTRL DTC 3 1% 1% 3
PR526 15 REF FEEDBACK 2 L9 1%
2IN- 1IN-

2
16 1 PQ505B
PR530

6
47K 2IN+ 1IN+

2
PC523 PR528 PC524 PR529 6.19K U502
CHARGING TL594C SO16 1U 100K 1000P 10K PQ504B
1% VADJ2
JS502 10% 1% 1 H8-34347

6
PR534 PC530 NDC7002N
PC526

5
SHORT-SMT1 0.1U NDC7002N PWR_ON
0 50V 1
PR531 PC529 0.01U
0.1U

5
10K 50V

PC527
0.1U
50V

117
 7170 N/B MAINTENANCE
8.2 No Display
There is no display on both LCD and monitor

No Display

Plug PIO debug board to PIO

port and get the 378h error code.
1. Check if power system is O.K .
2. Remove all the I/O device
from system.

Is there YES Refer to the error

YES Connect the I/O device any error code code description
Reboot & cables to the system shown on debug and find out the
and display one at a time to find out board ? error.
OK? the faulty parts then
replace and end. NO
NO

Check system clock or reset

Check switch setting or replace
circuit and major chip for any
a known good battery.
cold solder.

NO
Reboot
and display Replace motherboard or into
OK? board-level Troubleshooting.

YES

Replace the faulty parts then end.

118
 7170 N/B MAINTENANCE
8.2 No Display ******System Clock Check ******

U1 SH4
BSEL1
VCC3 FC-PGA J501 J502
VCC3 SO-IMM SO-IMM
CPU
R559 BSEL0 SDRAMCLK2
10K Socket 370 SDRAMCLK1
61 74
R625
10K
14 U508A R560
BSEL0 1 2
10K SH8
R525 R534 SDRAMCLK0
7
SDRAMCLK3
PICCLK HCLK_CPU 74 61
74LVX07
VCC3 VCC3
OSC14M
R512 14 U508C R627
10K 10K R564
BSEL1 5 6
10K R548
FS0 2 45 35
7 26
74LVX07 FS1 10 R553
25
34
NBHCLK R532 10
SH6 46 R538 10
38
U501 NBPCLK R539 22
SH16 R540
12 10
R74 10
37
DCLKO
15 10
TWISTER DCLKI R536 10 R535 U21 SH14
39 PCPCLK
North Bridge R528 22
10
PCI 4410
REFCLK0
48 U503 22
PCMCIA-Controller
R672 22 FS2
MINIPCICLK R537
SH9 U511 ICS9248-195 J503
SH19
14M_TV R529
11 QTC
CH7005C 10K
Clock generator 22
R671 0
TV Encoder VCC3 5
R523
R526 4 1M
VCC3 U503 ICS9248-195
X500
10K R531 22
14.318MHz 30
SH10 SBPCLK 7 VCC3
L36 36
R153 1 C549 C551 VCC2.5 L506
-CPUSTP 41 10P 10P SH16 1
47 6
OSC14M U12 -PCISTP 20 FS3 R527 L508 14
VCC3
USBCLK R556 22 FS0 R537 10K VCC3
R524 22 SDATA SCLK 10K 7
VT8231 23 24
L510
GND 19
South Bridge SMBDATA VCC3
L511
SMBCLK
27
119
 7170 N/B MAINTENANCE
8.2 No Display ******Reset System ******
SH6 SH9 SH18
VDD5 H8_VDD5 PWROK
U501 -PCIRST
U511 U25
VCC_CORE TWINSTER CH7005C LSI80227
North Bridge TV_Encoder LAN PHY
For H8-3434F Reset SH17 VCC2.5
VDD5 U504 U505 -PCIRST
R153
ADM809 SH17

2
-CPURST

Level Shift
-H8_RESET R1
3
VCC RESET 2 1 SH4
H8_PWROK PWROK
GND 21 5 4 1 3 U1 VCC3
1 R549 DTC144TKA
FC-PGA SH14
100K Q9 -PCIRST
1
U26 5
-CBRST U21
PIII CPU NC7S08
U502 4
PCI 4410
SN74CBTD3384
PCMCIA Controller
SH11
H8-34347 VCC5
7170 SH22
PWR_ON H8_PWRON VDD3 PWROK U12

3
14
-PCIRST
-H8_MVP4BT 3 2 Q4
Power 2 R1 Q22 VT8231 DTC144WK
18
Module DTC144TKA
-MVP4BT
South Bridge J20
1 RP34 33*8

1
RPX8
1 16 1
2 15
R255 3 14 -BRSTDRV-1
23 4 13
10K R57 5 12
-ACRST 1M 6 11
7 10
8 9

SH13
J9 U16 RP37
-ACRST 33*8 RPX8
1 16
-PWRSW R554 -POWERBTN ALC200 2 15
5
3 14 -BRSTDRV-2
1K C570 Audio Codec 4
5
13
12
6 11
0.1U 7 10
J503 8 9
Easy Start J13
Button J18 SH18 -PCIRST SH19
CONN

-ACRST -ACRST QTC

MDC
Modem

120
 7170 N/B MAINTENANCE
8.3 VGA Controller Failure
There is no display or picture abnormal on LCD or monitor.
VCC3 NDS9410 Q500
8
SH6 7 3 L502 LCDVCC 2 1 LCDVCC
6 2 4 2 1 3
5 1 6 4 3 5
120Z/100M
D S TXCLK+ 8 6 5 7 TX2CLK+
LCDVCC G C506 C503 C505 C501 TXCLK- 10 8 7 9 TX2CLK-
C509 12 10 9 11
10U 0.1U 1000P 1000P
TXCLK+- 0.1U +12V TX2OUT1+ 12 11 TX2OUT0+
TX2CLK+- 50V R506
4
10V 50V TX2OUT1-
14
16
18
14
16
13
15
13
15
17
TX2OUT0- LCD
TXOUT0+ 20 18 17 19 TX2OUT2+
TXOUT[0:2]+- 470K
TXOUT0- 22 20 19 21 TX2OUT2-
22 21
TX2OUT[1:2]+- Q501R1 3
TXOUT1+
24
24 23
23
TXOUT2+
2 26 25
26 25
1 TXOUT1- 28 27 TXOUT2-
30 28 27 29
ENPVDD DTC144TKA 30 29

DF13-30DP-1.25V J8
ENPBLT ENPBLT1 L6
J3
BKL_VMAIN L5 1
2
BLADJ L4

Inverter
3
U501 U502 BLADJ
4
5
C2 6
H8-34347 0.1U 7
8
50V
9
VT8603 L3 10

VDD5S C1 INVERTER BD.

S3 J10 PJ2 0.1U
VCC3 VCC5 50V

Graphics DC Power Board VCC5

A
R87 R83
4.7K 4.7K EC11FS2 D508 16

TWISTER RED 120Z/100M L2

K
1
DDC2B

External VGA Connector

9
GREEN
BLUE
120Z/100M L3
L4
2
10 J4
3
120Z/100M 11
4
12
VGA
5
G Q6 4
3
5
6
13
6
SUYIN
SDA S D 2 7 14
S
D

1 8 7
G Q503 2N7002 15
8
HSYNC S D FA500
120OHM/100MHZ
D
S

17
CP501
2
1

4
3
2
1

2
1
4
3

4
3
2N7002 G Q502 CP500 7535S-15G2T-05
4
3
2
1

VSYNC S D 22P*4
CP502
RP1 22P*4 22P*4 MONITOR
S
D

G Q5 75*4 1
JL5002
2N7002
SCL S D SHORT-SMT3
S
D

7
8

5
6
7
8

7
8
5
6

5
6
1
JL5012
5
6
7
8

2N7002
SHORT-SMT3
GND_CRT15
121
 7170 N/B MAINTENANCE
8.3 VGA Controller Failure
There is no display or picture abnormal on LCD or monitor.

VGA Controller Failure

Replace motherboard or into
board-level Troubleshooting.
1. Confirm LCD panel or monitor is good
and check the cable are connected
properly. YES
2. Try another known good monitor or Check if
LCD module. U501,U502 Re-soldering.
are cold
YES solder?

Display Replace faulty part of NO

OK? LCD or monitor.
One of the following parts on the mother-board may be defective,
NO use an oscilloscope to check the following signal or replace the
parts one at a time and test after each replacement.
Remove all the I/O device & cable from LCD Panel failed External VGA failed
motherboard except LCD panel or extended
Parts: Signals: Parts: Signals:
monitor.
Q500 LCDVCC D508 RED
Q501 TXCLK+- L2~L4 GREEN
YES
Connect the I/O device & L502 TX2CLK+- Q5,Q6 BLUE
Display cable to the M/B one at a R506 TXOUT[0:2]+- Q502,Q503 SDA
OK? time to find out which part J8 TX2OUT[1:2]+- R87,R83 SCL
C501 ENPVDD FA500,J4 HSYNC
is causing the problem.
C503 ENPBLT CP500~ VSYNC
C505 CP502
NO
C506 RP1
122
 7170 N/B MAINTENANCE
8.4 Memory Test Error
Either one or two extend SO-DIMM RAM Module is failure or system hangs up.
J501

SH6 SDRAMCLK2 R548

CK0,1 SH16
10
SDRAMCLK3 R553
MA[0..14] RP509,RP510 10
R252 R254
22 22
RP505,RP506,RP512,RP514
MD[0..63] RP504,RP507,RP513,RP515 C283
10P
C285
10P
U503
-DQMA[0..7] SMBCLK
RP511 -MDQMA[0..7]
SMBCLK ICS9248-195
-MCS[2..3] SMBDATA1 Clock generator
-MSWEA R538 SDRAMCLK0
U501 -MSCASA 10
-CS[0..3] -MCS[0..3] -MSRASA R540 SDRAMCLK1
-SWEA RP508 -MSWEA 10
SH8
VT8603 R253 R251

S3
-SCASA -MSCASA
-MCS[0..1] J502 22 22
-SRASA -MSRASA C284 C282 SMBDATA
-MSWEA 10P 10P
Graphics -MSCASA VCC5
-MSRASA
R111
10K
SDRAMCLK0
TWISTER
Q13
SDRAMCLK1 3
DRAMENA
DTC144TKA R1 2
1
MDD[0..63]
SMBCLK

MAA[0..14]

G
G
CK2,3 SMBDATA0 SMBDATA1 SH11
S D
D S
U12

S
D

S
D
Q12
Q11
FDV302P
FDV301N
VT8231
SMBDATA
SMBCLK
South Bridge

123
 7170 N/B MAINTENANCE
8.4 Memory Test Error
Either one or two extend SO-DIMM RAM Module is failure or system hangs up.

Memory Test Error

Board-level Troubleshooting
For Memory test error.

1. Check if SO-DIMM Connectors are no cold solder.

2. Check the extend SDRAM module is installed
properly. ( J501,J502 )
3. Confirm the SDRAM socket is ok, no band pins.

Check the following parts for cold solder or one of the following
YES parts on the mother-board may be defective, use an oscilloscope
Test to check the following signal or replace the parts one at a time and
Correct it. test after each replacement.
OK?
NO

Parts: Signals:
Try another known good
SO-DIMM modules. MD[0:63] -CS[0:3]
J501,J502
RP505,RP506 MA[0:14] CKE[0:3]
RP512,RP514 -SCAS SDRAMCLK[0:2]
NO Replace mother RP504,RP507 -SRAS SMBDATA
Test board or into RP513,RP515 -SWEA SMBCLK
OK? board level RP511,RP508 -DQMA[0:7]
Troubleshooting. R548,R553
YES R538,R540
Q11,Q12,Q13
R111
END
124
 7170 N/B MAINTENANCE
8.5 Keyboard(K/B) , Touch-pad(T/P) , ESB Test Error
Error message of keyboard failure is shown or any key doesn’t work.
J15
79 KO0 1
P10/A0 78 KO1 2
P11/A1

Internal Keyboard Connector

77 KO2 3
P12/A2 76 KO3 4
P13/A3 75 KO4 5
U502 P14/A4
P15/A5
P16/A6
74
73
KO5
KO6
6
7
72 KO7 8
P17/A7 67 KO8 9
Micro P20/A8
P21/A9
66
65
KO9
KO10
10
11
Controller P22/A10
P23/A11
P24/A12
64
63
KO11
KO12
12
13 Email BTN SW3
25V/24M
62 KO13 14
P25/A13 61 KO14 15 1 2
P26/A14 KO0 KI1
60 KO15 16
SH17 P27/A15 17

3
4
18
P52/SCK0 26 KI0 19
P60/KEYIN0/FTCI
97 27 KI1
-IOW P61/KEYIN1/FTOA 28 KI2
20
21
P62/KEYIN2/FTIA 29 KI3 22
P63/KEYIN3/FTIB 32 KI4 EASY START BTN
23
P64/KEYIN4/FTIC
96 33 KI5 24
-IOR P65/KEYIN5/FTID 34 KI6 KO1 1 2 KI1
P66/KEYIN6/IRQ6 KO0
35 KI7 3 4 KI2
P67/KEYIN7/IRQ7 -PWRSW 5
SH11 J9 6 KI3
KI4
7 8
IRQ1 53 L1 9 10
VCC5 F1
External Keyboard/Mouse
U12 120Z/100M C1
IRQ12 54 1000P
PS/2
VT8231 FA1 J1
KM_CLK GND_PS2
1 8 1
XD[0:7] M_CLK
KM_DATA
2 7 2 1
2
3 6 3
3
South M_DATA 4 5 4
5 4
5
Bridge 120OHM/100MHZ 6
6
2 GND1

1
4
3
2
GND1
X501 CP1 GND2
GND2
16MHz 3 47PX4 MINI-DIN/6P
C10801-106XX

8
5
6
7
-ROMCS U505 JL1 PS2 Keyboard or Mouse
95 -H8_KBCS
74CBTD SHORT-SMT3
GND_PS2
3384
VCC5

T_DATA
L521120Z/100M 1
L38 120Z/100M 2
3 J17 TOUCH-PAD
120Z/100M 4
T_CLK L37 C189 C188 C627 MODULE
47P 47P 0.1U
50V

125
 7170 N/B MAINTENANCE
8.5 Keyboard(K/B) , Touch-pad(T/P) , ESB Test Error
Error message of keyboard or touch pad failure is shown or any key doesn’t work.

Board-level Troubleshooting for

Keyboard Test Error
K/B or T/P or ESB test error.

Check if K/B or T/P cable or ESB Check if J15, J1and J17 is cold
Connect is installed properly. solder or bend pins.

YES YES
Replace or
Test Correct it then Test Re-solder
OK? end. OK? J15, J1and J17
NO NO

Check the following parts for cold solder or one of the following
Try another known good K/B or
parts on the mother-board may be defective, use an oscilloscope
T/P or ESB (Internal or external).
to check the following signal or replace the parts one at a time
and test after each replacement.
YES Parts: Signals:
Test Replace the faulty K/B
OK? or T/P or ESB then end. J15 U502 KI[0:7] -IOW
J1 CP1 KO[0:15] -IOR
NO J17 L37 T_DATA IRQ1
X501 L38 T_CLK IRQ12
U12 L521 -H8_KBCS XD[0:7]
Replace M/B or into
F1 C188
board-level Troubleshooting L1 C189
FA1 C627
U505

126
 7170 N/B MAINTENANCE
8.6 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.

SH11 SA[0..15] J13

SA0 1 16 DD0-2
SA1 2 15 DD1-2
VCC5
SA2 3 14 DD2-2
RP48 SA3 4 13 DD3-2
33*8 SA4 5 12 DD4-2
RPX8 SA5 6 11 DD5-2
3

-PCIRST SA6 7 10 DD6-2

2 Q4
SA7 8 9 DD7-2
DTC144WK
SA8 1 16 DD8-2
SA9 2 15 DD9-2
SA10 3 14 DD10-2 SH12
U12
1

RP47 SA11 4 13 DD11-2

33*8 SA12 5 12 DD12-2
R57
1M RPX8 SA13 6 11 DD13-2
VCC5 SA14 7 10 DD14-2
VT8231 SA15 8 9 DD15-2
R132
10K
South Bridge RP37 33*8 RPX8
-RSTDRV 1 16 -BRSTDRV-2
SDA0 2 15 DA0-2
SIORDY 3 14 IORDY-2 CD-ROM
-SDACK 4 13 -DACK-2
SDA1 5 12 DA1-2
-SDIOW 6 11 -DIOW-2
-SDIOR 7 10 -DIOR-2
SDREQ 8 9 DREQ-2

R130
5.6K
VCC5

R181
4.7K
RP38 33*4
IRQ15 1 8 INTRQ-2
-SCS1 2 7 -CS1-2
-SCS3 3 6 -CS3-2
SDA2 4 5 DA2-2
127
 7170 N/B MAINTENANCE
8.6 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.

CD-ROM Drive Test Error

Board-level Troubleshooting for
CD-ROM drive test error.

1. Try another known good compact disk.

2. Check if CD-ROM is installed
properly( J13 ).

YES Check the following parts for cold solder or one of the following
Test Correct parts on the mother-board may be defective, use an oscilloscope
OK? It then end. to check the following signal or replace the parts one at a time and
NO
test after each replacement.

Try another known good Parts: Signals:

CD-ROM drive.
U12, J13 SA[0~15] -BRSTDRV-2
Q4, R57 -PCIRST DA[0:2]-2
R132 ,R181 SDA[0:2] IORDY-2
YES
Replace faulty RP47, RP48 SIORDY -DACK-2
Test -SDACK -DIOW-2
parts then end. RP37, RP38
OK? R130 -SDIOW -DIOR-2
NO -SDIOR DREQ-2
SDREQ INTRQ-2
IRQ15 -CS1-2
Replace M/B or into -SCS1 -CS3-2
-SCS3 DA2-2
board-level Troubleshooting.

128
 7170 N/B MAINTENANCE
8.7 Hard Drive Test Error
Either an error message is shown , or the driver motor continues spinning ,
while reading data is from or writing data is to hard drive.
SH11 PD_D[0..15] J20

PD_D 11 1 16 DD11-1
PD_D 3 2 15 DD3-1
VCC5
PD_D 12 3 14 DD12 -1
RP36 PD_D 7 4 13 DD7 -1
33*8 PD_D 8 5 12 DD8-1
RPX8 PD_D 6 6 11 DD6-1
3

-PCIRST PD_D 9 7 10 DD9-1

2 Q4
PD_D 5 8 9 DD5-1
DTC144WK
PD_D 15 1 16 DD15-1
PD_D 2 2 15 DD2-1
PD_D 13 3 14 DD13-1 SH12
U12
1

RP35 PD_D 1 4 13 DD1-1

33*8 PD_D 14 5 12 DD14-1
R57
1M RPX8 PD_D 0 6 11 DD0-1
VCC5 PD_D 10 7 10 DD10-1
VT8231 PD_D 4 8 9 DD4-1
R129
10K
South Bridge RP34 33*8 RPX8
-RSTDRV 1 16 -BRSTDRV-1
-PDACK 2 15 -DACK-1
PDA1 3 14 DA1-1
PDA0 4 13 DA0-1
PIORDY 5 12 IORDY-1
PDREQ 6 11 DREQ-1
-PDIOW 7 10 -DIOW-1
-PDIOR 8 9 -DIOR-1

R128
5.6K
VCC5

R173
4.7K
RP33 33*4
IRQ14 1 8 INTRQ-1
-PCS1 2 7 -CS1-1
-PCS3 3 6 -CS3-1
PDA2 4 5 DA2-1
129
 7170 N/B MAINTENANCE
8.7 Hard Drive Test Error
Either an error message is shown , or the driver motor continues spinning ,
while reading data is from or writing data is to hard drive.

Hard Drive Test Error.

Board-level Troubleshooting
For hard drive test error.
Check if HDD’s connector installed to HDD and
system is connected properly (J20)

YES
Re-boot Correct it Check the following parts for cold solder or one of the following parts
OK? then end. on the mother-board may be defective, use an oscilloscope to check
NO the following signal or replace the parts one at a time and test after
each replacement.
1. Try another known good HDD.
Parts: Signals:
2. Try another known good HDD
cable. PD_D[0~15] -BRSTDRV-1
U12, J20
Q4, R57 -PCIRST -DACK-1
RP35, RP36 -PDACK DA[0:2]-1
YES
Replace the R129, RP34 PDA[0:2] IORDY-1
Re-boot R173, RP33 PIORDY DREQ-1
faulty part
OK? R128 PDREQ -DIOW-1
then end. -PDIOW -DIOR-1
NO -PDIOR INTRQ-1
IRQ14 -CS1-1
-PCS1 -CS3-1
Replace mother BD or into -PCS3
board-level Troubleshooting.

130
 7170 N/B MAINTENANCE
8.8 USB Port Test Error
An error occurs when a USB I/O device is installed.

F5

mircoSMDC110
SH10 F4 USBVCC5
VCC5
MINISMDC110 R2
33K L16
-USBOC1
R1 120Z/100M
C10 C9
47K 0.1U
1000P 50V

GND_USB
J26
USBP1- R161 1
2 1
3 2
22 4 3
4 3 4
L57 GND1
1 2 200Z/100M GND2 GND1
CORE_ACM2520U GND3 GND2
R157 GND4 GND3
USBP1+ GND4
U12 USB/4PX1
22 LINKTEK
C209 C207
47P 47P R160 R156 GND_USB UAR80-4W510
15K 15K
VT8231
USBVCC5 SH15
South Bridge
R11
L15 J27
-USBOC0 33K
1
2 1
C11 R4 120Z/100M 3 2
C8 4 3
1000P 47K 0.1U 4
50V GND1
GND2 GND1
R167 GND_USB GND3 GND2
USBP0- GND4 GND3
GND4
22
USB/4PX1
4 3 LINKTEK
L58 UAR80-4W510
1 2 GND_USB
600Z/100M
USBP0+ R165 CORE_ACM2520U

22
C218 C212
R166 R164 JO500
47P 47P GND_USB
15K 15K
SHORT-SMT4
GND_USB

131
 7170 N/B MAINTENANCE
8.8 USB Port Test Error
An error occurs when a USB I/O device is installed.

USB Test Error

Board-level Troubleshooting
For USB test error
1. Check if the USB device is
installed properly.
2. Confirm USB driver is installed
ok.

YES Check the following parts for cold solder or one of the following
Test parts on the mother-board may be defective, use an oscilloscope
Correct It.
OK? to check the following signal or replace the parts one at a time and
test after each replacement.
NO

Try another known Signals:

Parts: Parts:
good USB device.
J26 J27 VCC5
YES U12 U12 USBVCC5
Change the F4, F5 F4, F5
Re-test
faulty part L16,R1, R2 L15 USBP1-
OK? USBP1+
NO then end. C9, C10 R1, R2
R157, R161 R11, R4 -USBOC1
L57, C209 C11, C8
C207, R156 R167, R165 USBP0-
Change M/B or go into R160 L58, C218 USBP0+
board-level Troubleshooting. C212, R164 -USBOC0
R166

132
 7170 N/B MAINTENANCE
8.9 PIO Port Test Error
When a print command is issued, printer prints nothing or garbage. VCC5
U501
RP500
0*4 J10 PJ2 12 13 D1
11 14 BAS32L
RP501 RP501
0*4 -P_STB 8 1 -PP_STB 10 15
-P_AFD 7 2 -PP_AFD
P_LPD06 3 PP_LPD0 9 16
RP502 -P_ERR 5 4 -PP_ERR
0*4 8 17
0*4
SH10 P_LPD0 8 1 DP_LPD0 7 18
P_LPD1 7 2 DP_LPD1 RP502 PP_LPD1
J1
P_LPD2 6 3 DP_LPD2 P_LPD18 1 6 19
P_LPD3 5 4 DP_LPD3 -P_INIT 7 2 -PP_INIT 26
P_LPD4 8 1 DP_LPD4 P_LPD26 3 PP_LPD2 5 20
P_LPD5 -PP_SLIN
U12 P_LPD6
7
6
2
3
DP_LPD5
DP_LPD6
-P_SLIN5
0*4
4
4 21
STB#
AFD#
1
14
P_LPD7 5 4 DP_LPD7 R503 LPD0 2
P_SLCT 8 1 DP_SLCT P_LPD3 PP_LPD3 3 22 ERR# 15
-P_STB 7 2 -DP_STB 2 23 LPD1 3
-P_AFD 0 1 24 INIT# 16
VT8231 -P_ERR
6
5
3
4
-DP_AFD
-DP_ERR LPD2 4

Parallel Port Connector

-P_INIT 1 8 -DP_INIT SLIN# 17
-P_SLIN 2 7 -DP_SLIN PAC128401Q LPD3 5
-P_ACK 3 6 -DP_ACK QSOP24A 18
P_BUSY 4 5 DP_BUSY LPD4 6
South P_PE 8 1 DP_PE 19
-COM1RTS 7 2 -DCOM1RTS LPD5 7
Bridge COM1TXD
-COM1DTR
6
5
3
4
DCOM1TXD
-DCOM1DTR D/D BD LPD6
20
8
-COM1CTS -DCOM1CTS 21
COM1RXD DCOM1RXD U502 LPD7 9
-COM1DCD -DCOM1DCD 22
-COM1DSR -DCOM1DSR 12 13 ACK# 10
-COM1RI 1 2 -DCOM1RI 23
11 14 BUSY 11
R12 RP503 24
2
1
4
3

2
1
4

3
2
1
4
3

2
1
4
3

3
2
1
4

0 P_LPD48 1 PP_LPD4 10 15 PE 12
P_LPD57 2 PP_LPD5 25
1

C15 P_LPD66 3 PP_LPD6 9 16 SLCT 13

RP2 P_LPD75 4 PP_LPD7
0*4 22P
8 17 27
5% 0*4
2

7 18 GND_IO2 PIO
RP504
7
8
5
6

7
8
5

6
7
8
5
6

7
8
5
6

6
7
8
5

7536S-25G2T GND_IO2
RP521 -P_ACK 8 1 -PP_ACK 6 19 SUYIN
0*4 P_BUSY7 2 PP_BUSY
CP503 CP504 CP506 CP2 CP507 P_PE 6 3 PP_PE 5 20
22P*4 22P*4 22P*4 22P*4 22P*4 P_SLCT5 4 PP_SLCT
4 21
0*4
3 22
2 23
1 24

GND_IO2 PAC128401Q GND_IO2

QSOP24A
PIN D E FIN IT IO N O F PIO PO R T L O O PB A C K C O N N E C T O R FO R PIO T E ST : PRINTER
PIN 1 ST B ST R O B E SIG N A L PIN 14 AFD A U TO LIN E FEE D PIN 1, 13 SH O R T PIN 10,16 SH O R T
PIN 2-9 D0 - D7 PA R A L LE L PO R T D A T A B U S D 0 TO D 7 PIN 15 ER R ER R O R A T PR IN T ER PIN 2, 15 SH O R T PIN 11,17 SH O R T
PIN 10 ACK A C K N O W LE D G E H A N D S H A N K PIN 16 IN IT IN IT IA T E O U T PU T PIN 12, 14 SH O R T
PIN 11 BUSY B U S Y SIG N A L PIN 17 SL IN PR IN T E R SE LE C T L O O PB A C K C O N N E C T O R FO R E PP T E ST :
PIN 12 PE PA P ER EN D PIN 18-25: SIG N A L G R O U N D PIN 1, 2, 4, 6, 8 SH O R T
PIN 13 SL C T PR IN TE R SE L EC T ED PIN 3, 5, 7, 9, 16 SH O R T
PIN 18, 19, 20, 21, 22, 23, 24, 25 SH O R T
133
 7170 N/B MAINTENANCE
8. 9 PIO Port Test Error
When a print command is issued, printer prints nothing or garbage.

PIO test error

Board-level troubleshooting for

1. Check if PIO device is installed PIO test error
properly.(J1)
2. Check CMOS LPT port setting
properly.

Yes
Test Check the following parts for cold solder or one of the following
Correct it
ok? parts on the mother-board may be defective, use an oscilloscope
No to check the following signal or replace the parts one at a time and
test after each replacement.
Try another known good PIO device.
On D/D BD
Yes PARTS: PARTS: SIGNALS: SIGNALS:
Re-test Change the U12, J10 RP501 P_LPD[0:7] P_PF
ok? faulty device. JP2, J1 RP502 P_SLCT -COM1RTS
No RP500, RP501 R503 -P_STB -COM1TXD
RP502, RP521 RP503 -P_AFD -COM1DTR
Replace M/B or go into RP2, R12 RP504 -P_ERR -COM1CTS
board-level troubleshooting CP503, CP504 U501 -P_INIT -COM1RXD
CP506, CP507 U502 -P_SLIN -COM1DCD
CP2, C15 D1 -P_ACK -COM1DSR
P_BUSY -COM1RI

134
 7170 N/B MAINTENANCE
8.10 Audio Failure
J24
No sound from speaker after audio driver is installed. LINE_IN_L R694 L534 600Z/100M 1
2
6.8K 3
LINE_IN_R R695 L535 600Z/100M 4
VCC3 5
VCC5 6.8K
AVDDAD JS5 C662 C663R693 R696 L536 Line In
L42
6.8K 6.8K Jack
L44 100P 100P 5% 5% 120Z/100M
120Z/100M SHORT-SMT4 120Z/100M C620
0.1U AGND CAGND

C217 C603
50V J30
C605 C608 0.1U 0.1U 1
0.1U 0.1U 50V 50V AGND 2
50V 50V Internal
AGND AGND AGND Micro Phone
23 C247 2.2U +80-20%
Jack
LINE/IN/L
24 C248 2.2U +80-20% AVDDAD 5
J23
LINE/IN/R 4
C245 1U 10V R207 R206 MIC_3
MIC1
21 MIC1 MIC MIC_2 L47 3
2
22K 1
22K 600Z/100M
C244 1U 10V R690 CDROM_RIGHT C253
CD/R
20 6.8K 5% J13 C254 C261 100P
External
SH11 18 C242 1U 10V R688 6.8K 5% CDROM_LEFT 1U 0.1U CAGND Micro Phone
CD/L 50V L533
19 C243 1U 10V R689 0
CDROM_COMM SH12 Jack
CD/GND 600Z/100M
R691 R193 R191 CD-ROM
U12 -ACRST
Audio Jack
6.8K 6.8K 0
ACSDOUT U16 5% 5% AGND
5V_AMP C260
VT8231 ACSDIN R581 C625 R585 R583 AGND
100U

+
33K 22K
22 2.2U 16V EW6.3
South
ACSYNC ALC200 +80-20%
21 22 SPKROUT+ 1
ACBITCLK R578 C624 R584 20 RLINE IN
RHP IN
R OUT+ 15
R OUT-
SPKROUT- 2 R J22 Internal Speaker
Bridge R582 SH13 3 SPKLOUT+ 1
22
2.2U 22K 4 L OUT+ 10 SPKLOUT- 2 L Connector
SH13 33K
5 LLINE IN L OUT- J21
+80-20% LHP IN
VR1_5 RVDD 7
18
LINE_OUT_5 L46 5
J25
LVDD 600Z/100M 4
C249
VR1 U18 1
GND0 12 EW6.3 LINE_OUT_2 L532 3

+
C259 2
5

VR1_4 GND1 13
L.CH
AOUT_R 10K 100U 16V 600Z/100M 1
36 4.7U 16V 4 14 GND2 24
LINE/OUT/R 16 SE/BTL# GND3 R692 C286 C665
35 AOUT_L C258 1 3 HP/LINE# R199 1K IDJ-B27-F6T
LINE/OUT/L 16V 9 1K 100P 100P
4.7U Line Out
VR1_1 MUTE OUT
2

8 Phone Jack
SHUTDOWN L45
PQFP48_0.5MM VR1_2 30 25
AGND 31 G6 Amplifier G1 26
C256 R186 R184 32 G7 G2 27 5V_AMP 120Z/100M CAGND
33 G8 G3 28 AGND
2.2U 33K 22K 34 G9
G10
TPA0102 G4 29
G5 R205
+80-20% TSSOP24_TPA0102 100K
AGND
AGND R204
C257 R174 R183 22K
100K
2.2U 33K
+80-20%
135
 7170 N/B MAINTENANCE
8.10 Audio Failure
No sound from speaker after audio driver is installed.

Audio Drive Failure Board-level

Troubleshooting for
audio test error.

1. Check if speaker cables are connected

properly.
2. Make sure all the drivers are setting
properly. Check the following parts for cold solder or one of the following parts on the
motherboard may be defective,use an oscilloscope to check the following signal
or replace the parts one at a time and test after each replacement.

YES 1. If no sound 2. If no sound 3. If no sound

Test cause of line out, cause of MIC, cause of CD-ROM,or Line In
OK? check the following check the following check the following
NO parts & signals: parts & signals: parts & signals:

1.Try another known good Parts: Signals: Parts: Signals: Parts: Signals:
speaker, CD-ROM.
2. Exchange another known J25, J21, J22 AOUT_R U12, U16 MIC U12, U16 CDROM_LEFT
good charger board. U12, U16 AOUT_L J23, J30 MIC_2 C242~C244 CDROM_RIGHT
C258,C259 SPKROUT+ R207, R206 MIC_3 R688~R693 CDROM_COMM
U18,VR1 SPKROUT- L47, L533 J13 LINE_IN_L
YES C624, C625 SPKLOUT+ C254, C261 C247, C248 LINE_IN_R
Test R582~R585 SPKLOUT- C253 R694, R695
End. C260, L46 LINE_OUT_5 L534, L535
OK?
C256, C257 LINE_OUT_2 C662, C663
NO R174, R183 R693, R696
R184, R186 L536
R204, R205
Replace M/B or go
C249, L532
into board-level R199, L45
Troubleshooting.
136
 7170 N/B MAINTENANCE
9. Spare Parts List-1

Part Number Description Location(s) Part Number Description Location(s)

441999900201 AC ADPT ASSY OPTION;M722 272431105901 CAP;100U ,10V ,20%,7343,SMT PC505,PC506,PC513,PC5
442051200001 AC ADPT ASSY;19V/3.16A,DELTA 272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SMT C208,C21,C214,C219,C22
541666990001 AK;01-EN,BOX,7170 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,SMT C133,C150,C20,C506,C59
541666990032 AK;EN,7170,UTILITY ONLY 272043106501 CAP;10U ,CR,25V ,20%,1812,Y5U,SMT PC23,PC503,PC504
441999900051 BATT ASSY OPTION;LI,9-CELL,7170 272431157506 CAP;150U ,UD,2.5V ,20%,7343,SP-CON PC1,PC11,PC2,PC3
442669900003 BATT ASSY;11.1V/5.4AH,LI,E-ONE,7170 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5V PC508
340669900022 BEZELASSY;DVD ROM,PIONEER,7170 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5V C103,C115,C116,C126,C1
221669940001 BOX;AK,7170 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805,Y5V PC507
340669900020 BRACKET ASSY;I/O,TV-OUT,7170 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y5V C247,C248,C256,C257,C6
340669900021 BRACKET ASSY;TOUCHPAD,7170 272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y5V C167,C168,C586,C591,C6
343669900006 BRACKET;CD-ROM,7170 272075221401 CAP;220P ,CR,50V ,10%,0603,X7R,SMT PC508
341669900004 BRACKET;LCD,14.1",HYUNDAI,L,7170 272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT C15,C207,C209,C212,C21
341669900003 BRACKET;LCD,14.1",HYUNDAI,R,7170 272041226501 CAP;22U ,CR,10V ,20%,1812,X7R,SMT C57
421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z CORE 272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C18
272075103702 CAP;.01U ,50V,+80-20%,0603,SMT C111,EC1,EC10,EC11,EC 272431337506 CAP;330U,4V,20%,7343,SMT PC31
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C1,C2,C509,PC13,PC14,P 272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y5V PC19,PC21,PC6
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C100,C104,C118,C119,C1 272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y5V C258,C259,C610,C611,C6
272072224701 CAP;.22U ,16V ,+80-20%,0603,Y5V,SMT PC509,PC510,PC514 272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,SMT C188,C189
272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT C2 272431566501 CAP;56U ,TT,4V,20%,SP-CON,7343,SMT PC521
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,SMT PC17,PC23 272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C575,C576
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,SMT C1,C10,C107,C109,C11,C 272431826501 CAP;82U ,2.5V,20%,SP-CON,7343,SMT C51,C60,C68,PC500,PC5
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SMT PC524 221669950007 CARD BOARD;BTM,PALLET,7170
272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,SMT C510,C511,C512,C513 221669950008 CARD BOARD;FRAME,PALLET,7170
272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,SMT C253,C286,C662,C663,C6 221669950006 CARD BOARD;TOP,PALLET,7170

137
 7170 N/B MAINTENANCE
9. Spare Parts List-2

Part Number Description Location(s) Part Number Description Location(s)

221670020009 CARTON;NON-BRAND,TW,7521 331040050006 CON;HDR,MA,50P,0.8MM,R/A,ALLTOP J13
431669900002 CASE KIT;TV-OUT,7170 291000011023 CON;HDR,MA,5P*2,1.27MM,ST,H10.4,SPEED J9
344669900010 CASE;HDD,7170 291000256821 CON;IC CARD,68P,.635MM,62598-22A,FCI J14
451669900051 CD ROM ME KIT;24X,7170 331000004018 CON;IEEE1394,MA,4P,.8MM,R/A,LINKTEK J3
273000500035 CHOKE COIL;0.6UH,1.44mOHM,20%,27A PL1 331870004010 CON;MINI DIN,4P,R/A,W/GROUND,C10801 J5
273000111002 CHOKE COIL;120OHM/100MHZ,20%,3216 L57,L58 331870006013 CON;MINI DIN,6P,R/A,W/GROUND,73156 J1
273000500044 CHOKE COIL;2.2UH,2.7mOHM,20%,3.10A PL2 291000251241 CON;PCI CARD,124P,FM,.8MM,SMT J503
273000500015 CHOKE COIL;50UH(REF),D.4*2,5.5T,SMT L8 291000810203 CON;PHONE JACK,2P,H=8.5,R/A,SMT J2
331000006011 CON;BATT,6P,2.5MM,R/A,CEN LINK J16 291000810802 CON;PHONE JACK,8P,H=12.59,R/A,RJ45 J11
331720015006 CON;D,FM,15P,2.29,R/A,3ROW J4 331910003034 CON;POWER JACK,3P,D=2.5,SINGATRON J4
331720025005 CON;D,FM,25P,2.775,R/A J1 331840005028 CON;STEREO JACK,5P,R/A,W10.4,BLUE J24
291000153006 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST,SMT J18 331840005029 CON;STEREO JACK,5P,R/A,W10.4,GREEN J25
291000142402 CON;FPC/FFC,24P,1MM,H5.5,ST,ACES J15 331840005027 CON;STEREO JACK,5P,R/A,W10.4,PINK J23
291000150812 CON;FPC/FFC,8P,1MM,R/A,2CONTAC,W/GND,AC J501 331000004025 CON;USB,MA,R/A,4P*1,2MM,85116-4011,ACES J26,J27
331040020004 CON;HDR,FM,10P*2,2.54MM,R/A,H8,49 J7 291000410201 CON;WFR,MA,2P,1.25,ST,SMT/MB J21,J22,J30,J6
331030044013 CON;HDR,FM,22*2,2MM,ST,C16805 291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J12
331040044011 CON;HDR,FM,22P*2,1.27MM,R/A,H3MM J10 291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J502
291000011024 CON;HDR,FM,5P*2,1.27MM,ST,H4.5,SPEED J501 291000410404 CON;WFR,MA,4P,1.25MM,ST,SMT,HIROSE J17
291000011001 CON;HDR,MA,10P*1,1.25,ST,SMT J3 345669600065 CONDUCTIVE TAPE;MB,SDRAM,RACE
331040020005 CON;HDR,MA,10P*2,2.54MM,R/A,H8.49 PJ1 345669600053 CONDUCTIVE TAPE;PCMCIA,RACE
291000013012 CON;HDR,MA,15P*2,1.25MM,ST,H4.8,ACES J8 313000150093 CORE;LAN CORE,230OHM/100MHZ,LF-100
331040020006 CON;HDR,MA,22P*2,1.27MM,R/A,H3MM PJ2 340669900010 COVER ASSY;14.1"LCD COVER,7170
291000024409 CON;HDR,MA,22P*2,2MM,R/A,SMT,ALLTOP J20 340669900006 COVER ASSY;7170
291000020202 CON;HDR,MA,2P*1,1.25,R/A,SMT,HIROSE J505 340669900018 COVER ASSY;ID1,7170

138
 7170 N/B MAINTENANCE
9. Spare Parts List-3

Part Number Description Location(s) Part Number Description Location(s)

340669900009 COVER ASSY;KEYBOARD COVER,7170 344668900053 DUMMY-CARD;PCMCIA,M722
340669900015 COVER ASSY;RAM-MINIPCI COVER,7170 523499999028 DVD ASSY OPTION;8X,7170
340669900008 COVER ASSY;SPEAKER COVER,7170 523424379020 DVD DRIVE;8X,DVD-K11TA,PIONEER
344669900003 COVER;HINGE,7170 523466990004 DVD ROM ASSY;8X,K11,PIONEER,7170
272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,SMT CP1,CP2,CP500,CP501,C 312271006350 EC;100U ,25V,20%,RA,6.3*7,-40~105'C PC10,PC11,PC4,PC5,PC8
291006214426 DIMM SOCKET;144P,.8MM,AMP353870,RAC J501 312271006350 EC;100U ,25V,20%,RA,6.3*7,-40~105'C PC12,PC21,PC8,PC9
291006214427 DIMM SOCKET;144P,.8MM,H4,AMP1318144 J502 272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,SMT C249,C260
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D1 227669900005 END CAP; HEATSINK, AK BOX,7170
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D1,D19,D2,D507,PD2,PD 227669900001 END CAP;7170
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 PD504,PD505 227669900004 END CAP;BATTERY,7170
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D3 227669900002 END CAP;FDD,FRAME,7170
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D30,D31,D32,D33 227669900003 END CAP;FDD,T/B,7170
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D500,D501 481669900002 F/W ASSY;KBD CTRL,7170 U502
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D500,D501,D502,D503,D 481669900003 F/W ASSY;SYS/VGA BIOS,REV8231,7170 U8
288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD503 523499993004 FDD DRIVER OPTION;EXT. FDD,7170
288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD1 523411442043 FDD KIT;MITSUMI,D353FU,USB,7170
288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200V PD501 273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN,NZ FA1
288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200V D508 273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN,NZ FA1,FA500
288103103001 DIODE;EC31QS03L,30V,3A,SMT PD1,PD2 273000130019 FERRITE CHIP;120OHM/100MHZ,1608,MLB L4,L6,L501,L502,L503,L5
288103103001 DIODE;EC31QS03L,30V,3A,SMT PD4,PD5,PD500,PD7 273000130019 FERRITE CHIP;120OHM/100MHZ,1608,MLB L17,L2,L22,L24,L26,L29,
288137010001 DIODE;MA3X70100L,30V,700MA,SOT-23 PD502 273000150013 FERRITE CHIP;120OHM/100MHZ,2012,6A L1,L3,L5,PL10,PL4,PL5,P
288100027001 DIODE;RLZ2.7B,ZENER,2.6-2.91,5%,SMT PD503 273000150013 FERRITE CHIP;120OHM/100MHZ,2012,6A L1,L15,L16,L20,L36,L43,
288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD502 273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1608 L46,L47,L532,L533,L534
288100012002 DIODE;SK12,VRRM20V,SMT D4,D5 422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENUS

139
 7170 N/B MAINTENANCE
9. Spare Parts List-4

Part Number Description Location(s) Part Number Description Location(s)

346664900010 FILM;LCD PROTEC,.14.2",235*300,5027 284507005001 IC;CH7005C,TV ENCODER,3/5V,PQFP,44P U511
288003600001 FIR;HSDL3600#007,FRONT VIEW,10P,SMT U1 286302211002 IC;CP2211,POWER DISTRI SW,SSOP16 U5
295000010044 FUSE;1.1A/6V,POLY SWITCH,1210,SMT F1,F2,F5,F500 324180786021 IC;CPU,P-III,866MHZ,FCPGA,370P
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF501 283466570001 IC;EEPROM,9346,64*16 BITS,SO8,SMT U6
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1 283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U10
345669600048 GASKET;FDD,SHORT,RACE 283450083001 IC;FLASH,256K*8-70,PLCC32,ST39SF020
345669600033 GASKET;SUPPORT,EXT RAM,L,RACE 284583434001 IC;H8/F3434,KBD CTLR,TQFP,100P
345669600042 GASKET;USB,10X15X0.3,RACE 284509248019 IC;ICS9248-195,CLOCK GEN,SSOP,48P U503
523416340057 HD DRIVE;20GB,2.5",DJSA-220,H=9.5MM 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU507,PU509
451669900071 HDD ME KIT;7170 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,SO PU6
340669900003 HEATSINK ASSY;CPU,7170 286329510001 IC;LP2951CM-3.3,VOLTAGE REGULATOR PU7
340669900007 HOUSING ASSY;7170 286301632002 IC;MAX1632CAI,PWM CTRL,SSOP,28P PU501
340669900011 HOUSING ASSY;LCD 14.1",HYUNDAI,7170 286301717001 IC;MAX1717,PWM,QSOP,24P PU504
441669900031 HOUSING ASSY;M/B,TV-OUT,7170 281300732001 IC;NC7S32,SINGLE OR GATE,SC70-5 U507
451669900001 HOUSING KIT;7170 281307085001 IC;NC7SZ08P5,2-INPUT & GATE,SC70-5P U26,U514
344600030002 IC CARD CON PART;68P,62601-22ROC,FCI 286307805010 IC;NJM78L05UA,VOL REGULATOR,SOT,89P U513
331650037014 IC SOCKET;370P,ZIF,SOCKET370,CENLIN U1 284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSOP24 U501,U502
282074338402 IC;74CBTD3384,10 BIT BUS SW,TSOP-24 U505 284504410005 IC;PCI4410A,CARDBUS/OHCI,uBGA,209P U21
282007407001 IC;74LVC07,HEX-BUFFER, TSSOP14,14P U508 286301401001 IC;SC1401,PWN CTRL,SSOP,20P PU4
282574164002 IC;74VHC164,SIPO REGISTER,TSSOP,14P U19 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT23 PQ507
284580227001 IC;80227,LAN-PHY,TQFP,64P,SMT U25 286300594001 IC;TL594C,PWM CONTROL,SO,16P PU506
284501021002 IC;ADM1021,TEMPERATURE MTR,SSOP16 U2 286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24P U18
286300809003 IC;ADM809M,RESET CIRCUIT,4.38V,SOT2 U504 284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U500
284500200005 IC;ALC200,AC97 CODEC,TQFP,48P U16 284508231002 IC;VT8231,PCI/ISA,BGA,376P,SMT U12

140
 7170 N/B MAINTENANCE
9. Spare Parts List-5

Part Number Description Location(s) Part Number Description Location(s)

284508603002 IC;VT8603,PCI/AGP/VGA,BGA,552P,SMT U501 242669900005 LABEL;LCD SIDE,7170
273000990018 INDUCTOR;10uH,CDRH125,SMT PL1 242600000412 LABEL;PENTIUM,PWR SUITE 3 NOTE BIOS
273000990023 INDUCTOR;10UH,CDRH125B,SMT PT1 242668820022 LABEL;WINDOWS ME/2000,ORION-3
273000990021 INDUCTOR;33uH,CDRH124,SMT PL4 441669900010 LCD ASSY;HYUNDAI,XGA,14.1",7170
273000150106 INDUCTOR;4.7UH,10%,2012,SMT L21 451669900034 LCD ME KIT;HYUNDAI,XGA,14.1",7170
346668300024 INSULATOR;DIMM P/N MB TOP,HOPE 413000020236 LCD;HT14X13,TFT,14.1",XGA,HYUNDAI
346669900004 INSULATOR;INVERTER,7170 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT D10,D6,D7,D8,D9
346669900019 INSULATOR;MDC MB,94VO,7170 294011200063 LED;RE/GR,H.6,L2.1,W1,12-215 VGC D11
531099990102 KBD OPTION;87,UK,7170 294011200064 LED;RE/GR,H.6,L2.1,W1,12-215 VRC D15
531066990002 KBD;87,UK,K000918F,7170 561566990001 MANUAL KIT;EN,7170,N-B
344669900007 KNOB;MIDDLE,TOUCHPAD,7170 561566990101 MANUAL;USER'S,EN,7170,N-B
451669900092 LABEL KIT;N-B,7170 416266990012 NB PF;HYUNDAI,TV-OUT,XGA,14.1",7170
242600000380 LABEL;10*8MM,BIOS,HI-TEMP 260 375102030010 NUT-HEX;M2,2,NIW
242600000380 LABEL;10*8MM,BIOS,HI-TEMP 260 461669900002 PACKING KIT;N-B,7170
242662300009 LABEL;25*10MM,3020F 227669900006 PAD;LCD/KB,ANIT-STATIC,7170
242600000385 LABEL;27*10,LAN ID BAR CODE 221669950004 PARTITION;A,PALLET,7170
242600000378 LABEL;27*7MM,HI-TEMP 260'C 221669950001 PARTITION;AK BOX,7170
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE 221669950005 PARTITION;B,PALLET,7170
242669900008 LABEL;AGENCY,7170 412669900001 PCB ASSY;INVERTER BD,13",7170
242600000088 LABEL;BAR CODE,125*65,COMMON 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/KIT
242669900012 LABEL;BAR CODE,32x11MM,7170 222600020049 PE BAG;50*70MM,W/SEAL,COMMON
242600000433 LABEL;BLANK,11*5MM,COMMON 222667220003 PE BAG;L560XW345,CERES
242669900009 LABEL;BLANK,60*80MM,7170 222670000001 PE BUBBLE BAG;BATTERY,7521
242664800013 LABEL;CAUTION,INVERT BD,PITCHING 411669900008 PWA;PWA-7170,ESB BD,SMT

141
 7170 N/B MAINTENANCE
9. Spare Parts List-6

Part Number Description Location(s) Part Number Description Location(s)

411669900007 PWA;PWA-7170,ESB BD,T/U 271071121211 RES;12.1K,1/16W,1% ,0603,SMT PR545
411669900006 PWA;PWA-7170,T/P BD 271071121311 RES;121K ,1/16W,1% ,0603,SMT PR532
411669900013 PWA;PWA-7170,TV-OUT,D/D BD,SMT 271071141102 RES;140 ,1/16W,1% ,0603,SMT R69
411669900012 PWA;PWA-7170,TV-OUT,D/D BD,T/U 271071151101 RES;150 ,1/16W,1% ,0603,SMT R27,R29,R32,R36,R37,R5
411669900014 PWA;PWA-7170,TV-OUT,MOTHER BD 271071153301 RES;15K ,1/16W,5% ,0603,SMT R156,R160,R164,R166,R1
411669900016 PWA;PWA-7170,TV-OUT,MOTHER BD,SMT 271071169311 RES;169K ,1/16W,1% ,0603,SMT PR504,PR524
411669900015 PWA;PWA-7170,TV-OUT,MOTHER BD,T/U 271071187211 RES;18.7K,1/16W,1% ,0603,SMT PR518
332810000033 PWR CORD;125V/7A,2P,BLACK,AMERICA 271071102102 RES;1K ,1/16W,1% ,0603,SMT PR505,PR533,PR537,R50
271045057101 RES;.005 ,1W,1% ,2512,SMT PR15,PR16 271071102302 RES;1K ,1/16W,5% ,0603,SMT PR515,PR516
271045207101 RES;.02 ,1W ,1% ,2512,SMT PR1,PR2 271071102302 RES;1K ,1/16W,5% ,0603,SMT R13,R16,R199,R222,R39,
271045207101 RES;.02 ,1W ,1% ,2512,SMT PR1,PR14 271071105101 RES;1M ,1/16W,1% ,0603,SMT PR547,R20
271071000002 RES;0 ,1/16W,0603,SMT PR519,PR514,R503 271071105301 RES;1M ,1/16W,5% ,0603,SMT PR517
271071000002 RES;0 ,1/16W,0603,SMT PR13,PR511,PR534,R102 271071105301 RES;1M ,1/16W,5% ,0603,SMT R169,R523,R541,R57,R66
271071100302 RES;10 ,1/16W,5% ,0603,SMT PR504 271034278301 RES;2.7 ,1/2W ,5% ,2010,SMT R502
271071100302 RES;10 ,1/16W,5% ,0603,SMT PR2,R505,R532,R534,R53 271071203101 RES;20K ,1/16W,1% ,0603,SMT PR12,PR521
271071101301 RES;100 ,1/16W,5% ,0603,SMT R117,R227,R575 271071214101 RES;210K ,1/16W,1% ,0603,SMT PR539
271071104101 RES;100K ,1/16W,1% ,0603,SMT PR507,R501 271071221302 RES;22 ,1/16W,5% ,0603,SMT PR508,R135,R136,R157,R
271071104101 RES;100K ,1/16W,1% ,0603,SMT PR507,PR549,PR551,PR5 271071223302 RES;22K ,1/16W,5% ,0603,SMT R40,R44,R510
271071104302 RES;100K ,1/16W,5% ,0603,SMT PR10,PR5,PR503,PR513, 271071249811 RES;24.9 ,1/16W,1% ,0603,SMT R246,R247,R70,R71
271071103101 RES;10K ,1/16W,1% ,0603,SMT PR529,PR558 271071301311 RES;301K ,1/16W,1% ,0603,SMT PR552
271071103302 RES;10K ,1/16W,5% ,0603,SMT PR4,PR7,R504 271071324012 RES;324K ,1/16W,1% ,0603,SMT PR556
271071103302 RES;10K ,1/16W,5% ,0603,SMT PR506,PR512,PR517,PR5 271071333301 RES;33K ,1/16W,5% ,0603,SMT PR523,R11,R2
271071118211 RES;11.8K,1/16W,1% ,0603,SMT PR540 271071361101 RES;360 ,1/16W,1% ,0603,SMT R670
271071111101 RES;110 ,1/16W,1% ,0603,SMT R28,R34 271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR544,R109,R115,R121,R

142
 7170 N/B MAINTENANCE
9. Spare Parts List-7

Part Number Description Location(s) Part Number Description Location(s)

271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR11,R15 271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP54,RP59,RP61
271071402311 RES;402K ,1/16W,1% ,0603,SMT PR536,PR550 271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP30,RP33,RP38
271071432211 RES;43.2K,1/16W,1% ,0603,SMT PR535 271571330301 RP;33*8 ,16P ,1/16W,5% ,1606,SMT RP34,RP35,RP36,RP37,R
271071453311 RES;453K ,1/16W,1% ,0603,SMT PR538 271611331301 RP;330*4 ,8P ,1/16W,5% ,0612,SMT RP15,RP16
271071475211 RES;47.5K,1/16W,1% ,0603,SMT PR510,PR557 271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP22,RP39,RP46,RP50,R
271071471302 RES;470 ,1/16W,5% ,0603,SMT R209,R210,R211,R212,R2 271621472303 RP;4.7K*8,10P,1/16W,5% ,1206,SMT,TF RP32,RP43,RP49,RP51,R
271071474301 RES;470K ,1/16W,5% ,0603,SMT PR3,PR5 271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP31,RP517
271071474301 RES;470K ,1/16W,5% ,0603,SMT PR9,R506,R518,R60 271621560301 RP;56*8 ,10P,1/16W,5% ,1206,SMT,TF RP10,RP11,RP12,RP13,R
271071475311 RES;475K ,1/16W,1% ,0603,SMT PR548 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP505
271071473101 RES;47K ,1/16W,1% ,0603,SMT PR6 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP1
271071473301 RES;47K ,1/16W,5% ,0603,SMT PR526,R1,R104,R4,R580, 345669900004 RUBBER;LCD,DOWN,7170
271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R128,R130 345669900003 RUBBER;LCD,TOP,7170
271071510301 RES;51 ,1/16W,5% ,0603,SMT R49,R53,R64 565166990001 S/W;CD ROM,SYSTEM DRIVER,7170
271071560301 RES;56 ,1/16W,5% ,0603,SMT R10,R17,R18,R22,R25,R3 565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO
271071619111 RES;6.19K,1/16W,1% ,0603,SMT PR530 323766990002 SDRAM MODULE;128M,8M*16,PC133,SPD
271071634111 RES;6.34K,1/16W,1% ,0603,SMT R19 323799990034 SDRAM OPTION;128MB,PC133,7170
271071682301 RES;6.8K ,1/16W,5% ,0603,SMT R193,R688,R690,R691,R6 340669900024 SHIELDING ASSY;D/D,7170
271071750101 RES;75 ,1/16W,1% ,0603,SMT R14,R24,R45,R65,R7,R9 340669900004 SHIELDING ASSY;TOP CASE,7170
271071806111 RES;8.06K,1/16W,1% ,0603,SMT PR509,PR541 343669900012 SHIELDING;EMI-3,TOP CASE,7170
271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP501,RP502,RP503,RP5 346669900008 SHIELDING;M/B,7170
271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP2,RP500,RP501,RP502 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&LCD
271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SMT RP508,RP509,RP510,RP5 346667120001 SPACER;FC-PGA CPU,6133XN
271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP23,RP27,RP28,RP40,R 370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK
271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP29 370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK

143
 7170 N/B MAINTENANCE
9. Spare Parts List-8

Part Number Description Location(s) Part Number Description Location(s)

370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,NLK 297040105009 SW;PUSH BUTTOM,4P,SPST,12V/50MA,H2.5,W/ SW10,SW7,SW8,SW9
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,NLK 297030105003 SW;TOGGLE,SPST,5V/1mA,MPU-101-80 SW4
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,NLK 340669900002 TILT UNIT;L,7170
370102630601 SPC-SCREW;M2.6L6,HDt0.5,NIWNLK 340669900001 TILT UNIT;R,7170
370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK 442164900010 TOUCH PAD MODULE;TM41PD-350
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK,NIW 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ501
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK,NIW 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ501,PQ502,PQ506,PQ
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK,NIW 288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q501
370102010253 SPC-SCREW;M2L2.5,NIW/NLK,HD07 288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 PQ5,Q10,Q13,Q14,Q15,Q
370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ4,PQ503,Q4,Q7,Q8
370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 Q12
370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 288200302001 TRANS;FDV302P,P-CHANNEL,SOT23 Q11
370102010605 SPC-SCREW;M2L6,NIW,HDT=0.4,779 288207811002 TRANS;IRF7811ATR,N-MOS,.01OHM,SO8 PU2,PU501
370102010605 SPC-SCREW;M2L6,NIW,HDT=0.4,779 288202222001 TRANS;MMBT2222AL,NPN,TO236AB PQ2
370102010605 SPC-SCREW;M2L6,NIW,HDT=0.4,779 288203904010 TRANS;MMBT3904L,NPN,Tr35NS,TO236AB Q1
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 288203906018 TRANS;MMBT3906L,PNP,Tr35NS,TO236AB PQ500,Q504
340669900014 SPEAKER ASSY;L,7170 328202003001 TRANS;MTD20N03HDL,N-MOSFET,2A,30V PQ1
340669900013 SPEAKER ASSY;R,7170 288207002001 TRANS;NDC7002N,N-MOSFET,SSOT-6 PQ504,PQ505
377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW 288214404001 trans;s14404DY,N-MOS,.008OHM,SO8 PU1,PU500,PU502
341668300008 STANDOFF;MDC MODEM,NLK,HOPE 288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 PQ3,PQ6,Q2
344669600037 STOPPER;CUP SOCKET,RACE 288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO8 PU1,PU2
337120100006 SW;DIP,SPST,2P,24V,50MA,HDK632AR-ST SW3 288204816001 TRANS;SI4816DY,2 N-MOSFET,30V,SO8 PU3
297120101005 SW;DIP,SPST,8P,50VDC,.1A,SMT,DHS4S SW1 288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM,SO8 PU3,PU4
297040105009 SW;PUSH BUTTOM,4P,SPST,12V/50MA,H2.5,W/ SW1,SW2,SW3,SW4,SW5, 288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035,SO8 PQ1

144
 7170 N/B MAINTENANCE
9. Spare Parts List-9

Part Number Description Location(s)

288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035,SO8 PU5,PU505
288204925001 TRANS;SI4925DY,P-MOSFET,SO-8 PU508
288209410001 TRANS;SI9410DY,N-MOSFET,.04OHM,SO-8 Q500
273001050040 TRANSFORMER;10/100 BASE,H0011,SMT U3
270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-050 S500
271911103905 VR;10K ,20%,0.05W,RN101GAC10KPCJ-R VR1
421668300005 WIRE ASSY;BIOS,BATTERY,HOPE
421669900001 WIRE ASSY;HYUNDAI 14.1",7170
421669900006 WIRE ASSY;INVERTER,7170
421669900013 WIRE ASSY;MDC,7170
421669900014 WIRE ASSY;MICROPHONE,7170
421669900012 WIRE ASSY;PATCH ANTENNA,7170
421669900007 WIRE ASSY;TOUCHPAD,7170
274011431409 XTAL;14.318MHZ,16PF,50PPM,8*4.5,2P X500,X502
274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X501
274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5,2P X1,X4
274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X2
274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM200 X3

145
 A B

MODEL : 7170 Revision 0A

Contexts
Title Page History of Schematics
Cover Sheet 1 Revision 00 (EVT)
System Block Diagram 2 1.Change S.B.VT8231
2.Del R518 Add R519.
Power Block Diagram 3 3.Del R66
4.Del R106,Add R105.
Central Processor Unit 4
CPU Decoupling Capacitor & VTT Termination Resistor 5
Revision 0A (PreDVT)
North Bridge (VIA TWISTER ) Partial I 6
2 2

North Bridge (VIA TWISTER ) Partial II 7

SO-DIMM Memory X 2 8
LCD & CRT&TV-OUT Interface 9
South Bridge (VIA VT8231 ) Partial I 10
South Bridge (VIA VT8231 ) Partial II 11
HDD, CDROM Connector 12
Audio Codec & Amplifier 13
PCMCIA/1394 Controller(PCI4410) & Socket 14
USBx2, BIOS,TOUCH PAD 15
Clock Generator,Screw holes 16
Micro Controller(H8) 17
LANPHY,MDC 18 POWER STATES Layout note:
Component side
STATE Differential Signal [1]
MINIPCI 19 VOTAGE FULL ON STR STD MEC-OFF REMARK
SIGNAL VCC [2]
CPU Vcore/VTT 20 LCD,PIO [3]
-SUSA - HIGH LOW LOW LOW LVDS,VGA [4]
Battery Connector 21 -SUSB - HIGH LOW LOW LOW GND [5]
Differential Signal [6]
-SUSC - HIGH HIGH LOW LOW Solder side
DC-DC CONNECTOR,CHARGER 22
DVMAIN +18.5V O O O O
VDCIN +18.5V O O O O IDSEL BUSMASTER
IDSEL CHIP REQ CHIP
BATTERY +12V O O O O AD18 VIA(S.B.) REQ0 PCMCIA
AD11 VGA(N.B.) REQ1 NU
RTC_VCC +3V O O O O AD22 LAN REQ2 VGA(N.B.)
VCC_CORE +1.65V O O X X AD17 MINI PCI REQ3 MINI PCI
AD21 PCMCIA REQ4 LAN
VTT +1.5V O O X X
VCC2.5 +2.5V O O X X PCIINT
1
DRAW DESIGN CHECK ISSUED 5VALWAYS +5V O O O O
PCIINT CHIP 1

INTA PCMCIA
VDD5S +5V O O O O INTB N.B.(VGA)
INTC MINI PCI
VDD5 +5V O O O O INTD USB /MINI PCI(REV)/1394/LAN
AVDD +5V O O X X
VCC5 +5V O O X X
5V_AMP +5V O O X X
VCC3 +3.3V O O X X
VCC3_LAN +3.3V O O X X
VCC_LVDS +3.3V O O X X
VCC_CRT +2.5V O O X X
VGTLREF_CPU +1V O O X X
+12V +12V O O X X Title
Cover Sheet

Size Document Rev

C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 1 of 22
A B
 A B

7170 System Block Diagram

Pentium III Thermal
Celeron Resistor
C.P.U.
FC-PGA AD 1021
SOCKET 370 Thermal Recorder

IC CARD CP2211

-HA3..31]
-HD[0..63]

Control
Socket Power Switch
SSOP 16

A[0..25]

D[0..15]

Control
2
DDC 2

VSYNC
HSYNC 144 Pin SO-DIMM Socket*2
CRT

S3 SAVAGE4
R
1394 G TWISTER
PHY
PCI 4410 B
MD[0..63]

TSB41AB1 PCMCIA/1394 LINK Y

NORTH BRIDGE
TI PQFP64 CONTROLLER
S TV-OUT TVD0-11 MA[0..14]

SO-DIMM
C CH7005C
Vedio DRAM Control
uBGA 209 BGA 552
TFT LCD LVDS DATA
MINI 12.1"/ 13.3"/14.1"

AD[0..31]
1394
Control

PCI BUS
External
AD[0..31]

Control
USB0
Microphone

USB1 Internal
RJ45 LAN PHY Microphone MINI PCI
LSI80223 PRINTER Type IIIA SKT
PORT Line In
PD[0..15]
VT8231 COM
JACK Blue Tooth

PORT
(HDD)
Primary EIDE

Internal
Control Speaker
SOUTH BRIDGE AC Link
Realtek ALC200 TPA 0202
Secondary EIDE

SD[0..15] Audio Codec Amplifier Line Out

BGA 376 PQFP 48 JACK Clock
(CDROM/DVD)

Control Generator
M.D.C. RJ-11 ICS9248-143
(30 pin) JACK
Control
16MHz
Cover Switch
1

H8-3434/7 1

XD[0..7] Keyboard Controller

PQFP 100
Internal Keyboard
IR Module
HP-3600
External Keyboard
SA2
Power Button PS/2 Mouse
SA[0..17]
FAN
Touch PAD
Flash ROM
2M/4M bits
PLCC 32
Title
Block Diagram

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 2 of 22
A B
 5 4 3 2 1

POWER DIAGRAM OF THE 7170

PWR_ON
D D

SC1402&MAX1632
VCC3
Shut Down
Protecter
ADAPTOR Self Diode 3.3V DC to DC Convertor
Dischange

VCC5
ON5
learning
5V DC to DC Convertor
VCC12
P Channel D/VMAIN
MOSFET Regulator
C Battery Discharge SI4835DY C

Pack
VCC CORE
Vcc Core DC to DC Convertor
MAX1717
VTT
Diode
VCC25 VDD5
VTT DC to DC Convertor
SC1401
Charge

Always Regulator
LP2951
P Channel
MOSFET Protector
B
Choke Diode
B

SI4835DY

Resistor

CHARGE Charge
CV SWITCH
PWM SI4925DY
Charge IC CC R Sense Resistor
TL594C
CC
A A

Title
Central Processor Unit

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 3 of 22
5 4 3 2 1
 A B

CENTRAL PROCESSOR UNIT VCC5

-BREQ0
5,6 -BREQ0 -RS[0..2]
5,6 -RS[0..2]

1
C69
-RS0 0.1U
-RS1 0603
VCC_CORE -RS2 50V

2
L21 -BP3 5 U2
Note:1.C should be closed to PLL1 and PLL2 W=12 mils -BP2 5 Modify by 12/15 '00
2.PLL2 route should be parallel and next to PLL1(minimize loop 1 2 PLL1 1 2
C57 -BPM1 5 TEST VDD
area) -BPM0 5 Modify by 2/21 '01 16
TEST1

1
4.7UH 22U C59 10
3.L should be closed to C CPU_THERMDA ADD0
2012 1812 10U 3 6
10V 1206 D+ ADD1
V00-V0A 4
W=12milLayout Note:
D-

1
VCC_CMOS (3225->2012) 20% 10V PLL2 V00-V0A

2
C636 11
R27 150 0603 ALERT
Modify by 2/21 '01

RECORDER
(Del to SB) 1000P 7
GND1
2 PICD0

THERMAL
1 0603 8 12
CPU_THERMDC GND2 SDATA H8_THRM_DATA 17

2
R32 150 0603 5 14
PICD1 NC1 SCLK H8_THRM_CLK 17
1 2 9
NC2 -SUSA
W/S=12/12 mils 13 15 -SUSA 6,9,11,16,17
INTR VCC_CORE NC3 STBY
11 INTR
11 NMI
NMI (平平平平長長 GL528SM QSOP16B

1
as short as possible V00-V0A R519 R42
PICCLK (AD1021->GL528SM) 0 0
16 PICCLK 0603 0603

AM32
AM28
AM24
AM20
AM16
AM12
AH22
AH26

AN29

AD32

AH24

AH36
AH32
AK28

AK34

AB34

AA37
AF34

AJ29
AJ25
AJ21
AJ17
AJ13
W33

AM4

AM8
M36

M32

AE5
AB2
AA5

AK2
G33
U33

C35

R32
R36

H36

H32

D20
D24
D28
D32
D36

AF2
E37

E35

X34
Y35
P34
V32

K34

K32

V36
B34
B30
B26
B22
B18
B14

B10

E17
E13
Z32

T34

F22
F26
F30
F34

F14

AJ9
AJ5
L37

L35
J33

J35

W5
U1

D6

C3

N5
B6

E9
E5

K2

S5

P2

2
F4
F2

T2
J5
MENDOCINO
-HTRDY AN25

LINT1/NMI
LINT0/INTR

VC34C
PICD1
PICD0

PLL2
PLL1

RS#2
RS#1
RS#0

BR#0

BP#3
BP#2

BPM#1
BPM#0

VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
VCC56
VCC55
VCC54
VCC53
VCC52
VCC51
VCC50
VCC49
VCC48
VCC47
VCC46
VCC45
VCC44
VCC43
VCC42
VCC41
VCC40
VCC39
VCC38
VCC37
VCC36
VCC35

VCC33
VCC32
VCC31
VCC30
VCC29
VCC28
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC0
PICCLK
5,6 -HTRDY -PRDY TRDY# -INIT
A35 AG33 -INIT 11
5 -PRDY PRDY# INIT#
AE35
-DBSY IERR#
5,6 -DBSY AL27
-DRDY DBSY# -HITM
5,6 -DRDY AN27 AL23 -HITM 5,6
DRDY# HITM# -HIT VTT
AL25 -HIT 5,6
-HD[0..63] -HD63 HIT# VCC2.5 VCC3
5,6 -HD[0..63] F16
-HD62 D63
-HD61
E25
D62 VCC_1.5
AD36 V00-V0A
2
A27
D61 VCC_2.5
Z36 (2.7K->4.7K) 2

1
-HD60 A25
-HD59
-HD58
-HD57
C17
C23
D60
D59
D58
PENTIUM III/CELERON FC-PGA 370-PIN SOCKET A20M#
VCC_CMOS
AE33
AB36
-A20M
-A20M 11
VCC_CMOS R38
4.7K
0603
VCC_CMOS
A19
D57

1
-HD56 C27 AE37 -FLUSH C71
D56 FLUSH#

1
-HD55 -IGNNE

2
C19 AG37 -IGNNE 11 0.1U
-HD54 D55 IGNNE# 0603 R39
-HD53
C21
D54 CPUPRES#
C37
50V 11 -C_FERR 1K
V00-V0A
Processor Pin Definition Comparison (2.7K->1K)

2
A23
-HD52 D53 -PREQ 0603
D16 J37
-HD51 A13
D52 ========================================= PREQ# -PREQ 5
C
-HD50 D51 Pin Celeron P-III Q1

2
C25 W37 HCLK_CPU 16 B
-HD49 D50 BCLK -HLOCK MMBT3904L
C13 ----------------------------------------- AK20 -HLOCK 5,6 E
-HD48 D49 LOCK# VCC2.5 VCC_CORE
A17
-HD47 A15
D48 A29 RSV DEP7# AG35 -C_STPCLK
-HD46 D47 STPCLK# -C_STPCLK 11
A21
D46
A31 RSV DEP3#

1
-HD45 C11 AN19 -DEFER
D45 A33 RSV DEP2# DEFER# -DEFER 5,6

2
-HD44 A11 X4 -CPURST R54
-HD43 D44 AA33 RSV VTT RESET# -CPURST 5,6,11 4.7K
A7 R49
-HD42 D43 0603
D12
D42 AA35 RSV VTT THERMTRIP#
AH28
-HD41 D14 AL31 CPU_THERMDA 51
-HD40 D41 AC1 RSV A33# THERMDP CPU_THERMDC

2
C15 AL29
-HD39 D40 AC37 RSV RSP# THERMDN

1
D10
-HD38 D39
D8 AF4 RSV A35# AG1
-HD37 D38 EDGCTRL CPWROK
A9 AK26
-HD36 D37 AH20 RSV VTT PWRGOOD -FERR
C9 AC35
-HD35 D36 FERR#
B2
D35 AH4 RSV RESET#

2
-HD34 C7 AN31 -ADS
D34 AK16 RSV VTT ADS# -ADS 5,6

1
-HD33 C1 AH30 -SLP V00-V0A
D33 SLP# -SLP 11
-HD32 F6 AK24 RSV AERR# AN17 -BPRI
-BPRI 5,6
R43 (2.7K->1K)
-HD31 D32 BPRI# BSEL0 1K
C5 AL11 RSV AP0# AJ33

R1
-HD30 D31 BSEL# BSEL0 16 0603
J3 AJ35 -SMI
-HD29 D30 AL13 REV VTT SMI# -SMI 11
A3 AH14 -BNR 3 1
-HD28 D29 BNR# -BNR 5,6 PWROK 6,11,17
AL21 RSV VTT -TRST

2
A5 AN33 -TRST 5
-HD27 D28 TRST# DTC144TKA
F12 AN11 RSV VTT
-HD26 D27 TMS Q9 VCC_CMOS
E1 AK32 TMS 5
-HD25 D26 AN13 RSV AP1# TMS TCK
E3 AL33 TCK 5
-HD24 D25 TCK
K6
D24 AN15 RSV VTT
-HD23 G3 AN35 TDI
-HD22 F8
D23 AN21 RSV VTT TDI
AN37 TDO
TDI 5
D22 TDO TDO 5
-HD21 G1 AN23 RSV RP#
-HD20 D21 R28
L3 B36 REV BINIT# E27 1 2 110 0603 1%
D20
-HD19 H6
D19
RSVRD SLEWCTRL RSVRD
RSV50
W35
-HD18 P4 C29 RSV DEP5# AA33
-HD17 D18 VTT VTT
R4
D17 C31 RSV DEP1# VTT
AA35
-HD16 H4 AC37
-HD15 D16 C33 RSV DEP0# RSV47
U3 N35
-HD14 D15 E23 RSV VTT RSV46
N3 N37
-HD13 D14 RSV45
L1 E29 RSV DEP6# N33
-HD12
-HD11
Q1
D13
D12 E31 RSV DEP4#
RSV44
RSV43
Q33 NEAR TO SouthBridge
M4 L33 VTT
-HD10 D11 RSV42
Q3
D10
G35 RSV VTT RSV41
Q35
-HD9 P6 Q37
-HD8 D9 S33 RSV VTT RSV40 VCC_CMOS
S1 S33
-HD7 D8 S37 RSV VTT VTT R34 110
J1 S35 1 0603 2 1%
D7
-HD6 T6
D6 U35 RSV VTT RSV38 RTTCTRL RSV38
VTT
S37
-HD5 S3 U35
-HD4 U1
D5 V4 RSV BERR# VTT
U37 RP15 330*4 1206
-HD3 D4 W3 RSV A34# VTT -A20M
M6 G37 1 8
-HD2 D3 RSV34 NMI
N1 X4 RESET# RESET2# A33 2 7
-HD1 D2 RSV33 INTR
T4 A31 3 6
-HD0 D1 X6 RSV A32# RSV32 -IGNNE
W1 A29 4 5
D0 RSV31
Y33 RSV CLKREF RSV30
AL21
B36
-HA[3..31] -HA31 RSV29 RP16 330*4 1206
5,6 -HA[3..31] AD4
A31 RSV28
G35 Modify by 12/15 '00
-HA30 AA3 C33 1 8 -SMI
-HA29 A30 RS27V -SLP
Z4 C31 2 7
-HA28 A29 RSV26 -C_STPCLK
AK6 C29 3 6
-HA27 A28 RSV25 -INIT
AA1 E31 4 5
-HA26 A27 RSV24
Y3 E29
-HA25 A26 RSV23
AF6 E21
-HA24 A25 VCORE_DET R33 470 0603
AB4 E23
-HA23 A24 VTT -FLUSH
AB6
A23 FSB FREQ SELECT PIN RSV20
F10 1 2
-HA22 AE3 AL13
-HA21 A22 ======================== RSV19
AJ1
A21 RSV18
AL11 V00-V0A
-HA20 AC3 BSEL1 BSEL0 FREQ Y1 (330 -> 470)
-HA19 A20 RSV17
AG3 0 0 66MHz AK24
-HA18 A19 RSV16
Z6 X6
-HA17 AE1
A18 0 1 100MHz RSV15
X2
-HA16 A17 BRI#
AN7
A16
1 0 RESERVED RSV13
R2
-HA15 AL5 V4
-HA14 A15 1 1 133MHz RSV12
AK14 W3
-HA13 A14 RSV11
AL7 AK30
-HA12 A13 RSV10
1
AN5 AC1 1

-HA11 A12 RSV9

AK10
A11 RSV8
AK16 Modify by 12/15 '00
-HA10 AH6 AN11 Modify by 2/21 '01
-HA9 A10 RSV7
AL9 AF4
-HA8 A9 RSV6
AH10 AH20
-HA7 A8 RSV5 -CPURST
AL15 AH4

RESERVED
-HA6 A7 RSV4
AN9 AN15
VTT -HA5 A6 RSV3
AH8 AN13 V00-V0A
REQ#4
REQ#3
REQ#2
REQ#1
REQ#0
VREF7
VREF6
VREF5
VREF4
VREF3
VREF2
VREF1
VREF0

VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
-HA4 A5 RSV2

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2

VSS0
AH12 AN21 (Short)
VID3
VID2
VID1
VID0

-HA3 A4 VTT
AK8 AN23
A3 RSV0
1

AM36

AM34
AM30
AM26
AM22
AM18
AM14
AM10
AH18
AH16

AD34

AC33

AH34
AK22
AK12

AK18

AB32

AK36
AF32

AF36
AL17
AL19

AL37

AL35
AJ37

AJ31
AJ27
AJ23
AJ19

AJ15
AJ11

AM6
AM2
AG5
AD6

M34

AD2
AC5

AH2

AN3
AK4
R34

H34

D18
D22
D26
D30
D34
E33

X36
P32

X32

Y37
Y33

P36

K36
V34

A37
B28
B32
B20
B24

B12

B16

E11
E19
E15

AL3
AL1
R45
F18

Z34

T32
T36

F20
F28
F24

F36
F32

AJ3

AJ7 ONLY FOR Cm-256

M2
G5

Q5
R6

D2
D4

H2

U5
V6

K4

B4
B8

E7

V2

Y5

Z2
L5

75
0603
1%
AGTL_VREF AGTL_VREF=VTT*2/3=1V
2
1

-HREQ4
-HREQ3
-HREQ2
-HREQ1
-HREQ0

CLKREF=VCC25*1/2=1.25V BSEL1
16 BSEL1
1

R29 C629 C56 C63 C80 C635

150 2.2U 0.1U 0.1U 0.1U 0.1U
0603 1206 0603 0603 0603 0603 VCC2.5
1% 16V 50V 50V 50V 50V
2

2
2

R37
150
-HREQ[0..4] 0603
5,6 -HREQ[0..4] PVID[0..3] 1%
PVID[0..3] 20
CLKREF
2

PVID0
1

PVID1
1

PVID2 R36 C66

PVID3 150 4.7U_NA
0603 1206
1% 16V
2

Title
2

V00-V0A Central Processor Unit

(Add NA)
Size Document Rev
411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 4 of 22
A B
 A B

AGTL PLUS BUS TERMINATION

-HA[3..31] -HD[0..63]
4,6 -HA[3..31] 4,6 -HD[0..63]
VTT VTT
VTT VTT VTT VTT

RP21
RP18 RP11 -DRDY 1 10
-HD10 4,6 -DRDY -DBSY -RS2
-HA8 1 10 1 10 2 9
-HD12 -HD13 4,6 -DBSY -RS0 -RS2 4,6
-HA11 2 9 -HA4 2 9 3 8
-HD18 -HD11 4,6 -RS0 -HTRDY
-HA6 3 8 -HA14 3 8 4 7
-HD14 -HD9 4,6 -HTRDY -PRDY -ADS 4,6
-HA9 4 7 -HA7 4 7 5 6
-HA28 -HD2 -PRDY 4
5 6 5 6
56X8
56X8 56X8 RP20
RP17 RP12 -HITM 1 10
4,6 -HITM
-HA3 1 10 -HD0 1 10 -HLOCK 2 9
-HD6 -HD17 4,6 -HLOCK -RS1
-HA16 2 9 -HA25 2 9 -HREQ2 3 8
-HD15 -HD8 4,6 -HREQ2 -RS1 4,6
-HA13 3 8 -HA10 3 8 -HREQ3 4 7 -HIT
-HA15 -HD4 -HD5 4,6 -HREQ3 -HIT 4,6
-HA5 4 7 4 7 5 6 -CPURST
-HD1 -CPURST 4,6,11
5 6 -HA12 5 6

1
56X8
56X8 56X8 R63
RP14 RP10 56_NA
-HA21 1 10 -HD20 1 10 0603
-HA24 2 9 -HA20 -HD3 2 9 -HD16
-HA19 -HA23 -HD7 -HD23

2
3 8 3 8 -BREQ0 4,6
-HA31 4 7 -HA17 -HD30 4 7 -HD21

1
5 6 -HA22 5 6 -HD24
R62
56X8 56X8 56
RP13 RP9 0603
1 10 -HD26 1 10
-HA18 -HD25 -HD31

2
2 9 -BP3 4 2 9
-HA30 3 8 -HD33 3 8 -HD32
-HA26 -BP2 4 -HD19 -HD29
-HA27 4 7 4 7
5 6 -HA29 5 6 -HD35
2 2

56X8 56X8
RP6 CPU DEBUG PORT
-HD28 1 10
RP19 -HD22 2 9 -HD39
-HREQ4 1 10 -HD34 3 8 -HD37 VCC_CMOS
4,6 -HREQ4 -BNR -BPRI -HD43 -HD36
2 9 4 7 Must be added
4,6 -BNR -BPRI 4,6 -HD38
3 8 -HREQ1 5 6 termination in debug bd V00-V0A
-HREQ1 4,6
4 7 -HREQ0 are below (330->470)
-DEFER -HREQ0 4,6
5 6 56X8
-DEFER 4,6

1
RP8 gtl_cpurst#:240ohm
56X8 -HD27 1 10 cpu_tck:47ohm R56 R513 R55 R26 VCC_CMOS
-HD44 2 9 -HD47 cpu_tms:47 ohm 150 1K 1K 470
-HD45 3 8 -HD41 VCC3 0603 0603 0603 0603
R22 -HD42 4 7 -HD49
-HD51 J500

2
4 -BPM0 1 2 5 6

1
1
56 0603 56X8 R52 1
4,6,11 -CPURST 2
10K 2
RP5 4 TCK 3
R25 -HD40 0603 3
1 10 4 TMS 4
-HD52 -HD46 4
4 -BPM1 1 2 2 9 4 TDI 5
-HD48 -HD55 -DBRESET 5

2
3 8 6
56 0603 -HD59 -HD57 6
4 7 4 TDO 7
-HD63 7
5 6 4 -TRST 8
8
4 -PRDY 1 2 9
56X8 R58 240_NA 0603 9
4 -PREQ 10
10
RP7 11
11

1
-HD54 1 10 12
-HD53 -HD56 R514 12
2 9
-HD58 3 8 -HD61 1K
FPC/FFC-12P/1MM/NA
-HD50 4 7 -HD62 0603
5 6 -HD60

2
56X8
V00-V0A
(C515,516 ->NA)
(C533,C633,C634 ->NA)
(C519 ->NA)
FOR TERMINATION DECOUPLING FOR VCC_CORE DECOUPLING
VTT VTT VCC_CORE VCC_CORE
Layout Note:
VTT
1

C81 C82 C39 C25 C29 C22 C28 C60 C508 C634 C633 C533 C515 C516
1U 1U 0.1U 0.1U 0.1U 0.1U 0.1U + 82U + 82U_NA 10U_NA 10U_NA 10U_NA 10U_NA 10U_NA
0603 0603 0603 0603 0603 0603 0603 7343 7343 1206 1206 1206 1206 1206
50V 50V 50V 50V 50V 2.5V 2.5V 10V 10V 10V 10V 10V
2

56 Ohm Res.
2

2
1

C33 C38 VTT VCC_CORE C525 C588

0.1U 0.1U 1U 1U
0603 0603 0603 0603
50V 50V
2

2
1

C40 C49 C58 C89 C72 C68 C51 C519 C73 C628
0.1U
0603
0.1U
0603
0.1U
0603
0.1U
0603
0.1U
0603
+ 82U
7343
+ 82U
7343
10U_NA
1206
10U
1206
10U
1206
L2 < 2"
50V 50V 50V 50V 50V 2.5V 2.5V 10V 10V 10V
2

2
2

2
1

C79 C91 C55 C67

0.1U 0.1U 1U 1U
0603 0603 0603 0603
50V 50V
NB CPU
2

VTT VCC_CORE

1.5"<L1<4.5"
1

C92 C93 C77 C78 C90 C48 C599 C598 C45 C594 C44 C517
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V
2

2
1

VTT VCC_CORE C53 C52

0.1U 0.1U
0603 0603
50V 50V
2

1 1
1

C75 C74 C62 C64 C65 C595 C43

10U 10U 0.1U 0.1U 0.1U 0.1U 0.1U
1206 1206 0603 0603 0603 0603 0603
10V 10V 50V 50V 50V 50V 50V
2

C522 C520
0.1U 0.1U
0603 0603
50V 50V
2

CLOSE TO SOCKET 370

VCC_CORE
1

C527 C528 C529 C532 C531

1

0.1U 0.1U 0.1U 0.1U 0.1U C514 C518

0603 0603 0603 0603 0603 0.1U 0.1U
50V 50V 50V 50V 50V 0603 0603
2

50V 50V
2

VCC_CORE
1

C512 C513
0.1U 0.1U
0603 0603
1

50V 50V
2

C530 C526 C524 C523 C521

0.1U 0.1U 0.1U 0.1U 0.1U
0603 0603 0603 0603 0603
50V 50V 50V 50V 50V
2

Title
CLOSE TO SOCKET 370 VTT TERMINATION

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 5 of 22
A B
 A B

NORTH BRIDGE PARTIAL I

MD[0..63] AD[0..31]
8 MD[0..63] U501B AD[0..31] 10,14,19
MD0 M23 AF14 AD0
-HA[3..31] -HD[0..63] MD1 MD0 AD0 AD1
4,5 -HA[3..31] -HD[0..63] 4,5 K25 AE14
U501A MD2 MD1 AD1 AD2
L26 AE13
-HA3 -HD0 MD3 MD2 AD2 AD3
A25 E19 L25 AF13
-HA4 HA3 HD0 -HD1 MD4 MD3 AD3 AD4
D24 B18 M26 AC14
-HA5 HA4 HD1 -HD2 MD5 MD4 AD4 AD5
B25 B16 M24 AB14
-HA6 HA5 HD2 -HD3 MD6 MD5 AD5 AD6
B26 A16 N26 AC13
-HA7 HA6 HD3 -HD4 MD7 MD6 AD6 AD7
E23 C18 N24 AB13
-HA8 HA7 HD4 -HD5 MD8 MD7 AD7 AD8
C26 C17 P23 AE12
-HA9 HA8 HD5 -HD6 MD9 MD8 AD8 AD9
C24 D18 P25 AD12
-HA10 HA9 HD6 -HD7 MD10 MD9 AD9 AD10
A23 D15 R23 AB12
-HA11 HA10 HD7 -HD8 MD11 MD10 AD10 AD11
C25 D17 R25 AC12
-HA12 HA11 HD8 -HD9 MD12 MD11 AD11 AD12
D22 C16 P22 AF11
-HA13 HA12 HD9 -HD10 MD13 MD12 AD12 AD13
B24 B17 T23 AE11
-HA14 HA13 HD10 -HD11 MD14 MD13 AD13 AD14
D25 D16 T25 AD11
-HA15 HA14 HD11 -HD12 MD15 MD14 AD14 AD15
F22 A17 T22 AC11
2 -HA16
-HA17
C23
D21
HA15
HA16
HD12
HD13
A15
E16
-HD13
-HD14
PANEL TYPE SELECT SW1 MD16
MD17
AD22
AF22
MD15
MD16
AD15
AD16
AA8
AC9
AD16
AD17
2

-HA18 HA17 HD14 -HD15 MD18 MD17 AD17 AD18

A20 D19 AB21 AF8
-HA19 HA18 HD15 -HD16 MD19 MD18 AD18 AD19
C22 A14 AE21 AE8
-HA20 A21
HA19
HA20
HD16
HD17
E18 -HD17 LCD 1-8 2-7 3-6 4-5 MD20 AB20
MD19
MD20
AD19
AD20
AE7 AD20
-HA21 B23 E17 -HD18 MD21 AD20 AB8 AD21
-HA22 HA21 HD18 -HD19 MD22 MD21 AD21 AD22
A22 B14 AE20 AF7
-HA23 HA22 HD19 -HD20 MD23 MD22 AD22 AD23
B21 C15 AC19 AC8
-HA24 E20
HA23
HA24
HD20
HD21
E14 -HD21 1024x768 OFF OFF OFF ON MD24 AF19
MD23
MD24
AD23
AD24
AC7 AD24
-HA25 B22 B11 -HD22 MD25 AC18 AB7 AD25
-HA26 HA25 HD22 -HD23 MD26 MD25 AD25 AD26
B19 D14 AE18 AF6
-HA27 HA26 HD23 -HD24 MD27 MD26 AD26 AD27
C20 B15 AD17 AE6
-HA28 HA27 HD24 -HD25 MD28 MD27 AD27 AD28
A24 D13 AF17 AD6
-HA29 HA28 HD25 -HD26 MD29 MD28 AD28 AD29
B20 C13 AB17 AC6
-HA30 HA29 HD26 -HD27 MD30 MD29 AD29 AD30
D20 E9 AE16 AB6
-HA31 HA30 HD27 -HD28 MD31 MD30 AD30 AD31 -CBE[0..3]
C21 C12 AC16 AF5 -CBE[0..3] 10,14,19
ZV_Y[0..7] HA31 HD28 -HD29 MD32 MD31 AD31
14 ZV_Y[0..7] D12 K26
HD29 -HD30 MD33 MD32 -CBE0
E15 L23 AF12
ZV_Y0 HD30 -HD31 MD34 MD33 C/BE0# -CBE1
R6 A13 M22 AB11
ZV_Y1 LD0 HD31 -HD32 VCC3 MD35 MD34 C/BE1# -CBE2
T2 B12 L24 AD9
ZV_Y2 LD1 HD32 -HD33 MD36 MD35 C/BE2# -CBE3
T1 B13 M25 AD7
ZV_Y3 LD2 HD33 -HD34 MD37 MD36 C/BE3#
R5 A12 N23
ZV_Y4 LD3 HD34 -HD35 MD38 MD37 -FRAME
R2
LD4 HD35
E13 Modify by 2/21 '01 N25
MD38 FRAME#
AE9 -FRAME 10,14,19
ZV_Y5 R4 D11 -HD36 MD39 N22 AC10 -IRDY
ZV_UV[0..7] ZV_Y6 LD5 HD36 -HD37 MD40 MD39 IRDY# -IRDY 10,14,19
R1 D10 P26 AD10 -TRDY
14 ZV_UV[0..7] ZV_Y7 LD6 HD37 -HD38 MD41 MD40 TRDY# -TRDY 10,14,19
R3 A11 V0.1->V0.2 P24 AE10 -STOP
LD7 HD38 MD41 STOP# -STOP 10,14,19

4
3
2
1
ZV_UV0 P5 E10 -HD39 (Del RP24,Change MD42 R26 AB9 -DEVSEL
ZV_UV1 LD8 HD39 -HD40 MD43 MD42 DEVSEL# -DEVSEL 10,14,19
P2 E8 RP27 R24 AB10 PAR
ZV_UV2 P3
LD9 HD40
C9 -HD41 RP27 Location) 10K*4 MD44 R22
MD43 PAR
AF10 -SERR
PAR 10,14,19
ZV_UV3 LD10 HD41 -HD42 MD45 MD44 SERR# -SERR 10,14,19
P4 D9 1206 T26 AE5 -PLOCK
ZV_UV4 LD11 HD42 -HD43 MD46 MD45 LOCK# -PLOCK 10
N5 C11 T24 AC15 -PCIREQ
ZV_UV5 LD12 HD43 -HD44 MD47 MD46 PREQ# -PCIGNT -PCIREQ 10
N2 B10 U23 AD15 -PCIGNT 10
ZV_UV6 LD13 HD44 -HD45 MD48 MD47 PGNT#
N1 A10 AE22
ZV_UV7 LD14 HD45 -HD46 MD49 MD48 -REQ0

5
6
7
8
N4 E7 AC21 AC5 -REQ0 14
LD15 HD46 -HD47 MD50 MD49 REQ0# -REQ1
D8 SW1 AD21 AD5
VCC3 ZV_HREF HD47 -HD48 MA0 MD51 MD50 REQ1# -REQ2
14 ZV_HREF T3 B8 1 8 AF21 AE4
VCC3 R77 ZV_SYNC HREF HD48 -HD49 MA1 MD52 MD51 REQ2# -REQ3
14 ZV_SYNC U1 C10 2 7 AC20 AD4 -REQ3 19
4.7K ZV_PCLK VS HD49 -HD50 MA13 MD53 MD52 REQ3#
14 ZV_PCLK U3 B6 3 6 AF20
LCLK HD50 MD53
1

1 0603 2 SPCLK1 B9 -HD51 MA14 4 5 MD54 AB19 AB5 -GNT0

-GNT0 14
R152 REFCLK0 HD51 -HD52 MD55 MD54 GNT0# -GNT1
16 REFCLK0 A2 F8 AE19 AF4
100K XIN HD52 MD55 GNT1#
1 2 SPD1 TP1 1 A3 D6 -HD53 HDS404E MD56 AB18 AF3 -GNT2
0603 R75 SPCLK1 XOUT HD53 -HD54 MD57 MD56 GNT2# -GNT3
9 SPCLK1 F3 D7 AD18 AE3 -GNT3 19
4.7K SCL SPCLK1 HD54 -HD55 MD58 MD57 GNT3#
9 SCL M2 C7 AA19
0603 SPD1 SPCLK2 HD55 -HD56 MD59 MD58 -REQ4
V00-V0A
2

9 SPD1 F2 E5 AE17 AF2 -REQ4 11

R41 SDA SPD1 HD56 -HD57 MD60 MD59 REQX# -GNT4
(R75,R77 NA) 9 SDA M3
SPD2 HD57
A7
-HD58 MD61
AC17
MD60 GNTX#
AE2 -GNT4 11
0 (R68,R81 from 4.7K)VCC2.5 TP13 1 AA12 E6 AD16 AB15 NBPCLK NBPCLK 16
VCC3
GPOUT HD58 -HD59 MD62 MD61 PCLK
0603 TP501 1 C3 B7 AF16 AF15 -PCLKRUN -PCLKRUN 10,11,14,19
GOP0 HD59 -HD60 MA[0..14] MD63 MD62 PCKRUN#
1 2 C4 C6 8,16 MA[0..14] AB16 W5 -INTB 10
AGPBSY 1 0 2 STP_AGP HD60 -HD61 MD63 INTA#
(Del R147-0ohm) 11 AGPBSY B4 D5 AA11 R90 1 10K 2 0603
R94 0603 AGP_BUSY HD61 -HD62 MA0 WSC#
F5 A6 AA23
R517 1 SUSPEND HD62 -HD63 MA1 MA0 TVD11 TP502 TVD11
2 F4 A8 AB23 G2 1 TVD11 9
10K 0603 STANDBY HD63 MA2 MA1 FPD0/TVD11 TVD10 TP503 TVD10
3 AB26 H2 1 TVD10 9
-SUSA R1 Q16 VTTREF -ADS MA3 MA2 FPD1/TVD10 TP560
4,9,11,16,17 -SUSA 2 E12 J24 -ADS 4,5 AB25 H1 1
GTLREF0 ADS# MA3 FPD2
1DTC144TKA E21 MA4 AB24 J2 1 TP561
R85 GTLREF1 -BNR MA5 MA4 FPD3 TFT_B2
1 2 4.7K 0603 K24 D26 -BNR 4,5 AC26 J1 1 TP4
R68 PLLTST BNR# MA6 MA5 FPD4 TFT_B3
1 2 0 0603 F15 AC25 H4 1 TP5
R81 BISTIN -BPRI MA7 MA6 FPD5
1 2 0 0603 F11 E26 -BPRI 4,5 AC24 K6 1 TP562
VCC_CRT DFTIN BPRI# MA8 MA7 FPD6 TP563
Mpdify by 12/15 '00 AD26
MA8 FPD7
J4 1
R69 1 140 1% 2 0603 E3 H26 -DBSY MA9 AD25 J3 TVD9 1 TP504 TVD9
RESET DBSY# -DEFER -DBSY 4,5 MA10 MA9 FPD8/TVD9 TVD8 TVD8 TVD9 9
1 2 E4 F26 AE26 L5 1 TP564
RED COMP DEFER# -DRDY -DEFER 4,5 MA11 MA10 FPD9/TVD8 TVD8 9
C2 J23 AD24 K2 1 TP565
VTT 9 RED BLUE RED DRDY# -DRDY 4,5 MA12 MA11 FPD10
D2 AE24 J5 1 TP566
9 BLUE GREEN BLUE -HIT MA13 MA12 FPD11 TFT_G2
C104 D3 G24 AE25 K1 1 TP6
9 GREEN HSYNC GREEN HIT# -HITM -HIT 4,5 -CS[0..3] MA14 MA13/BA0 FPD12
0.1U E2 G26 AF25 K3 1 TP567
9 HSYNC HSYNC HITM# -HITM 4,5 8 -CS[0..3] MA14/BA1 FPD13
1

50V GND_CRT VSYNC E1 L6 1 TP568

9 VSYNC VSYNC -HLOCK -CS0 FPD14
R65 0603 G23 Y26 L2 1 TP569 R664
75 HLOCK# -HLOCK 4,5 -CS1 CS0#/RAS0# FPD15 TVCLKR1 TVCLKR1 1
TXOUT0+ AA3 Y25 K5 1 TP7 2
0603 9 TXOUT0+ TXOUT1+ Y0P -HTRDY -CS2 CS1#/RAS1# FPD16/TVCLKR TVCLKR 9
W4 G25 Y24 L1 1 TP570 0
1% 9 TXOUT1+ Y1P HTRDY# -HTRDY 4,5 -CS3 CS2#/RAS2# FPD17/TVBLANK#
TXOUT2+ Y5 Y23 L3 1 TP571 0603
9 TXOUT2+ TXOUT0- Y2P -HREQ0 CS3#/RAS3# FPD18
AGTL_VREF=VTT*2/3=1V TP18 TP109
2

9 TXOUT0- AB3 E24 1 Y22 M6 1

TXOUT1- Y0M HREQ0# -HREQ1 -DQMA[0..7] TP16 CS4#/RAS4# FPD19 TFT_R2 TP8
9 TXOUT1- Y4 F23 8 -DQMA[0..7] 1 W21 K4 1
Y1M HREQ1# CS5#/RAS5# FPD20
1

TXOUT2- AA5 F24 -HREQ2 M4 1 TP573

9 TXOUT2- Y2M HREQ2# FPD21
1

R76 C115 C99 C120 C124 TX2OUT0+ AC2 F25 -HREQ3 -DQMA0 V23 M5 1 TP574
9 TX2OUT0+ TX2OUT1+ Z0P HREQ3# -HREQ4 -DQMA1 DQM0/CAS0# FPD22
150 1U 1U 1000P 1000P AC3 E25 W23 M1 1 TP575
9 TX2OUT1+ Z1P HREQ4# -DQMA2 DQM1/CAS1# FPD23 TVD6 TVD6
0603 0603 0603 0603 0603 TX2OUT2+ AA4 AF24 T6 1 TP9
9 TX2OUT2+ TX2OUT0- Z2P -RS0 -HREQ[0..4] -DQMA3 DQM2/CAS2# FPD24/TVD6 TVD4 TVD4 TVD6 9
1% TP10
2

10V 10V 50V 50V 9 TX2OUT0- AD2 H23 -HREQ[0..4] 4,5 AE23 T5 1 TVD4 9
TX2OUT1- Z0M RS0# -RS1 -DQMA4 DQM3/CAS3# FPD25/TVD4 TVD5 TP506 TVD5
2

9 TX2OUT1- AD3 K23 W26 U4 1 TVD5 9

TX2OUT2- Z1M RS1# -RS2 -DQMA5 DQM4/CAS4# FPD26/TVD5 TVD7 TP508 TVD7
9 TX2OUT2- AB4 H25 W25 U2 1 TVD7 9
TXCLK+ Z2M RS2# -DQMA6 DQM5/CAS5# FPD27/TVD7 TVD0 TP509 TVD0
9 TXCLK+ AB1 AD23 V1 1 TVD0 9
TXCLK- YCP -RS[0..2] -DQMA7 DQM6/CAS6# FPD28/TVD0 TVD1 TP510 TVD1
9 TXCLK- AC1 A19 -RS[0..2] 4,5 AF23 V2 1 TVD1 9
TX2CLK+ YCM CPURST# DQM7/CAS7# FPD29/TVD1 TVD3 TP511 TVD3
9 TX2CLK+ AD1 E22 1 V3 1 TVD3 9
TX2CLK- ZCP CPURSTD# TP3 R248 2-CPURST -SCASA FPD30/TVD3 TV_VSYNC TP512 TV_VSYNC
9 TX2CLK- AE1 1 -CPURST 4,5,11 8 -SCASA U22 W3 1 TV_VSYNC 9
ZCM -BREQ0 CKE3 SCASA# FPD31/TVVS TVCLK TP17 TVCLK
1 J25 -BREQ0 4,5 8 CKE3 V25 V4 1 TVCLK 9
NBHCLK TP104 BREQ0# 0 CKE1 SCASB#/CKE3 FPD32/TVCLK TVD2 TP505 TVD2
1
16 NBHCLK G22 8 CKE1 V24 U5 1 TVD2 9
1

DCLKO HCLK SCASC#/CKE1 FPD33/TVD2 TV_HSYNC TV_HSYNC

16 DCLKO 1 R74 2 10 0603 J22 0603 V5 1 TP14
TV_HSYNC 9
DCLKI MCLKO -SWEA FPD34/TVHS TP2
16 DCLKI K22 8 -SWEA U24 C5 1
-PCIRST MCLKI CKE2 SWEA#/MWEA FPD35
9,10,12,14,18,19 -PCIRST AE15
PCIRST# V00-V0A 8 CKE2 U25
SWEB#/MWEB#/CKE2
PWROK AD14 ( Del NA) CKE0 U26 AA16
4,11,17 PWROK PWROK 8 CKE0 SWEC#/MWEC#/CKE0 PANELDET VCC3
1 2 AC22 G3 1 TP576
11 -SUSST SUST# -SRASA AA24 PANELVS
0 0603 R30 G5 1 TP110 V00-V0A
-SUSA 8 -SRASA SRASA# PANELHS
1 2 TWISTER TP514 1 AA26 H3 1 TP578 (Del DSTN)
0603 R35 TP513 SRASC#/CKE4 PANELDEN TP579
BGA516_36 1 AA25 G4 1
0/NA SRASB#/CKE5 PANELCLK TP580
V00-V0A FPGPIO
G1 1
(Add -SUSA) F1 ENPVDD
ENVDD ENPBLT ENPVDD 9
H5 ENPBLT 22
ENVEE
Don't Stuff
V00-V0A TWISTER
1

C123 C274 (From 10*8) VCC3 BGA516_36 Modify by 12/15 '00

10P_NA 10P_NA Modify by 2/21 '01
0603 0603
V00-V0A
2

RP516 (Del R518,R519)

-REQ0 1 10
-REQ1 2 9 -GNT0
-REQ2 3 8 -GNT1
-REQ3 4 7 -GNT2
5 6 -GNT3

Modify by 12/15 '00 4.7K*8 1206

1 2 -REQ4
R521 10K 0603

1 2 -GNT4
R520 10K 0603

1 2 -PCIREQ
R127 10K 0603

1 2 -PCIGNT Title
R522 10K 0603 North Bridge Partial I

1 2 MA6 Size Document Rev

R93 10K/NA 0603 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 6 of 22
A B
 5
NORTH BRIDGE PARTIAL II 4 3 2 1

VCC_PLL2 L29 VCC2.5 VCC_PLL1 L24 VCC2.5

120Z/100M 120Z/100M
1608 1608
1 2 1 2
C97 C125

1
10U_NA 10U_NA
D 1206
10V
C103
1U
0603
C109
1000P
0603 1
L28
2
1206
10V
C116
1U
0603
C107
1000P
0603 1
L23
2
D

2
10V 50V 10V 50V

JP_BEAD_DFS JP_BEAD_DFS
GND_PLL2 GND GND_PLL1 GND
V00-V0A V00-V0A
(From bead)) (From bead))

VCC2.5

U501C
AA9 A9
VC25_0 GND0
AA18 A18
VC25_1 GND1
F9 A26
VC25_2 GND2
F18 AA6
VC25_3 GND3
J6 AA13
VC25_4 GND4
J21 AA14
VC25_5 GND5
V6 AA15
VC25_6 GND6
V21 AA21
VC25_7 GND7 VCC_A L32 VCC2.5 VCC_CRT L30 VCC2.5
J11 AC4
VC25_8 GND8 120Z/100M 120Z/100M
J12 AC23
VC25_9 GND9 1608 1608
J15 AD8
VC25_10 GND10
J16 AD13 1 2 1 2
VC25_11 GND11 C134 C137
L9 AD19
VC25_12 GND12

1
L18 AF1 10U_NA C135 C136 10U_NA C126 C121
VC25_13 GND13 1206 L33 1206 L25
M9 AF9 1U 1000P 1U 1000P
VC25_14 GND14 10V 0603 0603 1 10V 0603 0603
M18 AF18 2 1 2
VC25_15 GND15

2
R9 AF26 10V 50V 10V 50V
VC25_16 GND16
T9 B2
VC25_17 GND17 JP_BEAD_DFS JP_BEAD_DFS
T18 C14
VC25_18 GND18
U18
VC25_19 GND19
C19 GND_A GND GND_CRT GND
V10 D4
VCC3 VC25_20 GND20
V13 D23
VC25_21 GND21
V15
VC25_22 GND22
F6 V00-V0A V00-V0A
GND23
F13 (From bead)) (From bead))
AA7 F14
VCC3_0 GND24
AA10 F16
VCC3_1 GND25
AA17 F21
VCC3_2 GND26
C AA20
F7
F10
VCC3_3
VCC3_4
GND27
GND28
H24
J26
M21
C
VCC3_5 GND29
F12 N3
VCC3_6 GND30
F17 N6
VCC3_7 GND31
F20 N21
VCC3_8 GND32
G6 P1
VCC3_9 GND33
G21 P6
VCC3_10 GND34
H6 P21
VCC3_11 GND35
K21 T21
VCC3_12 GND36
L4
VCC3_13 GND37
V26 V00-V0A
T4
VCC3_14 GND38
W24 (From bead)) VCC_PLLA
U21 L11 VCC2.5
VCC3_15 GND39
W6 L13
VCC3_16 GND40 L504 L503
Y6 L14
VCC3_17 GND41
Y21
VCC3_18 GND42
L16 GND 1 2 1 2
J9 M12 VDD_LA
VCC3_19 GND43
J10 M13
VCC3_20 GND44 JP_BEAD_DFS JP_BEAD_DFS VCC3 VCC_LVDS
J13 M14
VCC3_21 GND45
J14 M15
VCC3_22 GND46

1
L34
J17 N11 C538 C539
VCC3_23 GND47

1
J18
VCC3_24 GND48
N12 C536 C537 10U_NA 0.1U V00-V0A V00-V0A 1 2
K9 N13 0.1U 0.1U 1206 0603 (From bead)) (From bead))
VCC3_25 GND49 0603 0603 10V 50V

2
K18 N14
VCC3_26 GND50

1
50V 50V L505 JP_BEAD_DFS

2
L12 N15 C159
VCC3_27 GND51
L15 N16 1 2 0.1U
VCC3_28 GND52 0603
M11 P11
VCC3_29 GND53 50V

2
M16 P12
VCC3_30 GND54 JP_BEAD_DFS
N9
VCC3_31 GND55
P13 GND
N18
VCC3_32 GND56
P14 GND_LVDS GND
P9 P15
VCC3_33 GND57
P18 P16
VCC3_34 GND58
R16 R12
VCC3_35 GND59
R18 R13
VCC3_36 GND60
T15 R14
VCC3_37 GND61
U9 R15
VCC3_38 GND62
V9 T11
VCC3_39 GND63
V11 T13
VCC3_40 GND64
V12 T14
VCC3_41 GND65
V14 T16
VCC3_42 GND66
V16
VCC3_43
V17 L21
B VCC5
V18
R11
T12
VCC3_44
VCC3_45
VCC3_46
GNDA0
GNDA1
L22

B1
B
VCC_PLL2 VCC_PLL1 VCC_A VCC3_47 GNDDAC
GNDPLL1
A4 GND_A
U6 B5 VCC3
VCC5 GNDPLL2
H21
VCCA0
H22
VCCA1 GNDRGB
A1 GND_PLL1
C1
VCCDAC GNDS
C8 GND_PLL2

1
VCC_CRT
B3
VCCPLL1 V00-V0A C155 C133 C130 C149 C118 C119 C148 C163 C157 C146 C143
A5
VCCPLL2 LVDS1GND
AA1 GND_CRT (Add NA) 10U_NA 10U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
VDD_LA Y1 1206 1206 0603 0603 0603 0603 0603 0603 0603 0603 0603
LVDSGND 10V 10V 50V 50V 50V 50V 50V 50V 50V 50V 50V

2
D1 Y3
VCC2.5 VCCRGB PLLGND
Y2
VDDD VSSD
AA2 GND_LVDS
AA22 R21
VCC_LVDS VSUS25 N/C0 VCC3
N/C1
E11 GND
VCC_PLLA W2 F19
LVDS1VCCA N/C2
W1
LVDSVCCA N/C3
AB22 GND
AB2 V22
PLLVCCA N/C4
W22
N/C5
TWISTER
BGA516_36

Layout Note:
All L/C near NB for this page.

VCC2.5
1

1
C150 C132 C156 C139 C152 C129 C141 C142
10U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
A 1206
10V
0603
50V
0603
50V
0603
50V
0603
50V
0603
50V
0603
50V
0603
50V A
2

2
GND

Title
Nouth Bridge Partial II

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 7 of 22

5 4 3 2 1
 A B

SYSTEM MEMORY

SO-DIMM Module

VCC3 VCC3

MA[0..14]
6,16 MA[0..14] Close to SO-DIMM Module
J502 VCC3
J501 1 2
MA4 MAA4 1 2
1 16 1 2 MDD0 3 4 MDD32
MA3 MAA3 3 4
2
2 15 MDD0 3 4 MDD32 MDD1 5 6 MDD33 2
5 6

1
MA2 3 14 MAA2 RP509 MDD1 5 6 MDD33 MDD2 7 8 MDD34 C117 C106 C108 C544
MA7 MAA7 0*8 7 8
4 13 MDD2 7 8 MDD34 MDD3 9 10 MDD35 10U/NA 10U/NA 10U/NA 10U/NA
MA6 MAA6 RPX8 9 10 1206 1206 1206 1206
5 12 MDD3 9 10 MDD35 11 12
MA5 MAA5 11 12 16V 16V 16V 16V

2
6 11 11 12 MDD4 13 14 MDD36
MA0 MAA0 13 14
7 10 MDD4 13 14 MDD36 MDD5 15 16 MDD37
MA9 MAA9 15 16
8 9 MDD5 15 16 MDD37 MDD6 17 18 MDD38
MA8 MAA8 17 18
1 16 MDD6 17 18 MDD38 MDD7 19 20 MDD39
MA1 MAA1 19 20
2 15 MDD7 19 20 MDD39 21 22
MA10 MAA10 RP510 21 22
3 14 21 22 -MDQMA0 23
23 24
24 -MDQMA4 Close to SO-DIMM Module
MA11 4 13 MAA11 0*8 -MDQMA0 23 24 -MDQMA4 -MDQMA1 25 26 -MDQMA5
MA13 MAA13 RPX8 25 26 VCC3
5 12 -MDQMA1 25 26 -MDQMA5 27 28
MA12 MAA12 27 28
6 11 27 28 MAA0 29 30 MAA3
MA14 MAA14 29 30
7 10 MAA0 29 30 MAA3 MAA1 31 32 MAA4
-CS2 -MCS2 31 32
6 -CS2 8 9 MAA1 31 32 MAA4 MAA2 33 34 MAA5
-CS3 -MCS3 33 34
6 -CS3 1 16 MAA2 33 34 MAA5 35 36
35 36

1
-SCASA 2 15 -MSCASA 35 36 MDD8 37 38 MDD40 C127 C96 C175 C98 C177
6 -SCASA 37 38
-SWEA 3 14 -MSWE A RP508 MDD8 37 38 MDD40 MDD9 39 40 MDD41 0.1U 0.1U 0.1U 0.1U 0.1U
6 -SWEA 39 40
-CS1 4 13 -MCS1 0*8 MDD9 39 40 MDD41 MDD10 41 42 MDD42 0603 0603 0603 0603 0603
6 -CS1 41 42 50V 50V 50V 50V 50V
-CS0 -MCS0 RPX8

2
6 -CS0 5 12 MDD10 41 42 MDD42 MDD11 43 44 MDD43
-SRASA -MSRASA 43 44
6 -SRASA 6 11 MDD11 43 44 MDD43 45 46
45 46
7 10 45 46 MDD12 47 48 MDD44
47 48 VCC3
8 9 MDD12 47 48 MDD44 MDD13 49 50 MDD45
MD5 MDD5 49 50
1 16 MDD13 49 50 MDD45 MDD14 51 52 MDD46
MD36 MDD36 51 52
2 15 MDD14 51 52 MDD46 MDD15 53 54 MDD47
MD4 MDD4 RP505 53 54
3 14 MDD15 53 54 MDD47 55 56
MD7 MDD7 0*8_DFS 55 56
4 13 55 56 57 58
57 58

1
MD38 5 12 MDD38 RPX8 57 58 59 60 C176 C95 C3 C16 C128
MD37 MDD37 59 60
6 11 59 60 0.1U 0.1U 0.1U 4.7U_NA 4.7U_NA
MD39 7 10 MDD39 0603 0603 0603 0805 0805
MD6 MDD6 SDRAMCLK0 50V 50V 50V +80-20% +80-20%

2
8 9 16 SDRAMCLK0 61 62 CKE0
MD41 MDD41 SDRAMCLK2 CKE2 61 62 CKE0 6
1 16 16 SDRAMCLK2 61 62 CKE2 6 63 64
MD9 MDD9 63 64
2 15 63 64 -MSRASA 65 66 -MSCASA
MD40 MDD40 RP506 -MSCASA 65 66 CKE1
3 14 -MSRASA 65 66 -MSWEA 67 68
67 68 CKE1 6

1
MD8 4 13 MDD8 0*8_DFS -MSWE A 67 68 CKE3 -MCS0 69 70 MAA14
CKE3 6 69 70
1

MD12 5 12 MDD12 RPX8 -MCS2 69 70 MAA14 R251

-MCS1 71 72
MD43 MDD43 R252 -MCS3 22 71 72 SDRAMCLK1
6 11 71 72 73 74 SDRAMCLK1 16
MD10 MDD10 22 SDRAMCLK3 0603 73 74
7 10 73 74 75 76
MD44 MDD44 0603 SDRAMCLK3 16 75 76
8 9 Near to 75 76 77
77 78
78
MD16 MDD16

2
1 16 77 78 79 80
SO-DIMM 79 80

1
MD48 MDD48
2

2 15 79 80 81 82
81 82

1
MD17 3 14 MDD17 RP512 81 82 C282 MDD16 83 84 MDD48 R253
83 84
1

MD50 4 13 MDD50 0*8_DFS C283 MDD16 83 84 MDD48 R254 10P MDD17 85 86 MDD49 22 Near to
MD19 MDD19 RPX8 22 0603 MDD18 85 86 0603
5 12 10P MDD17 85 86 MDD49 87 88 MDD50
MD51 MDD51 0603 0603 87 88 SO-DIMM

2
6 11 MDD18 87 88 MDD50 MDD19 89 90 MDD51
MD18 MDD18 89 90
2

2
7 10 MDD19 89 90 MDD51 91 92
MD49 MDD49 91 92 VCC5

2
8 9 91 92 MDD20 93 94 MDD52
93 94

1
MD55 1 16 MDD55 MDD20 93 94 MDD52 MDD21 95 96 MDD53 C284
95 96

1
MD24 2 15 MDD24 MDD21 95 96 MDD53 C285 MDD22 97 98 MDD54 10P
MD57 MDD57 RP514 97 98 0603 R111
3 14 MDD22 97 98 MDD54 10P Near to MDD23 99
99 100
100 MDD55
MD26 MDD26 0*8_DFS 0603 10K

2
4 13 MDD23 99 100 MDD55 101 102
MD56 MDD56 RPX8 Modify by 12/15 '00 SO-DIMM 101 102 0603

2
5 12 101 102 MAA6 103 104 MAA7
MD25 MDD25 103 104
6 11 MAA6 103 104 MAA7 MAA8 105 106 MAA11
MD27 MDD27 105 106

2
7 10 MAA8 105 106 MAA11 107 108
MD59 MDD59 107 108
8 9 107 108 MAA9 109 110 MAA12
MD0 MDD0 109 110
1 16 MAA9 109 110 MAA12 MAA10 111 112 MAA13
MD1 MDD1 111 112
2 15 MAA10 111 112 MAA13 Near to 113
113 114
114 Modify by 12/15 '00
MD32 3 14 MDD32 RP504 113 114 -MDQMA2 115 116 -MDQMA6 3
MD33 4 13 MDD33 0*8_DFS -MDQMA2 115 116 -MDQMA6
SO-DIMM -MDQMA3 117
115 116
118 -MDQMA7 Q13 R1 2
MD35 MDD35 117 118 DTC144TKA1 DRAMENA 11
5 12 RPX8 -MDQMA3 117 118 -MDQMA7 119 120
MD3 MDD3 119 120
6 11 119 120 MDD24 121 122 MDD56
MD2 MDD2 121 122
V00-V0A 7 10 MDD24 121 122 MDD56 MDD25 123
123 124
124 MDD57
(Del MD0-63 RPs) MD34 8 9 MDD34 MDD25 123 124 MDD57 MDD26 125 126 MDD58
MD11 MDD11 125 126
1 16 MDD26 125 126 MDD58 MDD27 127 128 MDD59
MD42 MDD42 127 128
2 15 MDD27 127 128 MDD59 129 130
MD13 MDD13 RP507 129 130
3 14 129 130 MDD28 131 132 MDD60
MD15 MDD15 0*8_DFS 131 132
4 13 MDD28 131 132 MDD60 MDD29 133 134 MDD61
MD46 MDD46 RPX8 133 134
5 12 MDD29 133 134 MDD61 MDD30 135 136 MDD62
MD14 MDD14 135 136
6 11 MDD30 135 136 MDD62 MDD31 137 138 MDD63
MD45 MDD45 137 138
7 10 MDD31 137 138 MDD63 139 140 V00-V0A

G
MD47 MDD47 SMBDATA0 139 140 SMBCLK
8 9 139 140 141
141 142
142
SMBCLK 11,16 (R108,R109 Del)
MD20 1 16 MDD20 SMBDATA1 141 142 SMBCLK 143 144
MD52 MDD52 SMBCLK 11,16 143 144
2 15 143 144
MD21 3 14 MDD21 RP513 DIMM144P/0.8MM/H4 SMBDATA0 S D D S SMBDATA1
MD22 MDD22 0*8_DFS

S
D
4 13 AMP 1123693-1

D
S
DIMM144P/0.8MM
MD58 5 12 MDD58 RPX8 Q12
MD54 6 11 MDD54 FDV301N
MD53 7 10 MDD53 Q11 SOT23_FET
MD23 8 9 MDD23 FDV302P
MD28 1 16 MDD28
MDD29
BANK2/3 BANK0/1 SOT23_FET
MD29 2 15
MD60 3 14 MDD60 RP515 NO SUPPORT ECC FUNCTION NO SUPPORT ECC FUNCTION
MD31 4 13 MDD31 0*8_DFS
1 MD63 5 12 MDD63 RPX8 1

MD61 6 11 MDD61
MD30 7 10 MDD30
MD62 8 9 MDD62
-DQMA2 1 16 -MDQMA2
MD[0..63] -DQMA6 2 15 -MDQMA6
6 MD[0..63] -MDQMA3 SMBDATA 11,16
-DQMA3 3 14 RP511
-DQMA7 4 13 -MDQMA7 0*8
-DQMA4 5 12 -MDQMA4 RPX8
-DQMA5 6 11 -MDQMA5
-DQMA0 7 10 -MDQMA0
-DQMA1 8 9 -MDQMA1

-DQMA[0..7]
6 -DQMA[0..7]

Layout Note:

NB DIMM1 DIMM2
2.0"<L1<4.0" 0.4"<L2<0.5"
Title
System Memory

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 8 of 22
A B
 5 4 3 2 1
LCD & CRT INTERFACE
TV_Encoder
DVDD3 VCC3

V00-V0A L527
(Del DSTN CKT) +TV_VDD
1 2
120Z/100M
2012
DVDD

1
C646 C649 C650
0.1U 0.1U 10U_NA
LED INDICATOR 0603 0603 1206
50V 50V 10V

2
31
25

30

16
U511

5
SPD1 26 38

AVDD
VDD

DVDD0
DVDD1
DVDD2
6 SPD1 SD DVDD3
SPCLK1 27
6 SPCLK1 SC TV_COMP
D6 D7 D8 D9 D10 D11
D CVBS
20 TV_COMP 22
D

1
C61 C83 TVD8 7 TP586
6 TVD8 D[8] TV_LUMA
CDROM HDD NUM CAP SCROLL EMIAL 22P 22P TVD9 9 22
6 TVD9 D[9] Y TV_LUMA 22
0603 0603
TVCLKR TV_CRMA

2
6 TVCLKR 39 21 TV_CRMA 22
XCLK C

1
TV_HSYNC 40 17 CSYNC
6 TV_HSYNC HS CSYNC CSYNC 22
VCC5 TV_VSYNC 41 35
6 TV_VSYNC VS BCO TVCLK
37 R667 1 0 2 0603
P-OUT TVCLK 6
TVD7 6
6 TVD7 D[7]
TVD6 4 33
6 TVD6 D[6] XTALO

1
TVD5 3 32
6 TVD5 D[5] XTALI
BlueTooth R586 R211 R212 R213 R96 TVD4 2
470 470 470 470 470 6 TVD4 D[4]
TVD3 1 R668
13 -SCROLL 0603 0603 0603 0603 0603 6 TVD3 D[3]
TVD2 44 10 TVD10 1 2
13 -NUM 6 TVD2 D[2] D[10] TVD10 6
TVD1 43 11 TVD11 1M/NA 0603
13 -CAP 6 TVD1 D[1] D[11] TVD11 6
TVD0

2
13 -MAIL 6 TVD0 42 12
D10 D[0] D[12] DVDD3
6,10,12,14,18,19 -PCIRST 1 2 29 13
ADDR D[13]
K A PG1102W 14 ADDR
D8 R106 D[14] CONF_XLT
15 X502

DGND0
DGND1
DGND2
D[15]

DGND
AGND
GND0
GND1
K A PG1102W 0 1 2
D9 0603 24
IRSET

1
K A PG1102W C655 14.318MHZ/NA C656
CH7005C R670 10P/NA 10P/NA

34
19
23

18
36

28
D11 360 0603 0603

8
R669 PQFP44A_0.8MM
0603

2
EMAIL LED K
GREEN COLOR
A
12-215UBGC/TR8 1%
1 2
VCC3 Pin24 need wide trace.

2
D15 V00-V0A
VDD5S (From green led only) 4.7K/NA
U19 K A 0603 TV_GND
LED_DATA 1 3 -SCROLL 12-215SURC/TR8
17 LED_DATA A QA R671
74VHC164

2 4 -NUM BLUE-TOOTH LED This pin should TV_GND

B QB -CAP RED COLOR
5 16 14M_TV 1 2
QC
6 -MAIL1 be high in
QD -BTOOTH 13,17
QE
10 -AC_POWER
-AC_POWER 22 normal 0 0603
LED_CLK 8 11 -BATT_POWER Close to CH7005C Pin
17 LED_CLK CLK QF
12 -BATT_R
-BATT_LED 22 operates.
QG -BATT_R 22
-H8_RESET 9 13 -BATT_G
17 -H8_RESET CLR QH -BATT_G 22
7 14 L529 L530
GND VCC
1 2 1 2
+TV_VDD DVDD
1

74VHC164 C262 VCC5 120Z/100M VCC3 120Z/100M

1
C TSSOP14 0.1U
0603
50V
2012

L531
C657
0.1U
0603
C658
10U_NA
1206
2012 C659
0.1U
0603
C660
10U_NA
1206
C
2

50V 10V 50V 10V

2
3 3 1 2
Q18 R1 2 -SUSA -SUSA 4,6,11,16,17
Q19 R1 2 SQWO SQWO 11
DTC144TKA
1 DTC144TKA
1 JP_BEAD_DFS

TV_GND
DVDD3 DVDD3

1
LCD CONNECTOR R677 R678 TV_COMP
10K 10K
0603 0603 TV_LUMA

Q500NDS9410 SO8 TV_CRMA

2
VCC3 ADDR CONF_XLT
J8 8

1
LCDVCC 1 2 LCDVCC L502 1 2 120Z/100M 2012 3 7
1 2 R679 R680 R681 R682 R683
3 4 2 6
3 4 10K/NA 10K/NA 75 75 75
5
5 6
6 Close to LCD Connector 1 5

D
TX2CLK+ TXCLK+ 0603 0603 0603 0603 0603

S
6 TX2CLK+ 7
7 8
8 TXCLK+ 6 CLOSE TO NDS 9410

G
TX2CLK- 9 10 TXCLK- C501 C505 C503 C506 1% 1% 1%
6 TX2CLK- 9 10 TXCLK- 6

1
1000P

2
11
11 12
12 1000P 0.1U 10U C509 C507 V0.1-V0.2
TX2OUT0+ TX2OUT1+ 0603 0603 0603 1206 +12V (NA)

4
6 TX2OUT0+ 13 14 TX2OUT1+ 6 0.1U 10U_NA
TX2OUT0- 13 14 TX2OUT1- 50V 10V 0603 1206
2

2
6 TX2OUT0- 15 16 TX2OUT1- 6
15 16 50V 10V

2
17 18 1 2
TX2OUT2+ 17 18 TXOUT0+ TV_GND
6 TX2OUT2+ 19 20 TXOUT0+ 6
TX2OUT2- 19 20 TXOUT0- R506 470K
6 TX2OUT2- 21 22 TXOUT0- 6
21 22 Q501 0603
23 24 3
TXOUT2+ 23 24 TXOUT1+ R1
6 TXOUT2+ 25
25 26
26 TXOUT1+ 6 Close to LCD 2
TXOUT2- 27 28 TXOUT1- 1
6 TXOUT2- 27 28 TXOUT1- 6 Connector DTC144TKA
29 30
29 30
DF13-30DP-1.25V
ENPVDD
ENPVDD 6
V00-V0A
(From 40 pin)
VCC5

B 2

1
D16
3
BAV99_NA
B
2 D17 BAV99_NA
3
Layout Note: 1
2 D12 BAV99_NA
S/W/W/S=12/6/6/12 mils 3
as short as possible 1
D512 BAV99_NA
2 V00-V0A
四四四四平平四四平長 3 (Add BAV99 for ESD)
1
2 D13 BAV99_NA
3
VCC3 VCC5 1
VCC5 2 D514 BAV99_NA
3
1
2 D14 BAV99_NA

A
1

DDC2B 1Amp 3
R87 R83 EC11FS2 1
V00-V0A 4.7K 4.7K (40mil-60mil) D508
From 2.2K 0603 0603 V00-V0A 16
Add Diode for DDC2B
K

6 RED RED 2 L2 120Z/100M 1608 GND_CRT15

2

1 1

External VGA Connector

DDC2B 9
6 GREEN GREEN 1 2 L3 120Z/100M 1608 2
W/S=16/12/12/12/16 mils 6 BLUE BLUE
10
1 2 L4 120Z/100M 1608 3
11
4
12 J4
5 VGA
G 4 5 13 SUYIN
Q6 3 6 6 7535S-15G2T-05
6 SDA SDA S D 2 7 14
S
D

1 8 7
Q503
G 15
2N7002 FA500 8
6 HSYNC HSYNC S D 120OHM/100MHZ
S
D

Close to VGA Connector 17

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

G Q502 C637
A A
4
3
2
1

2N7002 RP62 CP500 CP502 CP501 10U_NA

6 VSYNC VSYNC S D 75*4_NA 22P*4 RP1 22P*4 22P*4 1206
1206 10V
S
D

1206 1206 1206 JL500

2

75*4
G Q5 1206 1 2
2N7002
6 SCL SCL S D SHORT-SMT3
S
D

JL501
5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8
5
6
7
8

1 2
2N7002
SHORT-SMT3

GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15

GND_CRT15
Title
Modify by 12/15 '00 LCD & CRT Interface

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 9 of 22

5 4 3 2 1
 A B

VCC3

1
C196 C192 C191 C195 C203 C223 C190 GPI LIST
0.1U
0603
0.1U
0603
0.1U
0603
0.1U
0603
1U
0603
1U
0603
1U
0603
GPO LIST
50V 50V 50V 50V

2
GPI0 Pull-High Only GPO0 SQWO
GPI1 Pull-High Only GPO1/SUSA#/strap SUSA#/strap
GPI2/EXTSMI# -EXTSMI GPO2/SUSB# SUSB#
GPI3/RING# -WAKE_UP GPO3/SUSST# SUSST#

M15
G10
G12

K15

P15
F12
F13
F15
J15
M6
G6

G8
G9
VCC3

H6

N6
GPI4/LID -SCI GPO4/SUSCLK TP V00-V0A

F7

F9
L6
J6
U12A L40
(From Pull-High)
AD0 C11 E15 1 2 GPI5/BATLOW# Pull-High Only GPO5/CPUSTP# CPUSTP#

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
AD1 AD0 USBVDD 120Z/100M
B11
AD1

1
AD2 D10 C198 1608 GPI6/PME# -PME GPO6/PCISTP# PCISTP#
AD3 AD2
E10 0.1U
AD4 AD3 0603 L41
B10 GPI7/SMBALRT# Pull-High Only GPO7/SLP# SLP#
AD5 AD4 50V

2
A10 F14 1 2
AD6 AD5 USBGND
C10
AD6
GPI8/INTRUDER# TP GPO8/HGNT1# Pull-High Only
AD7 D9 C15 USBCLK JP_BEAD_DFS
AD7 USBCLK USBCLK 16
AD8 E9 GPI9/APICCLK TP GPO9/HGNT2# -GATE1394
AD9 AD8 USBP0+
A9 B18 USBP0+ 15
AD10 AD9 USBP0+ USBP0-
B9
AD10 USBP0-
A18 USBP0- 15 GPI10/hREQ1# Pull-High Only GPO10/LGNT1# DRAMENA
AD11 F8 B19 USBP1+
AD11 USBP1+ USBP1- USBP1+ 15
AD12 C9 A19 GPI11/hREQ2# AGP_BUSY GPO11/LGNT2# TP
AD12 USBP1- USBP1- 15
AD13 E8
AD14 AD13 USBP2+
D8 B20 USBP2+ 15 V00-V0A GPI12/LREQ1# Pull-High Only GPO12 SPK_OFF
AD15 AD14 USBP2+ USBP2-
B8
AD15 USBP2-
A20
USBP3+ USBP2- 15 (From RP pull-low)
AD16 A6 C17 GPI13/LREQ2# Pull-High Only GPO13 -RS232_OFF
AD17 AD16 USBP3+ USBP3-
E6 B17
AD17 USBP3-

1
2 AD18 B6 GPI14/WSC# TP GPO14/IRTX IRTX 2

AD19 AD18 -USBOC0 R78 R79

C6 A17 -USBOC0 15
AD20 AD19 OC0 -USBOC1 10K 10K
D5
AD20 OC1
D16 -USBOC1 15 GPI15/LDRQ#/ACSDIN3 Pull-Low Only GPO15/IRRX IRRX
AD21 A5 0603 0603 V00-V0A
AD22 AD21
E5
AD22 (From RP) GPI16/CPUMISS Pull-High Only GPO16/PCS0# Pull-Low Only
AD23 P_LPD0

2
B5 D11 P_LPD0 22
AD24 AD23 PRD0 P_LPD1
A4 C12 P_LPD1 22
GPI17/THRM SB_THRM GPO17/MCCS# MCCS#
AD25 AD24 PRD1 P_LPD2
B4 A12 P_LPD2 22
AD26 AD25 PRD2 P_LPD3
A3
AD26 PRD3
E12 P_LPD3 22 GPIO18/FAN2/SLPBTN# Pull-High Only GPIO18/FAN2/SLPBTN#
AD27 C4 C13 P_LPD4
AD27 PRD4 P_LPD4 22
AD28 B3 B13 P_LPD5 GPIO19/ACSDIN2/PCS1# Pull-Low Only GPIO19/ACSDIN2/PCS1#
AD28 PRD5 P_LPD5 22
AD29 D4 A13 P_LPD6 V00-V0A
AD29 PRD6 P_LPD6 22
AD30 A1 C14 P_LPD7 GPIO20/USBOC2# GPIO20/USBOC2# -USBOC2 (To -USBOC2)
AD30 PRD7 P_LPD7 22
6,14,19 AD[0..31] AD[0..31] AD31 A2
AD31 -P_ACK
ACK
B14 -P_ACK 22 GPIO21USBOC3# GPIO21USBOC3# Pull-Low Only
-CBE0 F10 A14 P_BUSY
-CBE1 C_BE0 BUSY P_BUSY 22
A8 D13 P_PE GPIO22/IOR# -IOR GPIO22/IOR#
-CBE2 C_BE1 PE P_PE 22
D6 E13 P_SLCT
-CBE3 C_BE2 SLCT P_SLCT 22
6,14,19 -CBE[0..3] -CBE[0..3] C5 F11 -P_ERR GPIO23/IOW# -IOW GPIO23/IOW#
C_BE3 ERROR -P_ERR 22
B12 -P_INIT
-FRAME PINIT -P_INIT 22
F6 E11 -P_AFD GPIO24/GPIOA TP V00-V0A (From Pull-High) GPIO24/GPIOA
6,14,19 -FRAME FRAME AUTOFD -P_AFD 22
-DEVSEL A7 D12 -P_SLIN
6,14,19 -DEVSEL DEVSEL SLCTIN -P_SLIN 22
-IRDY C7 A11 -P_STB GPIO25/GPIOC Pull-High Only GPIO25/GPIOC
6,14,19 -IRDY -TRDY IRDY STROBE -P_STB 22
6,14,19 -TRDY B7
-STOP TRDY
6,14,19 -STOP D7
STOP
GPIO26/SMBDT2 Pull-High Only GPIO26/SMBDT2
-SERR E7 B15 COM1TXD
6,14,19 -SERR SERR TXD COM1TXD 22
PAR C8 A16 -COM1DTR GPIO27/SMCKT2 Pull-High Only V00-V0A GPIO27/SMCKT2
6,14,19 PAR PAR DTR -COM1DTR 22
A15 -COM1RTS Exchange GPIO26
RTS -COM1RTS 22
-PCIREQ D2 B16 -COM1CTS GPI28 GPO28/APICD0 -1394WR
6 -PCIREQ
-PCIGNT D1
REQL CTS
D14 -COM1DSR
-COM1CTS 22 and GPIO29
6 -PCIGNT GNTL DSR -COM1DSR 22
D15 -COM1DCD GPI29 -MPCIACT GPO29/APICD1
DCD -COM1DCD 22
-INTA B2 C16 -COM1RI
14 -INTA PINTA RI -COM1RI 22
-INTB B1 E14 COM1RXD GPIO30/GPI0D Pull-High Only GPIO30/GPI0D
6 -INTB PINTB RXD COM1RXD 22
-INTC C3
19 -INTC PINTC
-INTD C2 GPIO31/GPI0E GPIO31/GPI0E ENBTPWR V00-V0A
14,19 -INTD PINTD
L17 1 TP548 (From TP)
-PCIRST DRVDEN0 TP551
6,9,12,14,18,19 -PCIRST E4 K17 1
SBPCLK PCIRST DRVDEN1 TP61
16 SBPCLK M17 L20 1
-PCLKRUN PCICLK INDEX TP62
6,11,14,19 -PCLKRUN R5 K18 1
CLKRUN MTR0 TP63
K19 1
DS1 TP553 VCC5 VCC3 VCC5
J17 1
A20GATE DS0 TP554
17 A20GATE M4 J16 1
-RCIN KBCK/KA20G MTR1 TP68
11,17 -RCIN N1 K20 1
IRQ1 KBDT/KBRC DIR TP70
17 IRQ1 N2 J18 1
IRQ12 MSCK/IRQ1 STEP TP71
17 IRQ12 N4 J19 1
MSDT/IRQ12 WDATA

1
J20 1 TP72 EC28 EC500 EC27 EC14 EC1 EC5 EC9 EC21 EC514 EC32 EC506 EC509
WGATE TP555
H16 1 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U
IRRX TRAK00 TP559 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
22 IRRX U8 H17 1
IRTX IRRX WRTPRT TP75

2
22 IRTX R8 H20 1
FIRSEL IRTX RDATA TP76
T8 H19 1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19

22 FIRSEL IRRX2/GPI HDSEL

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

H18 1 TP77
DSKCHG
P14

K10
K11
K12
K13

P10

VCC5 VCC5
L10
L11
L12
L13
J10
J11
J12
J13

VT8231
K8
K9

L8
L9
J8
J9

BGA352_24

1
EC26 EC55 EC507 EC503 EC508 EC11 EC2 EC29 EC54 EC513 EC3 EC31 EC511 EC505 EC512
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

2
VCC5
VCC3 VCC5
VCC5
RP39
RP50 -INTA 1 8

1
IRQ12 1 8 -INTB 2 7 EC30 EC20 EC22 EC504 EC502
1

1
IRQ1 2 7 -INTC 3 6 EC38 EC39 EC40 EC41 EC564 EC43 EC44 EC45 EC46 EC47 0.01U 0.01U 0.01U 0.01U 0.01U
3 6 -INTD 4 5 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0603 0603 0603 0603 0603
4.7K*4 1206 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

2
4 5
4.7K*4 1206
2

2
RP32
-IRDY 1 10
-TRDY 2 9 -PLOCK VCC3 VCC5
PAR -PLOCK 6
-DEVSEL 3 8
1 -STOP 4 7 -SERR 1

5 6 -FRAME
1

1
4.7K*8 1206 EC18 EC13 EC23 EC25 EC4 EC12 EC10 EC7 EC17 EC6 EC33 EC526 EC527 EC34 EC35
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
2

2
17 -RI -RI

VCC3
3 VCC5
2 R1 Q3
VCC3
1 DTC144TKA
1

1
EC48 EC49 EC556 EC50 EC51 EC52 EC560 EC561 EC53 EC563

1
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U EC36 EC37 EC56 EC542 EC543
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0.01U 0.01U 0.01U 0.01U 0.01U
D2 BAS32L 0603 0603 0603 0603 0603
2

2
A K
-COM1RI 22

2
VCC3
1

VCC3
R59
100K
0603
C87
1

1
D1 BAS32L -CARD_RI
2

A K 1 2 -CARD_RI 14 EC15 EC24 EC16 EC19 EC8

0.01U 0.01U 0.01U 0.01U 0.01U
0603 0603 0603 0603 0603
0.1U
2

2
50V
0603
Title
South Bridge VT8231 (PCI,USB,GPIO)
Reserve for EMI
Size Document Rev
411669000014 0A
Number
Date: Friday, May 04, 2001 Sheet 10 of 22
A B
 A B

VCC3

V00-V0A
Layout Note: (NA)
AC97 Signals route 6/12 mil

R15
R14

R13

R10
P13

P12
P11

R9

R7
P9

P8
U12B JS506 SHORT-SMT3
ACBITCLK J3 W5 0_NA 0603 1 2 -A20M

VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
13,18,19 ACBITCLK BITCLK A20M -A20M 4
ACSDIN H1 U4 R153 1 2
13 ACSDIN SDIN0 CPURST -C_FERR -CPURST 4,5,6
MSDIN H2 U5 JS507 SHORT-SMT3
18,19 MSDIN SDIN1 FERR -C_FERR 4
ACSYNC R136 1 0603 2 22 G1 T6 1 2 -IGNNE
13,18,19 ACSYNC SYNC IGNNE -IGNNE 4
ACSDOUT R135 1 0603 2 22 H3 V5 -INIT
13,18,19 ACSDOUT SDOUT INIT -INIT 4
-ACRST R214 1 0603 2 22 G2 R6 JS508 SHORT-SMT3
U12C XD[0..7] 15,17 13,18,19 -ACRST ACRST INTR
SA[0..17] 1 8 J2 T5 1 2 INTR
12,15,17 SA[0..17] SA0 XD0 JBY NMI INTR 4
Y18 R12 2 7 K5 U6 -SLP
SA1 SA0/SDD0 SD0 XD1 JBX SLP -SLP 4
W17 V12 3 6 K4 Y5 -SMI JS509 SHORT-SMT3
SA2 SA1/SDD1 SD1 XD2 JAY SMI -C_STPCLK -SMI 4
V16 W12 4 5 J1 V6 1 2 NMI
SA3 SA2/SDD2 SD2 XD3 JAX STPCLK -C_STPCLK 4 NMI 4
Y16 Y12 RP53 4.7K*4 1206 SPK_OFF H5
SA4 SA3/SDD3 SD3 XD4 13 SPK_OFF GPI28 JAB2
W15 U12 G3 -RSMRST 17
SA5 SA4/SDD4 SD4 XD5 -RS232_OFF JAB1 -EXTSMI
V14 U11 22 -RS232_OFF H4 W1 -EXTSMI 17
SA6 SA5/SDD5 SD5 XD6 GPI29 JBB2 EXTSMI/GPI2 PWROK
U16 R11 F1 E2 PWROK 4,6,17
SA7 SA6/SDD6 SD6 XD7 VCC3 R218 1 0603 2 4.7K JBB1 PWRGD R154 10K_NA 0603
SA8
U15
SA7/SDD7 SD7
T11
GPI10
J4
MSO/SPDIF PWRBTN
U2 -MVP4BT 17 V00-V0A
T15 Y11 V00-V0A R219 1 0603 2 4.7K G4 F2 -RSMRST 1 2 (From VCC3)
SA8/SDD8 SD8/HREQ1/GPI10 MSI/I2S RSMRST VDD3

1
VCC3 SA9 W14 W11 GPO8 PD_D[0..15] U3 -WAKE_UP C202
SA10 SA9/SDD9 SD9/HGNT1/GPO8 GPI11 12 PD_D[0..15] PD_D0 RING/GPI3 -WAKE_UP 17
Y15 V11 (R250 Add) T16 R4 0603 1U_NA
SA11 SA10/SDD10 SD10/HREQ2/GPI11 GPO9 AGPBSY 6 PD_D1 PDD0 GPO0 SQWO 9
V15 T10 R250 1 2 0 R16 V3 GPI1 1 R123 2 0_NA 0603
SA11/SDD11 SD11/HGNT2/GPO9 -GATE1394 14 PDD1 GPI1
1

SA12 GPI12 0603 PD_D2 -PME1 1 R124 2 0 0603 VDD3

2
W16 U10 U20 U1 -PME 14,17,19
R188 SA13 SA12/SDD12 SD12/LREQ1/GPI12 PD_D3 PDD2 PME/GPI6 -SCI VCC5
2
Y17 Y10 DRAMENA 8 T19 V2 -SCI 17
2

10K SA14 SA13/SDD13 SD13/LGNT1/GPO10 GPI13 PD_D4 PDD3 LID/GPI4 GPI5

V17 W10 P16 T3
0603 SA15 SA14/SDD14 SD14/LREQ2/GPI13 PD_D5 PDD4 BATLOW/GPI5 -SUSST1 D19
W18 V10 1 N17 N5 K A BAS32L -SUSST 6
SA15/SDD15 SD15/LGNT2/GPO11 TP587 PDD5 SUSST1/GPO3

1
PD_D6 R20 W2 SUSCLK 1
SA16 PD_D7 PDD6 SUSCLK/GPO4 -SUSA1 D20 TP111
A BAS32L R40 R44
2

Y14 R18 P1 K -SUSA 4,6,9,16,17

SA17 SA16 VCC3 PD_D8 PDD7 SUSA/GPO1 -SUSB 22K 22K
T13 P18 P2 1
SA18 SA17 -LPC_FRAME PD_D9 PDD8 SUSB/GPO2 -SUSC TP39 0603 0603
15 SA18 U13 W8 R19 N3 -SUSC 17,22 V0A-V0B GQ17
SA19 SA18 LFRAME -LPC_LDAQ R220 1 10K PD_D10 PDD9 SUSC GPI7
1 V13 Y8 2 0603 N16 T2 (Add D19,D20) 2N7002
TP546 GPIO20 SA19 LREQ/SDIN3/GPI15 -LPC_LAD0 PD_D11 PDD10 SMBALT/GPI7 SMCK
V00-V0A 15

2
-USBOC2 W13 V8 P17 R3 D S SMBCLK 8,16
GPIO21 LA20/GPO20 LAD0 -LPC_LAD1 PD_D12 PDD11 SMBCLK SMDA
(New Add) Y13 Y7 T20 T1

D
S
LA21/GPO21 LAD1 -LPC_LAD2 PD_D13 PDD12 SMBDATA
W7 T18 G
-MEMR LAD2 -LPC_LAD3 PD_D14 PDD13 GPI0 Q20
15 -MEMR W9 V7 R17 F4
-MEMW MEMR LAD3 PD_D15 PDD14 GPI0 GPIO24 1
15 -MEMW Y9 T17 Y2 D S 2N7002 SMBDATA 8,16
-IOR MEMW PDD15 GPIOA/GPI24/GPO24 GPIO25 TP112
U7 J5

D
S
17 -IOR -IOW IOR/OC2/GPO22 GPIOC/GPI25/GPO25
T7 -PCS1 L18 Y1 GPIO30
17 -IOW IOW/OC3/GPO23 12 -PCS1 PDCS1 GPIOD/GPI30/GPO30
-PCS3 L19 W3 V00-V0A
IRQ14 12 -PCS3 PDCS3 GPIOE/GPI31/GPO31 ENBTPWR 15
T14 C1 -REQ4 Y6 -PCS0 (Add 2N7002,22K)
12 IRQ14 IRQ15 IRQ14 REQH -GNT4 -REQ4 6 PCS0/GPO16 R240
U14 D3 PDREQ P19 W6 -MCCS
12 IRQ15 SERIRQ IRQ15 GNTH -GNT4 6 12 PDREQ PDDREQ MCCS/GPO17 -MCCS 17
V9 -PDACK N20 G5 GPIO19 1 2
14 SERIRQ SERIRQ LAN_CRS 12 -PDACK PDDACK PCS1/SDIN2/GPI19/GPO19 -CPUSTP
G16 -PDIOR N18 P4
CRS LAN_COL LAN_CRS 18 12 -PDIOR PDIOR CPUSTP/GPO5 -PCISTP -CPUSTP 16
G17 -PDIOW P20 T4 4.7K
COL LAN_COL 18 12 -PDIOW PDIOW PCISTP/GPO6 -PCISTP 16
OSC14M T12 PIORDY N19 0603
16 OSC14M OSC LAN_MTXE 12 PIORDY PHDRDY
F19 RP54 1 22*4
8 1206 T9
MTXE LAN_MTXD0 LAN_MTXE 18 ROMCS/KBCS -ROMCS 15,17
RTC_VCC F20 2 7 PDA0 M19 U9 SBSPKR
MTXD0 LAN_MTXD1 LAN_MTXD0 18 12 PDA0 PDA0 SPEAK SBSPKR 13
E1 G18 3 6 PDA1 M18
VBAT MTXD1 LAN_MTXD2 LAN_MTXD1 18 12 PDA1 PDA1
G19 4 5 PDA2 M20 M1 RP55 1 10K*4 8 1206
MTXD2 LAN_MTXD2 18 12 PDA2 PDA2 UIC1
1

C269 C268 G20 R221 1 22 2 0603 LAN_MTXD3 M3 2 7

MTXD3 LAN_MTXD3 18 UIC2
0.1U 1U F17 LAN_MTXC M2 3 6
MTXC LAN_MTXC 18 UIC3
V00-V0A (From VCC3) 0603 0603 -SCS1 U18 L4 4 5
50V LAN_MRXER 12 -SCS1 SDCS1 UIC4
VCC3 -SCS3 RP28 10K*4 8 1206
2

F18 LAN_MRXER 18 12 -SCS3 U19 L1 1

VDD3 MRXER LAN_MRXC SDCS3 UIC5
C19 LAN_MRXC 18 2 7
GPIO26 MRXC LAN_MRXDV SDREQ
R2 E20 LAN_MRXDV 18 12 SDREQ U17 K2 3 6
SMBDT2/GPI26/GPO26 MRXDV SDDREQ FAN1

1
GPIO27 R1 E19 LAN_MRXD0 -SDACK W20 K3 4 5
SMBCK2/GPI27/GPO27 MRXD0 LAN_MRXD1 LAN_MRXD0 18 12 -SDACK SDDACK FAN2/GPI18/GPO18
-SB_THRM P3 E18 R222 V00-V0A -SDIOR W19
17 -SB_THRM GPI16 AOLGPI/GPI17 MRXD1 LAN_MRXD2 LAN_MRXD1 18 1K 12 -SDIOR SDIOR
V1 D20 (From 15K) -SDIOW Y19 L2 RP40 1 10K*4 8 1206
CPUMISS/GPI16 MRXD2 LAN_MRXD3 LAN_MRXD2 18 0603 12 -SDIOW SDIOW DTD+
1 R73 2 10K 0603 F3 D19 SIORDY Y20 2 7 V0A-V0B
INTRUDER/GPI8 MRXD3 LAN_MRXD3 18 12 SIORDY SHDRDY
VFER
K1 3 6 (Add RP40)
R223 1 22 2 0603 LAN_DCLK SDA0

2
C20 LAN_DCLK 18 12 SDA0 V19 4 5
MDC R224 1 22 2 0603 LAN_DATAIO SDA1 SDA0
1 V4 D18 LAN_DATAIO 18 12 SDA1 V18 L3
TP101 APICREQ/WSC/GPI14 MDIO SEECS SDA2 SDA1 DTD- L53
14 -1394WR W4 C18 12 SDA2 V20
-MPCIACT APICCS/PICD0/GPI28/GPO28 SEECS SEEDO SDA2
19 -MPCIACT Y4 D17 M5 1 2 VCC3
GPI9 APICACK/PICD1/GPI29/GPO29 SEEDO SEEDI VDD78 120Z/100M
TP103 1 Y3 E17 VCC3_LAN
APICCLK/GPI9 SEEDI

1
VCC3 E16 SEECLK P5 C266 C267 1608
SEECLK VCCSUS0
1

L54 0.1U 4.7U_NA

C270 P6

GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
VDD3 VCCSUS1 0603 1206 L52
1 2 L16 G15 0.1U L5
PLLVDD VDDRAM GND78

1
0603 V00-V0A 50V 16V

2
G13 C194 C224 C213 1 2
GNDRAM
1

120Z/100M 50V (From VCC3)

2

C271 0.1U 10U_NA 0.1U

M10
M11
M12
M13

G11
G14
H15

N15
2012 0.1U 0603 1206 0603

L15
F16

M8
M9

G7

P7
K6
VDDM0 50V 10V 50V VT8231
0603 JP_BEAD_DFS

2
K16 1 2 VCC3 BGA352_24
50V VDDM1
2

1 2 M16
PLLGND L55
RTCX1

RTCX2

L56 120Z/100M
120Z/100M 2012
2012
VT8231
E3

F5

BGA352_24
R241
GPIO20 1 2

10K/NA R159
0603 1 2
U6 VCC3_LAN
R242 10M_NA 0603 SEEDI SEEDO
3 4
GPIO21 DI DO
1 2 8
X3 SEECS VCC
1
CS
1

10K 4 1 SEECLK 2 5 C272

0603 SK GND
0.1U
93C468 SO8 0603
1

C208 32.768K 50V

2

C219
10P CM200 10P
0603 0603
2

VCC3 VCC3

V0A-V0B VCC5
Add R116,R109

1
VCC3
R225 R226
-SUSA1 R116 1 4.7K RP46 10K_NA 4.7K
2 0603
1
1 8 -IOR 0603 0603 1

-SUSA R109 1 4.7K 2 0603 2 7 -IOW

-MEMW R227 R228

2
3 6
-SUSST R46 1 4.7K 2 0603 V00-V0A 4 5 -MEMR 100 4.7K/NA
(From VCC3) 4.7K*4 1206 -PCLKRUN 1 2 1 2 SA17
-LPC_FRAME 6,10,14,19 -PCLKRUN
R229 1 4.7K 2 0603
VDD3 RP49 V00-V0A 0603 0603 LOW:Enable auto reboot
-CPUSTP R47 1 4.7K 2 0603 XD0 1 10 (From R225Add,R227NA) HIGH:Disable auto reboot
-RCIN 10,17 XD1 XD4
2 9
-PCISTP R48 1 4.7K 2 0603 XD2 3 8 XD5
XD3 4 7 XD6
RP56 -RCIN R50 1 10K 2 0603 5 6 XD7
-LPC_LAD0 1 8
-LPC_LAD1 2 7 -SUSC R51 1 10K 2 0603 4.7K*8 1206
-LPC_LAD2 3 6 RP52 VCC3
-LPC_LAD3 4 5 -SUSST1 R61 1 10K 2 0603 V0A-V0B SA0 1 10 -MCCS
4.7K*4 1206 SA1 SA4 R150
-PME1
Add R110 2 9
R110 1 10K 2 0603 SA2 3 8 SA5 1 2 LOW:Enable CPU Freq strapping
RP22 SA3 4 7 SA6 4.7K 0603
SPK_OFF 1 8 GPI0 1 RP23 8 -SUSA 5 6 SA7
GPIO25 GPI1 HIGH:Socket 370 R231 R232
2 7 2 7
GPI28 3 6 GPI5 3 6 LOW:Socket-7 4.7K*8 1206 SBSPKR 1 2 1 2 -MCCS
-MCCS 17
GPI29 4 5 GPI7 4 5 RP51 4.7K 0603 10K_NA 0603
4.7K*4 1206 10K*4 1206 SA8 1 10
SA9 2 9 SA12
SA10 SA13 SBSPKR: R233 SA16
3 8
SA11 4 7 SA14 1 2 SA16
5 6 SA15 H=ISA BUS 10K 0603 LOW:Disable LPC ROM
RP58 RP43
GPI10 1 10 -SB_THRM 1 10 4.7K*8 1206 L=2nd IDE
GPI11 2 9 GPO8 GPIO26 2 9 -WAKE_UP R234
GPI12 3 8 GPO9 -SCI 3 8 GPIO27 1 2 -PCS0
GPI13 4 7 AGPBSY GPI16 4 7 SQWO 100 0603 ISA DATA BUS:(-PCS0)
5 6 GPIO30 5 6 -EXTSMI
H=16 BIT
4.7K*8 1206 4.7K*8 1206 Title
L=8 BIT South Bridge VT8231 (IDE,LAN,FIR,MDC,PULL RES)

Size Document Rev

411669000014 0A
Number
Date: Friday, May 04, 2001 Sheet 11 of 22
A B
 A B

ENHANCED IDE

PD_D[0..15]
11 PD_D[0..15]
Primary EIDE Connector
For Hard-Disk
PD_D11 1 16 DD11-1 J20
PD_D3 2 15 DD3-1 R565 -BRSTDRV-1 1 2
PD_D12 DD12-1 RP36 DD7-1 1 2 DD8-1
3 14 1 2 3 4
PD_D7 DD7-1 33*8 DD6-1 3 4 DD9-1
4 13 5 6
PD_D8 DD8-1 RPX8 DD5-1 5 6 DD10-1
5 12 7 8
PD_D6 DD6-1 10K DD4-1 7 8 DD11-1
6 11 9 10
PD_D9 DD9-1 0603 DD3-1 9 10 DD12-1
7 10 11 12
PD_D5 DD5-1 DD2-1 11 12 DD13-1
8 9 13 14
PD_D15 DD15-1 DD1-1 13 14 DD14-1
1 16 15 16
PD_D2 DD2-1 DD0-1 15 16 DD15-1
2 15 17 18
PD_D13 DD13-1 RP35 17 18
3 14 19 20
VCC3 VCC5 PD_D1 DD1-1 33*8 VCC5 DREQ-1 19 20
4 13 21 22
PD_D14 DD14-1 RPX8 -DIOW-1 21 22
5 12 23 24
PD_D0 DD0-1 -DIOR-1 23 24 R576
6 11 25 26
PD_D10 DD10-1 IORDY-1 25 26
7 10 27 28 1 2
27 28

2
PD_D4 8 9 DD4-1 -DACK-1 29 30
R31 R210 INTRQ-1 29 30 470
31 32
10K_NA DA1-1 31 32 0603
33 34
0603 VCC5 470 DA0-1 33 34 DA2-1
0603 35 36
35 36

3
-CS1-1 37 38 -CS3-1 VCC5
-HDDACTP 37 38
2

1
A K 39 40
39 40

1
2 Q4 V0A-V0B VCC5 41 42
6,9,10,14,18,19 -PCIRST 41 42
DTC144WK (From DTC144TKA) R129 D7 PG1102W 43 44
10K 43 44
Close to IDE Connector
0603 MA/22PX2/ST

1
C16822-X44XX C614 C618 C611

2
13 -HDDACPT 0.1U 0.1U 4.7U
V00-V0A RP34 33*8 RPX8 0603 0603 1206
1
2 2

(From 1K) -RSTDRV -BRSTDRV-1 50V 50V 16V

2
1 16
-PDACK 2 15 -DACK-1
11 -PDACK PDA1 3 14 DA1-1
11 PDA1
1

V00-V0A PDA0 4 13 DA0-1

1111 PDA0 PIORDY IORDY-1
R57 (From 10K) 5 12
1M PIORDY PDREQ 6 11 DREQ-1
0603 11 PDREQ
V0A-V0B -PDIOW 7 10 -DIOW-1
11 -PDIOW
(From -PDIOR 8 9 -DIOR-1
11 -PDIOR
2

Modify By R0A 100K)

1
R128
5.6K
0603

2
VCC5 RTC BATTERY CONN.
R509
J505 D5 2.8V-3.6V

1
1 1 2 A K
R173 1 RTC_VCC
2
4.7K 2 100 SK12
0603 3 0603 DC2012
RP33 33*4 1206 GND1
4
INTRQ-1 GND2 VDD3

2
11 IRQ14 1 8
-PCS1 2 7 -CS1-1 DF13-2P-1.25H
11 -PCS1 -CS3-1
-PCS3 3 6
11 -PCS3

1
PDA2 4 5 DA2-1 V00-V0A V00-V0A
11 PDA2
From1.25V R67 (ALL)
0
0603
R148

2
D4
1 2 A K
VDD5

2
10K/NA SK12

1
0603 DC2012 C20
10U
R149 1206
33K/NA 10V

2
0603

1
SA[0..15]
11,15,17 SA[0..15]

SA0 1 16 DD0-2
SA1 2 15 DD1-2
SA2 3 14 DD2-2 RP48 Secondary EIDE Connector
SA3 4 13 DD3-2 33*8 For CD-ROM
Layout Note: SA4
SA5
SA6
5
6
7
12
11
10
DD4-2
DD5-2
DD6-2
RPX8 W/S=16/12/12/16 mils
CDROM_LEFT 1
J13
2 CDROM_RIGHT
W=12 mils
All RP on this page must near SB(VT82C686) SA7 8 9 DD7-2
13 CDROM_LEFT
13 CDROM_COMM
CDROM_COMM 3
1
3
2
4
4
CDROM_RIGHT 13
SA8 1 16 DD8-2 -BRSTDRV-2 5 6 DD8-2
SA9 DD9-2 DD7-2 5 6 DD9-2
2 15 7 8
SA10 DD10-2 RP47 DD6-2 7 8 DD10-2
3 14 9 10
9 10

1
SA11 4 13 DD11-2 33*8 Don't Stuff DD5-2 11 12 DD11-2
L1<1" SA12 5 12 DD12-2 RPX8 R699 DD4-2 13
11
13
12
14
14 DD12-2
SA13 6 11 DD13-2 10K_NA DD3-2 15 16 DD13-2
RP HDD SA14 7 10 DD14-2 0603 DD2-2 17
15
17
16
18
18 DD14-2
SA15 8 9 DD15-2 DD1-2 19 20 DD15-2
DD0-2 19 20 DREQ-2

2
21 22
SB 23
21
23
22
24
24 -DIOR-2
-DIOW-2 25 26
IORDY-2 25 26 -DACK-2
RP CDROM INTRQ-2
27
29
27 28
28
30
VCC5 DA1-2 29 30
31 32
DA0-2 31 32 DA2-2
33 34
R209 -CS1-2 33 34 -CS3-2 VCC5
35 36
35 36
1

1 2 A K -CDACTP 37 38
R132 VCC5 37 38
39 40
10K D6 39 40
PG1102W 41
41 42
42 Close to IDE Connector
1 0603 470 VCC5 43 44 1
43 44

1
0603 R698 45 46
45 46 C667 C666 C668
RP37 33*8 RPX8
2

1 2 47 48 0.1U 0.1U 4.7U

-RSTDRV -BRSTDRV-2 47 48 0603 0603 1206
1 16 49 50
SDA0 DA0-2 470_NA 49 50 50V 50V 16V

2
11 SDA0 2 15 13 -CDACTP
SIORDY 3 14 IORDY-2 0603
11 SIORDY -DACK-2
-SDACK 4 13 V00-V0A
11 -SDACK
SDA1 5 12 DA1-2 (NA) GND3
11 SDA1 -SDIOW GND3
6 11 -DIOW-2 GND4
11 -SDIOW GND4
-SDIOR 7 10 -DIOR-2
11 -SDIOR
SDREQ 8 9 DREQ-2 FM/25PX2-R/A
11 SDREQ
MTG13 C12436-X50XX

1
1

Modify by 12/15 '00

R130
5.6K ID2.2/OD3.8 V00-V0A
0603 (From C12436-50)
V00-V0A
2

(New add)

VCC5
1

R181
4.7K
0603
RP38 33*4 1206
INTRQ-2
2

11 IRQ15 1 8
-SCS1 2 7 -CS1-2
11 -SCS1
-SCS3 3 6 -CS3-2 Title
11 -SCS3
SDA2 4 5 DA2-2 EIDE & Floppy
11 SDA2
Size Document Rev
C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 12 of 22
A B
 5
AUDIO CODE & AMPLIFIER 4 3 Don't Stuff
L42
VCC5
2
V0A-V0B
IDJ-B27-F6T
HCH
1
JS5 (Add C662,663) RA/D3.6/5P
1 2 1 2
R694 L534 600Z/100M 1
SHORT-SMT4 Don't Stuff 2 1 LINE_IN_L 1 2 21608
L.CH
120Z/100M 6.8K 3

1
VCC3 1608 R695 L535 600Z/100M
V0A-V0B C620 4
VCC5 (For LCD 15") 0.1U 2 1 LINE_IN_R 1 2 51608
0603 6.8K R.CH
50V

2
J24

1
J19 C662 C663
1 2 -LID 100P 100P R693 R696
SPKROUT+ 1 2 SPKROUT- -LID 17 L44
3 4 0603 0603 6.8K 6.8K
SPKROUT+ VR1_2 3 4 VR1_5 SPKROUT- 120Z/100M L536
5%

2
VR1_2 5 6 VR1_5
VR1_1 5 6 VR1_4 1608 AVDDAD +12V 5%
VR1_1 7 8 VR1_4 U13 1 2
LINE_OUT_5 7 8 LINE_OUT_2

2
LINE_OUT_5 9 10 LINE_OUT_2 L78L05ACU_NA
LINE_OUT_4 9 10 MIC_3

2
LINE_OUT_4 11 12 MIC_3 JO8 SOT89N
LINE_IN_L 11 12 MIC_2 120Z/100M
LINE_IN_L 13 14 MIC_2 1 2 1 3
LINE_IN_R 13 14 SPKLOUT- O I 1608
LINE_IN_R 15
15 16
16 SPKLOUT- Close to Codec Close to Codec Close to 78L05
SPKLOUT+ OPEN-SMT4
D 17 18
D

GND
SPKLOUT+ 17 18

1
19 20 C617 C605 C608 C217 C603 C619 C204
19 20
17 KI1 21
21 22
22 KO0 17 V00-V0A 10U_NA 0.1U 0.1U 0.1U 0.1U 10U_NA V00-V0A 0.1U_NA
23 24 (NA) 1206 0603 0603 0603 0603 1206 (NA) 0603 AGND AGND CAGND
9,17 -BTOOTH 23 24 -SCROLL 9 10V 50V 50V 50V 50V 10V 50V

2
9 -MAIL 25 26 -NUM 9
25 26 L514
9 -CAP 27
27 28
28 -CDACTP 12 V00-V0A
12 -HDDACPT 29
29 30
30 1 1 2 (From 4.7K)
TP113
BEAD/NA R190
FM/15PX2/1.27_NA
B06B-3100-307 -ACRST AGND AGND AGND 0805C 1 2 MODEM_SPK
11,18,19 -ACRST MODEM_SPK 18,19
SPEED V00-V0A

1
U16 (From C247,C248 0603SIZE)

25
38
1
9

1
ACSDOUT V00-V0A R687 C669 47K
11,18,19 ACSDOUT 1K 0603
23 C247 1 2 2.2U 0805 +80-20% (From 10K) 0.1U_NA

DVDD1
DVDD2

AVDD1
AVDD2
R581 LINE/IN/L 0603 0603
AGND
ACSDIN C248 1 2 2.2U 0805 +80-20% 50V

2
11 ACSDIN 1 2 24
LINE/IN/R

2
22 0603 11 21 MIC1 C245 1 2 1U 10V 0603 MIC
ACSYNC RESET# MIC1
11,18,19 ACSYNC 5
SDATA/OUT MIC2 C246 1 1U 10V 0603
R578
8
SDATA/IN MIC2
22 2 AGND
10
ACBITCLK SYNC C244 1 1U 10V 0603 R690 1 CDROM_RIGHT
11,18,19 ACBITCLK 1 2 6 20 2 2 6.8K 5%
CDROM_RIGHT 12
BIT/CLK CD/R
22 0603 18 C242 1 2 1U 10V 0603 R688 1 2 6.8K 5% CDROM_LEFT
CD/L CDROM_LEFT 12
CLOSE TO CODEC 2
XTL/IN
19 C243 1 2 1U 10V 0603 R689 1 2 0 0603 CDROM_COMM
CD/GND CDROM_COMM 12
1 R169 2 3
XTL/OUT C615 1 1U 10V 0603 VIDEO_L
16 2
VIDEO/L

2
0603 1M 12
PC_BEEP C616 1 1U 10V 0603 VIDEO_R R691 R193 R191
17 2
VIDEO/R 6.8K 6.8K 0
V00-V0A
X4 14 C241 1 2 1U 10V 0603 5% 5% 0603
AUX/L
1 2
0603 10V 1U 2 C229 C670 1 1U 10V 0603

1
1 31 15 2
24.576MHZ BPCFG AUX/R AVDDAD ZV AUDIO
1

C214 0603 10V 1U 1 2 C227 32 35 AOUT_L U506

FLT3D LINE/OUT/L

1
10P C225 AGND AGND AGND
0603 10P 0603 10V 1U 1 2 C226 33 36 AOUT_R 7 1 ZV_DATA
FLTI LINE/OUT/R VA+ SDATAI ZV_SCLK ZV_DATA 14
0603
2

8 2 ZV_SCLK 14
0603 50V AOUTL SCLK ZV_LRCLK
2 C222 C240 1 1U 10V 0603

2
1 34 13 2 5 3 ZV_LRCLK 14
1000P_NA FLTO PHONE AOUTR LRCK ZV_MCLK
6 4 ZV_MCLK 14
C602 1 1U 10V 0603 MONO_OUT AGND MCLK
37 2 MONO_OUT 18
MONO_OUT
C VCC5 40
NC1
C

4
3
2
1
C221 CS4334/NA
43
NC2

1
C621 C216 1 2 1000P 50V 0603 C211 RP519
AGND 1 2 44
NC3 ALT_LINE_OUT_L
39 SO8
1 2 0.1U_NA 50V 0603 45 0.1U/NA V00-V0A 10K*4_NA
ID0# C215 1
46 41 2 1000P 50V 0603 0603 (NA) 1206
C607 ID1# ALT_LINE_OUT_R 50V

2
47
0.1U EAPD C236 1
1 2 48 29 2 1000P 50V 0603 V00-V0A
SBSPKR 50V 0.1U_NA 50V 0603 S/PDIF_OUT AFLT1
11 SBSPKR (NA)
0603 C230 1 2 1000P 50V 0603

5
6
7
8
U507 30
C178 C234 AFLT2
1
A VCC
5 Don't Stuff
-CARDSPK 1 2 2 4 1 2 1 2 27 20mil

DVSS1
DVSS2

AVSS1
AVSS2
14 -CARDSPK B Y REFFLT
3
GND R518 0.1U
VREFOUT
28 AGND
1

2
0.1U NC7S32 470K 0603 Very Close to Codec

1
50V SC70/SOT70 0603 50V CHIP ALC2000 AD1881 CS4299 C600 R640 R641

26
42
1

1
0603 R510 ALC200 0 0

4
7
V00-V0A C235 C239 C238 1000P/NA
R580 (From 6.8K) 22K Cap pin31: 0.1U 1U X PQFP48_0.5MM 0.1U 0.1U 1U 0603 0603 0603
47K 0603 0603 0603 0603 V00-V0A

2
0603 V00-V0A Cap pin32: 0.1U 1U 0.01U V00-V0A 50V 50V (Add 0ohm)
2

1
10V
(From 2.2K) (From CS4299) pre-AMP remove by R0A
Cap pin33: 1U 0.1U X
2

AGND AGND AGND AGND AGND AGND AGND AGND

Cap p33/34 X 0.1U 1000P

CHIP ALC2000 AD1881 CS4299

Cap. pin29: 1000P 270P 1000P Internal Micro Phone Jack V00-V0A
(Add 2P CONN)
Cap. pin30: 1000P 270P 1000P J30
JO9 L43
1
1 2 1 2 2 HIROSE
ST/MA-2
OPEN-SMT4 DF13-2P-1.25V
120Z/100M
AGND 2012 AGND External Micro Phone Jack
AGND J23
R.CH
5
AVDDAD 4
R207 R206 L47 MIC_3 3
JO7 L515 MIC_2 1608
1 2 1 2 1 2 2
B 1

OPEN-SMT4
2 1 2

22K 22K
600Z/100M
1
L.CH
B

2
120Z/100M 0603 0603 RA/D3.6/5P

2
AGND 2012 AGND L533 HCH

1
C254 C261 C253 V0A-V0B 600Z/100M R697 IDJ-B27-F6T
1U 0.1U 100P From 47P 1608 4.7K/NA
0603 0603 0603 0603
50V

2
Modify by 12/15 '00

1
V00-V0A
5V_AMP
AGND CAGND
C625
V00-V0A
R585 R583 (NA)
1 2 1 2 1 2 C260 100U 1 2 16V EW6.3
+

33K 0603 22K V00-V0A

2.2U 0603 (NA)
0805 C623 50V Internal Speaker Connector V0A-V0B VCC5
+80-20% 1 2 (Add C286,C665) Line Out Phone Jack

1
Amplifier C206 C205

1
AOUT_R/L Cap x2 - SIZE0805 0.1U_NA 0603 U18 J22 L46 J25 C210 R163 R155 0.1U_NA 10U/NA
VR1_5 SPKROUT+ HIROSE LINE_OUT_5 R.CH 3300P_NA 2.74K_NA 100K_NA 0603 1206
21 22 1 1 2 5 0603
RLINE IN R OUT+ SPKROUT- ST/MA-2 1608 600Z/100M LINE_OUT_4 0603 0603 LP2975_NA SSOP8 50V 10V
R

2
20 15 2 4 25V
VR1 R582 RHP IN R OUT- DF13-2P-1.25V L532 1%

2
3 10% 4 8
10K SPKLOUT+ J21 LINE_OUT_2 GROUDN INPUT

2
1 2 3 1 1 2 2 3 7
L OUT+ COMP CURR_LIM
5

C259 4.7U 16V 1206 0603 22K 4 10 SPKLOUT- 2 L HIROSE 1608 600Z/100M 1
L.CH
2 6 U15
LLINE IN L OUT- FEEDBACK N/C
1

1
AOUT_R 1 2 VR1_4 4 5 ST/MA-2 1 5 SO8
LHP IN ON/OFF GATE
1

1
C624 R584 DF13-2P-1.25V R199 R692 R162 SI4835DY_NA
18 C286 C665
RVDD

1
2
3
AOUT_L 1 2 VR1_1 1 3 1 2 1 2 1 2 7 1K 1K 100P 100P RA/D3.6/5P 1K_NA U14
LVDD

2
6 C249 0603 0603 0603 0603 HCH 0603 S
V00-V0A
C258 4.7U 16V 1206 2.2U 0.1U_NA 50V 0603 L BYPASS IDJ-B27-F6T 1% JS504 (From OPEN-SMT4)
2

19 1 2
0805 33K C622 R BYPASS GND0
2

2
+

12 1 2 4
GND1 SHORT-SMT4
1

+80-20% 0603 L45

C613 C250 GND2
13 Very Close to TPA0202 Pin 18/7
1U 1U 14 24 100U 1 2 G
SE/BTL# GND3
1

AGND 0603 0603 16V AGND

1
16 C612 C255 C610
HP/LINE# EW6.3
D
2

11 2 0.1U 0.1U 4.7U

MUTE IN NC0 0603 0603 1206 120Z/100M
9
MUTE OUT NC1
17
50V 50V 16V
V00-V0A AGND
1608
CAGND
Modify by 12/15 '00 AGND AGND (C610 From 10uF)
2

5
6
7
8
23 5V_AMP
C256 R186 R184 NC2
8
SHUTDOWN

1
1 2 1 2 1 2 C220
A A

1
0603 22K 30 25 AGND AGND AGND + 47U_NA C233
2.2U G6 G1 5V_AMP
31 26 7343 10U_NA
0805 33K C232 G7 G2 6.3V 1206
32 27
+80-20% 0603 G8 G3 10V

2
1 2 33 28
G9 G4
1

34 29
50V 0603 G10 G5 R205 AGND AGND
VR1_2 0.1U_NA TPA0202_GND TSSOP24_TPA0102 100K
AGND AGND 0603
R204
R183 22K
2

1 2
10603 2
C257 R174 C231 100K
1 2 1 2 1 2 0603 Title
Signal HI LOW AUDIO CODEC & AMPLIFIER
2.2U 0.1U_NA 50V 0603
0805 33K Size Document Rev
+80-20% 0603 SPK_OFF SPK_OFF Shut Down Normal 411669900014 0A
11 SPK_OFF Number
Date: Friday, May 04, 2001 Sheet 13 of 22

5 4 3 2 1
 5 4 3 2 1

VCC3 VCC5 -VCCEN0

PCMCIA CONTROLLER & CARD BUS SCOKET -VCCEN1
VPPEN0
VPPEN1

1
R102 R101
0 0/NA For PCMCIA Controller Decoupling
0603 0603

VCC3 VCCA VCC3

2
V00-V0A
(NA)
Card Bus Socket

1
C13 C172 C173 C185 C511 C179
0.1U 0.1U 0.1U 0.1U 0.1U 10U_NA VCCA
0603 0603 0603 0603 0603 1206

W13
M14

M18
M19
R10

H19

U12

R19

H15
A13

A12

V12

A15
E11

P14
F17

L15
J18
W7

W5
M1

M5
50V 50V 50V 50V 50V 10V

G1

R9
AD[0..31]

V6

P3

B9
A7

E7

E1

A5

2
U21

L2

J5
6,10,19 AD[0..31]
AD0 U9

VCCP0
VCCP1

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10

VCCI

VCCL

VCCCB0
VCCCB1

VCCD0
VCCD1

VPPD0
VPPD1

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
D AD0 D
AD1 V9 L18 CAD0
AD1 CAD0

1
AD2 W9 L14 CAD1 VCC3 C158
AD3 AD2 CDA1 CAD2
AD4
W8
AD3 CDA2
L17
CAD3
0.1U V00-V0A
V8 K18 0603 (Change Conn type)
AD5 AD4 CAD3 CAD4 50V Modify by 12/15 '00

2
U8 K19
AD5 CAD4

1
AD6 R8 K15 CAD5 C277 C278 C279 C280 C281 J14
AD7 AD6 CAD5 CAD6
V7 K17 0.1U 0.1U 0.1U 0.1U 0.1U 1 35
AD8 AD7 CAD6 CAD7 0603 0603 0603 0603 0603 CAD0 -CCD1
P8 J19 2 36
AD9 AD8 CAD7 CAD8 50V 50V 50V 50V 50V CAD1 CAD2

2
W6 J17 3 37
VCC3 AD10 AD9 CAD8 CAD9 CAD3 CAD4
R7 J15 4 38
AD11 AD10 CAD9 CAD10 CAD5 CAD6
U6 H18 5 39
AD12 AD11 CAD10 CAD11 CAD7 R2_D14
V5 H17 6 40
AD13 AD12 CAD11 CAD12 -CCBE0 CAD8
V00-V0A AD14
P7
AD13 CAD12
G19
CAD13
7 41
CAD10
(Add Res) R6 H14 CAD9 8 42
AD15 AD14 CAD13 CAD14 CAD11 CVS1
U5 G17 9 43
AD15 CAD14

1
AD16 N6 G18 CAD15 CAD12 10 44 CAD13
R72
0_NA
AD17
AD18
N3
N2
AD16
AD17
AD18
PCI4410 uBGA209 CAD15
CAD16
CAD17
G14
B15
CAD16
CAD17
CAD14
-CCBE1
11
12
45
46
CAD15
CAD16
VCC3 0603 AD19 N1 C14 CAD18 Close to PCI4410 CPAR 13 47 R2_A18
AD20 AD19 CAD18 CAD19 -CPERR -CBLOCK
M2 B14 14 48
AD21 AD20 CAD19 CAD20 VPPA -CGNT -CSTOP

2
U26 L5 A14 15 49
AD22 AD21 CAD20 CAD21 -CINT -CDEVSEL
6,9,10,12,18,19 -PCIRST 1 5 L6 C13 16 50
A VCC -CBRST AD23 AD22 CAD21 CAD22 VPPA
11 -GATE1394 2 4 L3 B13 17 51
B Y AD24 AD23 CAD22 CAD23
3 K5 C12 18 52
GND AD25 AD24 CAD23 CAD24 CCLK -CTRDY
K3 A11 19 53
AD26 AD25 CAD24 CAD25 -CIRDY -CFRAME
NC7S08 K2 B11 20 54
AD26 CAD25

1
SC70 AD27 K1 C11 CAD26 C131 -CCBE2 21 55 CAD17
AD28 AD27 CAD26 CAD27 CAD18 CAD19
J6 C9 10P/NA 22 56
AD28 CAD27

1
V00-V0A AD29 J3 F9 CAD28 VCCA C162 0603 CAD20 23 57 CVS2
AD30 AD29 CAD28 CAD29 10% CAD21 -CRST
(ADD)

2
J2 E9 0.1U 24 58
AD31 AD30 CAD29 CAD30 0603 CAD22 -CSERR
J1 A8 25 59
TP108 AD31 CAD30 CAD31 ZV_Y[0..7] 50V CAD23 -CREQ

2
1 W10 C8 ZV_Y[0..7] 6 26 60
MFUNC0 CAD31

1
SDATA V10 CAD24 27 61 -CCBE3
-CARD_RI 0603 2 0 MFUNC1 ZV_Y0 R104 CAD25 -CAUDIO
10 -CARD_RI 1 P10 R13 28 62
SERIRQ R99 MFUNC2 ZV_Y(0) ZV_Y1 47K CAD26 CSTSCHG
11 SERIRQ W11 U14 29 63
SCLK MFUNC3 ZV_Y(1) ZV_Y2 0603 CAD27 CAD28
U11 W15 30 64
ZV_ACT MFUNC4 ZV_Y(2) ZV_Y3 CAD29 CAD30
P11 V15 31 65
-PCLKRUN MFUNC5 ZV_Y(3) ZV_Y4 R2_D2 CAD31

2
6,10,11,19 -PCLKRUN V00-V0A R11
MFUNC6 ZV_Y(4)
R14
ZV_Y5
32 66
-CCD2
(From 75ohm) U15 -CCLKRUN 33 67
PCPCLK ZV_Y(5) ZV_Y6
16 PCPCLK M6 W16 34 68
PCLK ZV_Y(6) ZV_Y7 ZV_UV[0..7]
C ZV_Y(7)
T19 ZV_UV[0..7] 6 GND1 Modify by 12/15 '00 C
1 0603 2 0 -GRST V11 GND2
R137 -CARDSPK G_RST ZV_UV0
13 -CARDSPK U10 R17 GND3
-PME 0603 2 0 SPKROUT ZV_UV(0) ZV_UV1
11,17,19 -PME 1 P9 N14 GND4
R103 0603 2 -CBSUS RI_OUT/PME ZV_UV(1) ZV_UV2
1 W12 P15
-CBRST VCC3 R98 47K SUSPEND ZV_UV(2) ZV_UV3
M3 P17 FM/34X2P/H7.7
-GNT0 RST ZV_UV(3) ZV_UV4 VCC5
6 -GNT0 H1 R18
R117 -REQ0 GNT ZV_UV(4) ZV_UV5 FCI 62598-22A
6 -REQ0 H2 N15
AD21 REQ ZV_UV(5) ZV_UV6
1 0603 2 L1 P18 U9
100 -FRAME IDSEL ZV_UV(6) ZV_UV7 ZV_ACT
6,10,19 -FRAME P2 N17 1 5
-IRDY FRAME ZV_UV(7) A VCC
6,10,19 -IRDY N5 2 4 ZV_SCLK 13
-TRDY IRDY ZV_PCLK B Y
6,10,19 -TRDY R1 M17 ZV_PCLK 6 3
VCC3 -DEVSEL TRDY ZV_PCLK ZV_DATA GND
6,10,19 -DEVSEL P6 M15 ZV_DATA 13
-STOP DEVSEL ZV_SDATA ZV_LRCLK
6,10,19 -STOP R2 N19 ZV_LRCLK 13 NC7S08/NA
STOP ZV_LRCLI ZV_MCLK
1 R115 2 4.7K 0603 P5 N18 ZV_MCLK 13
SC70
-SERR PERR ZV_MCLK ZV_SCLK1
6,10,19 -SERR R3
SERR ZV_SCLK
P19 1 2 V00-V0A
-CBE[0..3] PAR T1 V14 ZV_SYNC (R121/122 from 2.7K)
6,10,19 -CBE[0..3] 6,10,19 PAR PAR ZV_VSYNC ZV_HREF ZV_SYNC 6
W14 0 R113 0603 VCC5 VCC3
-CBE0 ZV_YHREF ZV_HREF 6 R88
U7
-CBE1 C/BE0 -CCBE0 -VCCEN0
W4 J14 1 2 3 1
-CBE2 C/BE1 CC/BE0 -CCBE1
P1 F19
-CBE3 C/BE2 CC/BE1 -CCBE2
K6 F13
C/BE3 CC/BE2

1
B12 -CCBE3 47K Q7
-INTA CC/BE3 R122 R121 0603 DTC144WK
10 -INTA V13
PHY_RSVD10
PHY_RSVD11
PHY_RSVD12
-INTD IBTA -CCD1 4.7K 4.7K
PHY_RSVD0
PHY_RSVD1
PHY_RSVD2
PHY_RSVD3
PHY_RSVD4
PHY_RSVD5
PHY_RSVD6
PHY_RSVD7
PHY_RSVD8
PHY_RSVD9
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7

U13 L19

PHY_CTL(0)
PHY_CTL(1)
10,19 -INTD

PHY_LREQ
INTB CCD1

LEDA_SKT

CSTSCHG
-CCD2 0603 0603

CCLKRUN
A9

CDEVSEL
PHY_CLK

CFRAME
CCD2

CBLOCK

CRSVD0
CRSVD1
CRSVD2
CAUDIO
-1394WR

LINKON

2
P12

CSERR
CPERR
CSTOP

CTRDY
-1394WR 11

CIRDY
RSVD

CREQ

CGNT
CPAR

CRST
CCLK
CVS1

2
P13 F11

CINT
RSVP CVS1

LPS
E13 CVS2 U10
CVS2 SDATA
1 5
A0 SDA

G15
R12

D19
C10

C15
E12

E10

E19
B10

E18
A10

E17
A16

E14

K14
F14

F15

F12

F10

F18
G6

G5

G3
G2
C6

C5

D1

H6

H5
H3

C7
B6

B5
E6

A4

E3

E2

E8
B7

A6

B8
F6

F5

F3
F2

F1

F7

F8
PCI4410GHK SCLK R89
BGA_GHK_209 2 6
A1 SCLK -VCCEN1
1 2 3 1
3 7
PHY_LREQ

PHY_CTL0
PHY_CTL1

A2 WC-
PHY_CLK

Q8
PHY_D0
PHY_D1
PHY_D2
PHY_D3
PHY_D4
PHY_D5
PHY_D6
PHY_D7

-CDEVSEL

-CCLKRUN
2 0603

-CFRAME
CSTSCHG
47K DTC144WK

-CAUDIO

-CBLOCK
4 8

PHY_LKON

-CSERR
-CPERR

-CTRDY

R2_D14
GND VCC

R2_A18
-CSTOP
PHY_LPS 0603

-CIRDY
-CREQ

R2_D2
-CGNT

-CRST
CPAR

-CINT
NM24C02N

1
SO8 C186
1394AVDD VCC3

2
22 0.1U
Closed to PHY 0603 -1394WR
50V Write Protect when high.

2
B B
The singals need to be
1
1

C14 C35 C12 C23 C510

0.1U the same,length must
R80

0.1U 0.1U 0.1U 0.1U

0603 0603 0603 0603 0603 not execeed 4 inches
50V 50V 50V 50V 50V
2

CCLK

The length TPA+ and TPA- must

VCC3 1394AVDD VCC3 VCC3
L17 be the same.Also,TPB+ and TPB-
1 2 must be the same.Both pair
need to be as close the same J3
120Z/100M length as possible. TPB- R500 0 1 2 0603 1
1608 TPB+ R502 0 0603 1
30
31
42
51
52

25
26
61
62

16
56

1 2 2
U500 TPA- R501 0 0603 2
1 2 3
PHY_CTL0 TPA+ TPA+ R503 0 0603 3
4 37 1 2 4
PLLVDD
AVDD0
AVDD1
AVDD2
AVDD3
AVDD4

DVDD0
DVDD1
DVDD2
DVDD3

NC5

PHY_CTL1 CTL0 TPA+ TPA- 4

5 36
CTL1 TPA-
Close to PHY GND1
GND1
PHY_D0 6 46 GND2
D0 NC0 GND2
1

PHY_D1 7 45
D1 NC1 R18 R17
PHY_D2 8 IEEE1394/4P
D2 TPB+ 56 56
PHY_D3 9 35 LINKTEK
D3 TPB+ TPB- 0603 0603
PHY_D4 10 34 AVR20-4XXX0X
VCC3 D4 TPB-
PHY_D5 11
D5 JS6
2

PHY_D6 12 44
D6 NC2
PHY_D7 13 43 1 2
D7 NC3
20 38 SHORT-SMT4
R5 PC0 TPBIAS
21 47
PC1 NC4
1

1K 22 Close to PHY C26 1394_GND

0603 PC2 C31
54 1 2 1U
FILTER0
1

PHY_LKON 1 2 19 55 0.1U 0603

PHY_CLK C/LKON FILTER1 50V R3 R10
2

1 2 2
SYSCLK 0603 56 56
23 53
R505 PHY_LREQ ISO RESET 0603 0603
1 27
10 LREQ TESTM U5
1

0603 PHY_LPS PHY_XI -VCCEN0 VCCA

2

15 59 1 16 VCC3
LPS XI VCCD0 SHDN
1

24 C32 R21 -VCCEN1 2 15 VPPEN0

CPS PHY_XO VCCD1 VDDP0
A 60 0.1U 110K_NA VCC3 3 14 VPPEN1 A
XO 3.3VA VDDP1
1

3 0603 0603 4 13
PLLGND0
PLLGND1

CNA 3.3VB AVCCA

1

R6 50V R15 VCC5

2

14 40 C18 5 12
DGND0
DGND1
DGND2
DGND3
AGND0
AGND1
AGND2
AGND3
AGND4
AGND5

10K PD R0 4.99K 5VA AVCCB VPPA

2

28 41 270P 6 11
0603 SE R1 0603 0603 5VB AVCCC
29
SM Close to CP2211 7
GND AVPP
10
1

1% 10% PHY_XI
2

1 2 8 9 +12V
OC 12V
1

R19 R20 Close to CP2211

2

C183 C182 C200 C201

32
33
39
48
49
50

17
18
63
64

57
58

R504 R13 R16 R8 TSB41AB1 6.34K 1M C21 0.1U 0.1U 0.1U 0.1U CP2211 SSOP16
2

1
4.7K 1K 1K 1K PQFP64_0.5MM 0603 0603 10P 0603 0603 0603 0603 C170 C169 C171 C147
2

0603 0603 0603 0603 1% 1% 0603 50V 50V 50V 50V

2

V00-V0A 0.1U 4.7U_NA 0.1U 4.7U_NA

X1 R23 0603 1206 0603 1206
2

24.576MHZ 1M_NA from TPS2211 50V 16V 50V 16V

2

2
Meet 6.3K ohm. V00-V0A 0603
C34
(R15 from 5.1K)
1

PHY_AGND L20 PHY_XO Title

1 2
V00-V0A 1 2 PCMCIA Controller & Socket
(R504 from 2.7K) 120Z/100M
2012 10P Size Document Rev
0603 0A
Number 411669900014
PHY_AGND
Date: Friday, May 04, 2001 Sheet 14 of 22
5 4 3 2 1
 A B

Place two fuses on same location,

only use one fuse.
F5
1 2

mircoSMDC110

F4
1 2 USBVCC5
TOUCH_PAD VCC5
MINISMDC110

1
V00-V0A R2
(R1,R2 from 470K/576K) 33K
0603
Modify by 12/15 '00
-USBOC1

2
10 -USBOC1 L16
VCC5

1
1 2

1
C10 R1
L521 120Z/100M 1608 1000P 47K 120Z/100M

1
1 2 1 J17 0603 0603 C17 2012 C9
T_DATA L38 1 2 120Z/100M 1608

2
17 T_DATA 2 10U_NA 0.1U
T_CLK L37 1 2 120Z/100M 1608 1206 0603

2
17 T_CLK 3 HIROSE 10V 50V

2
4 ST/MA-4
V00-V0A V0A-V0B
DF13-4P-1.25V (NA) L12 (NA)
Close to North Bridge 200Z/100M_NA GND_USB
R161 2012

1
C189 C188 C627
47P 47P 0.1U USBP1- 1 2 1 2
10 USBP1-
0603 0603 0603 V00-V0A
50V (J17 from 8pin)

2
2 22 2

0603 V0A-V0B
(Add L57)4 3
L57
W/S=6/12 mils 1 2 200Z/100M
CORE_ACM2520U

R157
USBP1+ 1 2 1 2
10 USBP1+
L14

1
C209 C207 22 200Z/100M_NA C6 C7
Layout note: Same legth 47P
0603
47P 0603
0603
R160
15K
R156
15K
2012
47P/NA 47P/NA
0603 0603 V00-V0A 0603 0603

2
USBP0- (From L12/L14 NA)

2
USBP0+ V0A-V0B
(NA)
GND_USB
Flash ROM

XD[0..7] SA[0..17] J26

11,17 XD[0..7] SA[0..17] 11,12,17
U8 1
XD0 13
O0 A0
12 SA0 GND 2
1
2
XD1 14 11 SA1 3
XD2 O1 A1 SA2 3
15 10 4
XD3 O2 A2 SA3 4
17
O3 A3
9 10mil
XD4 18 8 SA4 GND1
XD5 O4 A4 SA5 GND1
19 7 GND2
XD6 O5 A5 SA6 GND2
20
O6 A6
6 10mil GND3
GND3
XD7 21 5 SA7 GND4
Flash ROM

O7 A7 SA8 GND4
A8
27 5mil
26 SA9 USBP- V00-V0A
A9 USB/4PX1
1 23 SA10 (From VCC5+Fuse) JO500
11 SA18 VPP A10 LINKTEK
25 SA11 5mil 1 2
A11 SA12 GND_USB 16 UAR80-4W510
VCC5 4 USBP+ USBVCC5 GND_USB
A12 SA13 SHORT-SMT4
A13
28 5mil
29 SA14
A14

1
Close to EEPROM 3 SA15 10mil GND_USB
A15 SA16 R11
32 2
VCC A16
1

C199 30 SA17 V00-V0A 33K

A17 -ROMCS 0603
0.1U
CE#
22 -ROMCS 11,17 10mil (R4,R11 from 470K/576K)
0603 24 -MEMR
50V OE# -MEMR 11
-USBOC0
2

2
-MEMW 10 -USBOC0 L15 J27
16 31
VSS WE# -MEMW 11 GND

1
1 2 1
1

1
28F020-PLCC C11 R4 120Z/100M 2
47K 2012 2
1000P 3
3

1
0603 0603 C19 C8 4
10U_NA 0.1U 4

2
1206 0603

2
GND1
10V 50V GND1

2
GND2
GND2
V00-V0A V0A-V0B GND3
GND3
(NA) (NA) GND4
GND4
Close to North Bridge L9 GND_USB
R167 200Z/100M_NA USB/4PX1
2012 LINKTEK
USBP0-
Place two fuses on same location, 10 USBP0- 1 2 1 2
GND_USB
UAR80-4W510
F501 only use one fuse. V0A-V0B
VCC5 1 2 (Disable bluetooth function) 22 V00-V0A
0603 (From J5 8pin Conn.)
mircoSMDC110_NA
V0A-V0B
W/S=6/12 mils (Add L58)4 3
F502 L58
1 2 8 Q507 1 2
NDS9410_NA 600Z/100M
7 3 CORE_ACM2520U
MINISMDC110_NA 6 2 SO8
5 1
D

S
G

R165
1

C639 C640 L11

1206 USBP0+
4

0.1U_NA 10 USBP0+ 1 2 1 2
10U/NA 0603 +12V
10V 50V R649
2

1
1 2 C218 C212 22 200Z/100M_NA

1
470K_NA 0603 47P 47P 0603 R166 R164 2012 C4 C5
0603 0603 15K 15K V00-V0A 47P/NA
Q508 VCC3 0603 0603 (From L9/L11 NA) 0603 47P/NA

2
1
3 1
1

R1 0603

2
2
R650 V0A-V0B

2
1
DTC144TKA_NA 33K_NA (NA)
0603
11 ENBTPWR
GND_USB
-USBOC2
2

11 -USBOC2 L522
1

1 2
1

C641 R651
1000P 47K_NA 120Z/100M_NA V00-V0A
1

0603 0603 C642 2012 C643 (All new add)

2

10U_NA 0.1U_NA
1206 0603
2

10V 50V
2

Blue Tooth
Close to North Bridge
J504
R82 L523 1
USBP2- 1
10 USBP2- 1 2 1 2 2
22 0603 2
3
BEAD_NA 3
4
0603B 4
W/S=6/12 mils
MA/4PX1/1.25MM_NA
HIROSE
R86 L524 DF13-4P-1.25H
USBP2+ 1 2 1 2
10 USBP2+
22 0603
BEAD_NA
1

C50 C54 0603B

47P_NA 47P_NA R91 R92
0603 0603 15K 15K
0603 0603
2

Title
2

Beach Connector

Size Document Rev

C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 15 of 22
A B
 A B

CLOCK GENERATOR VCC3

L506
1 2
Layout Note: V00-V0A

1
C545 120Z/100M C550 C558 C542 C564
2012
Signal Name Trace Length Limit W/S 0.1U
0603
4.7U_NA
1206
0.1U
0603
0.1U
0603
0.1U
0603
50V 16V 50V 50V 50V

2
HCLK_CPU Lcpu 1" - 7" 6/12
NBHCLK Lcpu+2" 3" - 9" 6/12 VCC3

L510

DCLKO Modify by 12/15 '00 愈愈愈愈 1 2

DCLKI Lsd+2" 3" - 6" 6/12 V00-V0A

1
120Z/100M C581 C585
C187 2012 0.1U 2.2U_NA
0.1U 0603 1206
50V 50V 16V
SDRAMCLK0 Lsd 1" - 4" 6/12

2
0603
SDRAMCLK1 Lsd 1" - 4" 6/12
VCC3
SDRAMCLK2 Lsd 1" - 4" 6/12 L511

SDRAMCLK3 Lsd 1" - 4" 6/12 1 2

1
C587 120Z/100M C584
0.1U 2012 0.1U
0603 0603 R532 1 2 10 0603
SBPCLK Lpci 4" -15" 6/12 50V 50V NBHCLK 6

2
R534 1 2 10 0603
PCPCLK Lpci 4" -15" 6/12 HCLK_CPU 4
VCC3
MINIPCCLK Lpci-3" 1" -12" 6/12 L36

1
C557
2
NBPCLK Lpci 4" -15" 6/12 1 2
U503 10P_NA
C560
10P_NA
2

V00-V0A 1 46 0603 0603

VDDREF CPUCLK_F

1
120Z/100M

2
C184 C193 C566 C574 6
2012 VDDPCI0
REFCLK0 愈愈愈愈 6/12 0.1U
0603
2.2U_NA
1206
0.1U
0603
0.1U
0603
14
VDDPCI1 CPUCLK0
CPUCLK1
45
43
V00-V0A
(HCLK_CPU from pin43)
50V 16V 50V 50V
PICCLK L14m 6/12

2
19 42
VDDCOR CPUCLK2
愈愈愈愈 27
VDD48

Clock generator
DCLKO
OSC14M L14m 6/12 VCC2.5 30
SDRAM_IN
15
39 R536 1 2 10 0603 DCLKI
DCLKO 6
L508 VDDSDR0 SDRAM_F DCLKI 6
36
VDDSDR1 R538 1 SDRAMCLK0
1 2 47 38 2 10 0603
SDRAMCLK0 8
VCC3 VDDLCPU SDRAM0 R540 1 SDRAMCLK1
37 2 10 0603
SDRAMCLK1 8
SDRAM1 R548 1 SDRAMCLK2
V00-V0A 3 35 2 10 0603
SDRAMCLK2 8
GNDREF SDRAM2

1
C546 120Z/100M C559 C552 9 34 R553 1 2 10 0603 SDRAMCLK3
2012 GNDPCI0 SDRAM3 SDRAMCLK3 8
0.1U 0.1U 2.2U_NA 16 32
GNDPCI1 SDRAM4

1
0603 0603 1206 31
SDRAM5

1
2 50V 50V 16V R561 R557 R663 C568

2
22 29 C578 C573 C565 C562
10K 10K 10K GNDCOR0 SDRAM6 10P_NA 10P_NA 10P_NA 10P_NA 10P_NA
33 28
0603 0603 0603 GNDSDR1 SDRAM7 0603 0603 0603 0603 0603
40
GNDSDR2 -PCISTP VCC3

2
44 20 -PCISTP 11
GNDLCPU PCI_STOP#

2
SMBDATA 23 7 R526 1 2 10K 0603
8,11 SMBDATA SMBCLK SDATA CPU2.5_3.3#/PCICLK_F
8,11 SMBCLK 24
-SUSA R662 1 0_NA0603 SCLK
4,6,9,11,17 -SUSA 2 21
PD# FS3 R531 1 22 0603 SBPCLK
8 2 SBPCLK 10
-CPUSTP FS3/PCICLK0 R535 1 22 0603 PCPCLK
41 10 2 PCPCLK 14
11 -CPUSTP CLK_STOP# PCICLK1 R537 1 22 0603 MINIPCICLK
11 2 MINIPCICLK 19
USBCLK FS0 PCICLK2 NBPCLK
10 USBCLK 2 1 R556 22 0603 26 12 R539 1 2 22 0603
NBPCLK 6
FS1 48M/FS0 PCICLK3
25 13
24M/48M/FS1 PCICLK4
PCCLK/OSC14 平長 6 REFCLK0
4 PICCLK
REFCLK0
PICCLK
2
2
1 R528
1 R525
22
22
0603
0603
FS2 48
2
REF1/FS2
REF0
PCICLK5
PCICLK6
17
18

1
2 1 R524 22 0603
REFCLK0/14M_TV平長 11 OSC14M
9 14M_TV
14M_TV 2 1 R672 22 0603 4
X1 X2
5 R533
C567
10P
C563
10P
C561
10P
C556
10P
10K 0603 0603 0603 0603
0603

2
ICS9248-195 SSOP48

Pull-Low for pin25 o/p 48MHZ.

2
1

1
V00-V0A R523
C547 C548 C554 C661 C583 (From 9248-143) 1 2
MTG4 10P/NA 10P/NA 10P/NA 10P/NA 10P 1M 0603
ID2.8/OD7.6 0603 0603 0603 0603 0603
2

2
3
2
1

4 12
5 11 X500
6 10 1 2

1
C549 14.318MHZ C551
7
8
9

10P 10P
0603 0603

2
GND_PS2 17

Screw Hole
VCC3

MTG12 VCC3

1
MTG3 ID2.8/OD6.0 FD3 FD503 FD1 FD2 Configuration of Pin 10 will select the freq. of Pin 25. Verify the
ID2.8/OD7.6 FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK R559
results with spec. Correcting to mount 10k pull-high or 0 pull-low.
3
2
1

1
10K
4 12 H:24MHZ L:48MHZ 0603 VCC3
R625
1

5 11
10K
1

2
6 10

1
14 U508A 0603 R560
10K

2
FD502 FD4 FD501 FD500
0603 2 FS0 R105
7
8
9

FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK 1 2 1

4 BSEL0 10K
7 SO14 0603
R626

2
74LVX07 14 U508B
10K
1

MTG11 E501 E3 E506 E500 3 4 1 0603 2

MA8 6,8
ID2.8/OD6.0 MTG6 TOUCHPAD_METAL TOUCHPAD_METAL TOUCHPAD_METAL TOUCHPAD_METAL
ID2.8/OD7.6 VCC3 VCC37 SO14
Frequency Select
3
2
1

3
2
1

13 74LVX07
4 12 4 12 FS3 FS2 FS1 FS0 CPU( MHZ) PCI( MHZ)

1
1

5 11 5 11
6 10 6 10 0 0 0 0 66.67 33.33 R512 VCC3
0 0 0 1 100.00 33.33 10K R627
0 0 1 0 100.30 33.43 0603 14 U508C 10K R564

1
0603 10K
7
8
9

7
8
9

0 0 1 1 133.33 33.33
0 1 0 0 105.00 35.00 0603 2 FS1 R107

2
1
E503 E502 E504 E505 5 6 1 1

4 BSEL1 10K
TOUCHPAD_METAL TOUCHPAD_METAL TOUCHPAD_METAL TOUCHPAD_METAL 0 1 0 1 133.37 33.34 SO14
0 1 1 0 137.00 34.25 7 0603
0 1 1 1 75.00 37.50 74LVX07 14 U508D R628
10K

2
1 0 0 0 100.00 33.33
MTG9 MTG8 1 0 0 1 95.00 31.67 0603 2
1

9 8 1 MA12 6,8
ID2.8/OD7.6 ID2.8/OD7.6 1 0 1 0 97.00 32.33
3
2
1

3
2
1

SO14
1 0 1 1 133.33 33.33 7
4 12 4 12 1 1 0 0 90.00 30.00 74LVX07
5 11 5 11 1 1 0 1 96.22 32.07
6 10 6 10 1 1 1 0 66.82 33.41
MTG5 1 1 1 1 91.50 30.50
ID2.2/OD5.0 Internal Pull-Up 120Kohm R529 10K 0603
FS2
7
8
9

7
8
9

1 2

R527 10K 0603

1

CAGND FS3 1 2

MTG10 AGND
ID2.8/OD7.6
3
2
1

4 12
5 11
6 10 MTG7
ID2.8/OD7.6
3
2
1
7
8
9

4 12
5 11
6 10
MA12 MA8 CPU( MHZ)
GND_USB 15
0 0 66.67
7
8
9

0 1 100.00
1 0 AUTO Title
1 1 133.33 CLOCK GENERATOR

Size Document Rev

C 411669000014 0A
Number
Date: Friday, May 04, 2001 Sheet 16 of 22
A B
 A B

VCC5
VDD5
MICRO CONTROLLER

1
5VALWAYS R530
Email BTN 4.99K
BAV99_NA 0603 U11B U11A
5VALWAYS 1%

14

14
2 74AHC08_V_NA 74AHC08_V_NA

2
SW3 3

1
BAV99_NA HDK632A 1 C30 4 1
THRM_RES
2 25V/24M D501 1U_NA 6 3
3 KO0 1 2 KI1 0603 5 2
13 KO0 KI1 13

1
BAV99_NA

2
1
D502 2 R112 TSSOP14 TSSOP14
VDD5 H8_VDD5 VDD5 20K

3
4

7
3
L509 0603
1
BAV99_NA D503 Close to H8-3434F 1 2 Close to H8-3434F 1%
VCC3

2
2

3
3 BAV99_NA

1
1 2 C540 C571 C572 120Z/100M C555 C553 D3
D500 3 0.1U 0.1U 0.1U 1608 0.1U 0.1U VCC_CORE
0603 0603 0603 0603 0603 BAV70LT1
EASY START BTN 1
D506 50V 50V 50V 50V 50V VTT

2
J9
BAV99_NA KO1 2 KI1

2
1
2 KO0 3 4 KI2 BAV99_NA
3 -PWRSW 5 6 KI3 2 RP30 33*4
1 7 8 KI4 3 GND_H8 1206 Come From Battery
D505 9 10 1 BAT_TEMP 1 8 BAT_T
BAT_VOLT BAT_V BAT_T 21
D504 2 7 BAT_V 21

4
3
2
1
SPEED L507 3 6 BAT_C
BAT_C 21

1
S100-0000-101 1 2 RP29 C181 C180 4 5 BAT_D
BAT_D 21
HDR/SHR/MA/5PX2 1K*4 0.1U 0.1U
V00-V0A 1206 0603 0603 VDD3
(Pin9 from INT_MIC) GND_H8 JP_BEAD_DFS 50V 50V

2
59
37

70
71
92
15
46
36
H8_THRM_CLK 4

4
0603B_DFS U502
V0A-V0B

AVREF
AVCC
VCC1
VCC2

VSS1
VSS2
VSS3
VSS4
VCCB

AVSS

5
6
7
8
J15
GND_H8 H8_THRM_DATA 4 (Add Q21,R108)
3
1 KO0 79 38 -H8_RSMRST 2 R1 Q21
KO1 P10/A0 P70/AN0
2
2 78 39 1DTC144TKA 2

KO2 P11/A1 P71/AN1

3 77
P12/A2 P72/AN2
40 Cover Switch Signal HI LOW
4 KO3 76 41 -RSMRST
P13/A3 P73/AN3 R558 -RSMRST 11
5 KO4 75 42 SW4
KO5 P14/A4 P74/AN4
6 74
P15/A5 P75/AN5
43 1 2 1 3 -LID Normal Suspend

1
7 KO6 73 44 -H8_RSMRST 2 4
P16/A6 P76/AN6/DA0

2
8 KO7 72 45 BLADJ C586 R108
P17/A7 P77/AN7/DA1 BLADJ 22 10K
9 KO8 67 93 SA2 2.2U 1K MPU-101-80 V0A-V0B
P20/A8
Micro P80/HA0 SA2 11,12,15 0603 R114
Internal Keyboard

10 KO9 66 94 H8_A20GATE 16V (Add R114) V00-V0A 0603

KO10 P21/A9 P81/GA20 -H8_KBCS 1206 VDD5 (From VCC5)

1
11 65 95 1 2
KO11 P22/A10
Controller P82/CS1 -IOR

2
12 64 96 -IOR 11
KO12 P23/A11 P83/IOR -IOW 0
13 63 97 -IOW 11
AGND
KO13 P24/A12 P84/IRQ2/TXD1/I -H8_MCCS 0603
14 62 98 -LID 13
KO14 P25/A13 P85/IRQ4/RXD1/C BAT_CLK U11D
15 61 99
P26/A14 P86/IRQ5/SCK1/S
Connector

KO15 -H8_SUSC

14
16 60 25 74AHC08_V_NA
XD0 P27/A15 P90/IRQ2/ESC2 -LID
17 82 24
XD1 P30/HDB0/D0 P91/IRQ1/EIOW -POWERBTN -PWRSW
18 83 23 1 2 12
XD2 P31/HDB1/D1 P92/IRQ0 -H8_THRM
19 84 22 11
P32/HDB2/D2 P93/RD

1
20 XD3 85 19 SW_VDD5 C570 R554 13
P33/HDB3/D3 P94/WR SW_VDD5 21 -SUSC 11,22
21 XD4 86 18 -H8_MVP4BT 0.1U 1K
P34/HDB4/D4 P95/AS

1
22 XD5 87 17 H8_A20GATE 50V 0603 TSSOP14
XD6 P35/HDB5/D5 P96/0 BAT_DATA 0603 R125

7
23 88 16
XD7 P36/HDB6/D6 P97/WAIT/SDA H8_MODE0 1M
24 89 6
P37/HDB7/D7 MD0 H8_MODE1 0603
49 5
XD[0..7] -H8_WAKE_UP P40/TMCI0 MD1 LED_CLK U11C
11,15 XD[0..7] 50 91 LED_CLK 9
FPC/FFC/1MM/24P -H8_SMI P41/TMO0 PB0/XDB0 LED_DATA

2
51 90

14
9,13 -BTOOTH P42/TMRI0 PB1/XDB1 LED_DATA 9 74AHC08_V_NA
85203-24-02 H8_SCI 52 81 VADJ1
P43/TMCI1/HIRQ1 PB2/XDB2 VADJ1 22
ACES V00-V0A IRQ1 53 80 VADJ2 9
10 IRQ1 P44/TMO1/HIRQ1 PB3/XDB3 CHARGING VADJ2 22
From TP IRQ12 54 69 8
10 IRQ12 LEARNING P45/TMRI1/HIRQ1 PB4/XDB4 CHARGING 22
V00-V0A 55 68 KM_DATA 10 -SUSA
22 LEARNING P46/PW0 PB5/XDB5 -SUSA 4,6,9,11,16
(PWR_ON NA) -FAN 56 58 M_DATA
22 PWR_ON PWR_ON H8_PWRON P47/PW1 PB6/XDB6 T_DATA TSSOP14
14 57 T_DATA 15
-H8_RCIN P50/TXD0 PB7/XDB7 -RI

7
13 48 -RI 10
-H8_12V P51/RXD0 PA0/KEYIN8 -BATT_DEAD
12 47
KI0 P52/SCK0 PA1/KEYIN9 -H8_PME
26 31
P60/KEYIN0/FTCI PA2/KEYIN10
KI1 27 30 -ADEN
-ADEN 21 3 Q10
KI2 P61/KEYIN1/FTOA PA3/KEYIN11 H8_PWROK
28 21 R1 2 BATT_DEAD BATT_DEAD 21
KI3 P62/KEYIN2/FTIA PA4/KEYIN12 KM_CLK
29 20 1
KI4 P63/KEYIN3/FTIB PA5/KEYIN13 M_CLK DTC144TKA
32 11
KI5 P64/KEYIN4/FTIC PA6/KEYIN14 T_CLK
33
P65/KEYIN5/FTID PA7/KEYIN15
10 T_CLK 15 For H8-3434F Reflash 1 2
KI6 34 8 -H8_STBY
KI7 P66/KEYIN6/IRQ6 /STBY/FVPP -H8_SUSA R119
35
P67/KEYIN7/IRQ7 /NMI
7 V0A-V0B
Fan Control 1 -H8_RESET Signal HI LOW 0 (Add R119)
/RES VDD5 0603
2
VCC5 XTAL
3
EXTAL
/RESO
100 H8_12V Normal Flash

1
Close to SI2301DS R541
H8/F3437 PQFP100_0.5MM R547
1

C85 1 2
R60 10K +12V
0.1U H8 Mode Select Table 0603 D507 Q504 External Keyboard/Mouse
0603 470K 1M 0603 MMBT3906L
50V Q2 0603 MD0 MD1 MODE Description
2

2
X501 K A C E
SI2301DS F1 L1
1 2
S

1
R567
2

G C579 1 2 1 2
S G
16MHZ BAS32L 1K 0603 VCC5
0 1 MODE1 Expended mode with On-Chip ROM disable 0.1U

1
D

B
J12 C575 TXC8X4.5 C576 0603 1 2 MINISMDC110

1
1 0 MODE2 Expended mode with On-Chip ROM enable 50V 120Z/100M

2
68P 68P C1

1
2012
D

1 Signal HI LOW 0603 0603 1000P

1 1 MODE3 Single-Chip mode 5% 5% R142 0603
FAN

2
2
HIROSE 10K

2
3
ST/MA-3 -FAN FAN Off FAN On 0603 PS/2
DF13-3P-1.25V GND_PS2
Q14 VCC3 VDD5 FA1 J1

2
External Pull Up/Down
3 KM_CLK 1 8 1
-SCI VDD5 VDD5 R1 M_CLK 1
11 -SCI 2 2 7 2
2

1
Q15 1 KM_DATA 3 6 3
R145 M_DATA 3
Level Shift 3 RP31 4 5 4
4
R1 2 H8_SCI VDD5 VDD5 1 10 DTC144TKA 4.7K 5
-ADEN -RI 0603 5
V00-V0A 1 2 9 6
6
(Add 10K x 2) DTC144TKA H8_MODE0 3 8 -BATT_DEAD 120OHM/100MHZ
1

V0A-V0B H8_MODE1 -POWERBTN -H8_12V

2
4 7 GND1
GND1

4
3
2
1
(From 10K) R550 R551 5 6 -H8_PME GND2
10K 10K CP1 GND2
U505 0603 0603 47K*8 1206 For H8-3434F Reset 47PX4 MINI-DIN/6P
-EXTSMI 3 2 -H8_SMI RP517 1206 C10801-106XX
11 -EXTSMI PWROK 1A1 1B1 H8_PWROK KI0 VDD5 Modify by 12/15 '00
2

4,6,11 PWROK 4 5 1 10 U504

A20GATE 1A2 1B2 H8_A20GATE KI1 KI4 SOT23N
10 A20GATE 7 6 2 9 ADM809
-ROMCS 1A3 1B3 -H8_KBCS KI5
1 R643 2 0 0603 8 9 KI2 3 8 -H8_RESET 2 3
Level Shift

11,15 -ROMCS -SB_THRM 1A4 1B4 -H8_THRM KI6 9 -H8_RESET RESET# VCC
KI3

5
6
7
8
11 -SB_THRM 11 10 4 7
1A5 1B5

1
5 6 KI7 JL1

GND
-MCCS 1 R644 2 0 0603 14 15 -H8_MCCS R549 1 2
11 -MCCS -RCIN 2A1 2B1 -H8_RCIN 100K
10,11 -RCIN 17
2A2 2B2
16 V00-V0A 47K*8 1206
18 19 (From VCC5) 0603 SHORT-SMT3
-WAKE_UP 2A3 2B3 -H8_WAKE_UP Threshold : 4.38V GND_PS2

1
1
11 -WAKE_UP 21 20 1

-PME 2A4 2B4 -H8_PME VCC5 VDD5 BAT_CLK R118 1 2 10K

2
11,14,19 -PME 22 23
2A5 2B5 JS505 0603
R656 GND_PS2 16
1 24 1 2 BAT_DATA R120 1 2 10K
1OE# VCC 0603
21 -SW_VDD5 1 2 13 12
2OE# GND SHORT-SMT3 VCC5 VCC5
JO504
1

0_NA SN74CBTD3384 1 2
0603 R657 QSOP24A Close to 74CBTD3384DBQ RP518
V00-V0A 0 OPEN-SMT3 T_CLK 1 10 VDD3
1

New add 0603 C582 M_CLK 2 9 T_DATA

0.1U KM_CLK 3 8 M_DATA V0A-V0B
V0A-V0B 0603 -LID KM_DATA Add Q22,R255
2

4 7
NA Modify by 12/15 '00 50V After H8 off PWROK,then delay 150ms then H8(Pin14) o/p PWRON Low to OFF 3V D/D.
2

5 6
3
4.7K*8 1206 -H8_MVP4BT 2 R1 Q22
VDD3 ON then through R/C to generate -RSMRST. 1DTC144TKA
-RSMRST(SB I/P) -MVP4BT
-MVP4BT 11
Power switch ON. Power switch OFF

1
-POWERBTN(H8 I/P) R255
10K
H8(Pin 40) detect powebtn,then delay 100ms to o/p -MVP4BT pulse(1us) to SB.. 0603
-MVP4BT(H8 O/P)

2
SB received -mvp4sb, then o/p -SUSA-C. Into S1 Resume

-SUS[A-C](SB O/P)
H8's pin14 PWR_ON on VCC3/5 then Vcore/Vtt/Vcc25.
ALL POWER
H8 detect -SUSC,then delay 150ms then o/p PWROK. H8 OFF this pin before o/p PWRON low.. Title
Micro Controller
PWROK(H8 O/P)
Size Document Rev
C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 17 of 22
A B
 5 4 3 2 1

D
LSI80227 VCC3 VCC3_LAN
D

1
VCC3_LAN
R243 R244 L35
10K 10K 1 2
0603 0603

1
VCC3_LAN U25 C168 C167 C151 C138 C165
RP59 8 22*4 1206 1 LAN_MRXD0_2 120Z/100M

2
11 LAN_MRXD0 22 61 2.2U 2.2U 0.1U 0.1U 0.1U
LAN_MRXD1_2 RXD0 PLED0(MDA0) TP507 1608 1206 1206 0603 0603 0603
11 LAN_MRXD1 7 2 21 62 1
LAN_MRXD2_2 RXD1 PLED1(MDA1) TP515 16V 16V 50V 50V 50V

2
11 LAN_MRXD2 6 3 20 3 1
RP60 LAN_MRXD3_2 RXD2 PLED2(MDA2) TP516
11 LAN_MRXD3 5 4 19 4 1
ANEG RXD3 PLED3(MDA3) L26
8 1 9
DUPLX RP61 LAN_MRXDV_2 MDINT(MDA4)
7 2 11 LAN_MRXDV 1 22*4 1206 8 14 2 1 2
SPEED LAN_MRXER_2 RX_DV PLED4 VCC3_LAN
6 3 11 LAN_MRXER 2 7 18 63
MRXEN MRXEN LAN_MRXEN_2 RX_ER/R4D4 PLED5 120Z/100M
5 4 3 6 27
LAN_MRXC_2 RX_EN/JAM TXD+ 1608
11 LAN_MRXC 4 5 26 54
RX_CLK TPO+/FXI- TXD-
55
TPO-/FXI+

1
4.7K*4 LAN_MTXD0_2 35 C145 C154 C164 C166 C144 C140
1206 11 LAN_MTXD0 LAN_MTXD1_2 TXD0
36 58 RXIN+ L_AGND 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
11 LAN_MTXD1 LAN_MTXD2_2 TXD1 TPI+/FXO-
37 59 RXIN- 0603 0603 0603 0603 0603 0603
11 LAN_MTXD2 LAN_MTXD3_2 TXD2 TPI-/FXO+ 50V 50V 50V 50V 50V 50V
R97 0/NA 0603

2
11 LAN_MTXD3 38
TXD3 RPTR
24 1 2
RPTR
1 R235 2 22 0603 39 50 LAN_REXT 1 2
TX_ER/TXD4 REXT ANEG R237 0603 10K
11 LAN_MTXE 40 30
TX_EN ANEG
11 LAN_MTXC 1 R236 2 22 0603 34 29 DUPLX
TX_CLK DPLX
53 R100 0/NA 0603
SPEED SD/FXDIS
28 51 1 2
SPEED SD_THR
11 LAN_DCLK 10
MDC
11 LAN_DATAIO 11
MDIO
11 LAN_COL 1 R238 2 22 0603 12 56 VCC3_LAN
COL VDD1
11 LAN_CRS 1 R239 2 22 0603 13 57
CRS VDD2
7
VDD3
3 1 42 8
OSCIN VDD4
2 25
VDD5
4 44 32
25MHZ RESET VDD6
X2
1
NC0
5 52
NC1 GND1
15 60
NC2 GND2
16 6
NC3 GND3
17 41
C NC4 GND4 C

NC10
NC11
NC12
33 23

NC7
NC8
NC9
NC5 GND5
43 31
NC6 GND6
80227

45
46
47
48
49
64
6,9,10,12,14,19 -PCIRST PQFP64_0.5MM

V00-V0A
(From 80223)

RJ45
J11
1
PJ7 1
2
PJRX- 2
3
3
4
AVDD_LAN PJ4 4
5 GND1
PJRX+ 5 GND1
6 GND2
PJTX- 6 GND2
7 GND3
PJTX+ 7 GND3
8 GND4
8 GND4 VCC3 VCC5
Modify by 12/15 '00 J18
8PX1/1.016MM
1

C111 PJS-A8S0T MONO_OUT 1 2

13 MONO_OUT MODEM_SPK

Modem Dougther Board

R66 0.01U OCTRKCONN 3 4
Layout Note: 0_NA 0603 5 6
MODEM_SPK 13,19
0603
2

7 8

1
二四四四平平四四平長 VCC3
9 10 C593
2

11 12 0.1U
二四二二二二二, GND_45 13 14 R151 4.7K 0603
1

50V

2
C100 15 16 1 2
1

EX: GND SHIELDING 0.1U 17 18 0603

B 0603 R71 R70 19 20 CLOSE TO MDC B
50V 24.9 24.9 V00-V0A ACSYNC
2

S/W/W/S=12/6/6/12 mils 0603 0603 ACSDOUT

21 22
R570 1 MSDIN ACSYNC 11,13,19
1% 1%
(From 25ohm) 11,13,19 ACSDOUT 23 24 2 MSDIN 11,19
as short as possible L_AGND -ACRST 25 26
U3 11,13,19 -ACRST
CLOSE TO MDC 22 0603
2

27 28
RXIN+ R246 1 24.9 2 0603 1% 1 16 PJRX+ 29 30 R568 1 2 ACBITCLK
RD+ RX+ ACBITCLK 11,13,19

1
RXIN- R247 1 24.9 2 0603 1% 2 15 PJRX- C590
RD- RX- 22 0603
3 14 0.1U FM/0.8MM/H2.4
RDC RXC

1
0603 AMP C-179373

1
50V R684 R569

2
6 11 C592
TXD+ TDC TXC PJTX+ 0/NA 1K
7 10 10P_NA
TXD- TD+ TX+ PJTX- 0603 0603 0603
8
TD- TX-
9 MDC SCREW HOLE

2
1

JO6

2
4 12
NC0 NC2
1

C94 R64 R53 C88 C86 5 13 1 MDC_GND1 1 2

51 51 NC1 NC3 PJ4
22P_NA 22P_NA 0.1U
0603 0603 0603 0603 0603 MDC HARDWARE STRAP MTG1 SHORT-SMT3
H0013
50V PJ7 MDC HARDWARE STRAP ID2.8/OD5.0 JO502
2

XFMR_H0011-13
VCC3_LAN AVDD_LAN MDC W CRYSTAL MDC WO CRYSTAL MDC_GND2
2

1 1 2
L31 L22
V00-V0A LOW HIGH
(From H0011) MTG2 SHORT-SMT3
1

1 2 1 2 L_AGND PIN 16 AUDIO CODEC ON MOTHER BD AUDIO CODEC ON DAUGHTER BOARD R66 STUFF DON'T STUFF ID2.8/OD5.0
R24 R14 R7 R9 C66
1

C273 75 75 75 75 R26
120Z/100M 120Z/100M 0.1U U7 0603 0603 0603 0603 V00-V0A
1608 1608 0603 1% 1% 1% 1%
50V
7
TD+ TX+
10 (From 5%)
2

6 11
TDC TXC
8 9
TD1- TX-
1

C2
L_AGND 1 16 1000P
RD+ RX+ 1808
3 14
RDC RXC 2KV
2

2 15 10%
RD- RX-
DOUBLE CHECK POWER AND GND
PLANT 4 12
NC0 NC2
5 13
NC1 NC3
Modify by 12/15 '00
R686 LF-H80P L500
1 2 SOX16 GND_45
1 2
0 120Z/100M
0603 Note: Reserve fuse at PJRX+, PJTX+, PJ4 and PJ7 in LAN/ MDC 2012

1
A C626 A
Doughter board 1000P/NA
1808
L_AGND GND_45
3KV
RJ11

2
10%

1
J6 5 1 S500 J2
1 L8 Protector 1
1
2 3 2 2
50UH 1808A 2

2
GND1
ST/MA-2 CHOKE_WLT04020201 GND1
GND2
HIROSE GND2

2
DF13-2P-1.25V C102 1.016MM/H8.6
1000P/NA OCTEKCONN Title
1808 PJS-OXSXT LANPHY
L501 3KV

1
F500
1 2 1 2 10% Size Document Rev
120Z/100M 411669900014 0A
2012 Number
MINISMDC110 GND_RJ11
Date: Friday, May 04, 2001 Sheet 18 of 22

5 4 3 2 1
 5 4 3 2 1

D D

VCC3

1
C591 C597 C601 C228 C604 C596 C589 C609
2.2U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
1206 0603 0603 0603 0603 0603 0603 0603
16V 50V 50V 50V 50V 50V 50V 50V

2
VCC5
JS503
VCC3 SHORT-SMT3 VCC3

1 2
CBE[0..3]
6,10,14 -CBE[0..3]
AD[0..31]
6,10,14 AD[0..31]
J503
1 2
TIP RING
TOUCHPAD_10 TP543 1 TPJRX+ 3 4 TPJTX+ 1 TP542 TOUCHPAD_10
RX+ TX+
TOUCHPAD_10 TP539 1 TPJRX- 5 6 TPJTX- 1 TP541 TOUCHPAD_10
RX- TX-
TOUCHPAD_10 TP540 1 TPJ7 7 8 TPJ4 1 TP538 TOUCHPAD_10
PJ7 PJ4 VCC3
9 10
PJ8 PJ5
11 12
R579 LED1_GRNP LED2_YELP
13
LED1_GRNN LED2_YELN
14 V00-V0A
15
CHSGND RESERVED4
16 (Add VDD3 pull-high)
1 2 17 18 R176
10,14 -INTD INTB# 5V[1]

1
19
3.3V[0] INTA#
20 1 2 -INTC 10 V0A-V0B
0 21 22 0 R175 (Del R645)
0603 RESERVED0 RESERVED5 0603 10K_NA
23 24
C GROUND0 3.3VAUX[0] 0603 C
16 MINIPCICLK 25 26 -PCIRST 6,9,10,12,14,18
CLK RST#
27 28
GROUND1 3.3V[4]

2
6 -REQ3 29 30 -GNT3 6
REQ# GNT#

1
31 32
C606 AD31 3.3V[1] GROUND9
33 34 -PME 11,14,17
10P AD29 AD[31] PME#
35 36
0603 AD[29] RESERVED6 AD30
2 37 38
AD27 GROUND2 AD[30]
39 40
AD25 AD[27] 3.3V[5] AD28
41 42
AD[25] AD[28] AD26
43 44
-CBE3 RESERVED1 AD[26] AD24
45 46
AD23 C/BE[3]# AD[24] R575 1 100 AD17
47 48 2 0603
AD[23] IDSEL
49 50
AD21 GROUND3 GROUND10 AD22
51 52
AD19 AD[21] AD[22] AD20
53 54
AD[19] AD[20]
55 56 PAR 6,10,14
AD17 GROUND4 PAR AD18
57 58
-CBE2 AD[17] AD[18] AD16
59 60
C/BE[2]# AD[16]
6,10,14 -IRDY 61 62
IRDY# GROUND11
63 64 -FRAME 6,10,14
VCC3 3.3V[2] FRAME#
6,10,11,14 -PCLKRUN 65 66 -TRDY 6,10,14
CLKRUN# TRDY#
6,10,14 -SERR 67 68 -STOP 6,10,14
SERR# STOP#
69 70
R571 GROUND5 3.3V[6]
1 2 4.7K 0603 71 72 -DEVSEL 6,10,14
-CBE1 PERR# DEVSEL#
73 74
AD14 C/BE[1]# GROUND12 AD15
75 76
AD[14] AD[15] AD13
77 78
AD12 GROUND6 AD[13] AD11
79 80
AD10 AD[12] AD[11]
81 82
AD[10] GROUND13 AD9
83 84
AD8 GROUND7 AD[9] -CBE0
85 86
AD7 AD[8] C/BE[0]#
87 88
AD[7] 3.3V[7] AD6
89 90
AD5 3.3V[3] AD[6] AD4
91 92
AD[5] AD[4] AD2
93 94
AD3 RESERVED2 AD[2] AD0
95 96
AD[3] AD[0]
97 98
AD1 5V[0] RESERVED_WIP4[0]
99 100
AD[1] RESERVED_WIP4[1]
101 102
11,13,18 ACSYNC 103
GROUND8
AC_SYNC
GROUND14
M66EN
104 W/S=6/12 mils
1 2 R555 22 0603 105 106 AC97_SDOUT
11,18 MSDIN AC_SDATA_IN AC_SDATA_OUT ACSDOUT 11,13,18
B
11,13,18 ACBITCLK 1 2 R552 22 0603 107 108 B
AC_BIT_CLK AC_CODEC_ID0# AC97_RST
109 110 -ACRST 11,13,18
MODEM_SPK AC_CODEC_ID1# AC_RESET#
1 2 R542 0 0603 111 112
MOD_AUDIO_MON RESERVED7 R646
V00-V0A 113
AUDIO_GND0 GROUND15
114
(From MONO_OUT) 115 116 1 2 MODEM_SPK
SYS_AUDIO_OUT SYS_AUDIO_IN MODEM_SPK 13,18
117 118 0
SYS_AUDIO_OUT_GND SYS_AUDIO_IN_GND
1

119 120 0603

C577 AUDIO_GND1 AUDIO_GND2
121 122 -MPCIACT 11
10P RESERVED3 MPCIACT#
123 124
0603 VCC5VA 3.3VAUX[1]
2

GND1
GND1
GND2
GND2
124P/0.8MM/H5.2
QTC
CA-5.2-016-124-SVN323

A A

Title
LANPHY

Size Document Rev

411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 19 of 22
5 4 3 2 1
 A B C D E

CPU Core POWER

PL13 2012
120Z/100M
1 2 C1
4 4
DVMAIN
21,22 DVMAIN

1
PL14
PC10

1
1 2 0.01U PC503 PC504 + PC8 PC506 PC507 + PC9
120Z/100M 0603 10U 10U 100U 0.1U 0.1U 100U
2012 1812 1812 25V 0603 0603 25V

2
25V 25V 50V 50V

2
20% 20%

PR511 0 0603 VCC_CORE

DVCC5D 1 2 PL8
PR508 DVCC5T
1 2
22 C1
PC509 0603 SHORT-SMT4

1
1 2 1 2 PL9

1
5VALWAYS PD502 PC513 1 2
0.22U 1U

15
MA3X701

5
6
7
8

5
6
7
8

5
6
7
8
PU504 0603 SHORT-SMT4
PU2 PU503 PU501 PL10

2
17 1 D D D

VCC

VDD
PR516 0_NA 0603 D4 V+ IR7811A IR7811A IR7811A PD1

3
1 2 18 1 2
PR519 0_NA 0603 D3 G SO8 G SO8 G SO8
1 2 19 1
D2

1
PR515 1 0_NA 2 0603 20 22 PC514 4 4 4 3 SHORT-SMT4
PR514 0_NA 0603 D1 BST PL11
1 2 21 0.22U 2
D0 0603 1 2
PR512 10K 20603 16V S S S BAW56

2
1 16 24
A/B DH SHORT-SMT4
1

DVCC5T PL1 PR15 .005 2512 1% PL12

1
2
3

1
2
3

1
2
3
PR513 C2
1

23 1 2 1 2 1 2
PR520 100K PR506 10K LX
1 20603 2 0.6UH
10K 0603 SKP/SDN ETQP6F SHORT-SMT4

K
5
6
7
8

5
6
7
8

5
6
7
8

1
0603 14 30% PR16 PC1 PC2 PC3 PC5 PC512 PC500

K
DL
1

1
PR507 100K 0603 1% PU500 PU502 PU1 + 150U + 150U + 150U + 150U_NA PD7 + +
2

D D D 1 2 PC7 PC4 82U 82U

PR503 1 2 3 PC515 SI4404 SI4404 SI4404 PD501 PD500 PC6 7343 7343 7343 7343 4.7U 0.1U EC31QS03L 7343 7343
2

100K TIME 0.1U G SO8 G SO8 G SO8 EC31QS03L 2.5V 2.5V 2.5V 2.5V 1206 0603 2.5V 2.5V
13
0603 PC508 220P GND .005 0.1U 20% 20% 20% 20% 16V 50V

2
4 4 4 50V
2512

A
1 2 6 4 0603
3 CC FB 1% 3

A
PGND
2

DVCC5T PC510 0.22U S S S EC31QS03L_NA

1 2 9 5
REF FBS C6

1
2
3

1
2
3

1
2
3
PR505

DVCC5D 8 11 1 2
RP503 TON GNDS
PR509 1K R507 1K 0603 1%
4 PVID3 1 8
2 7 1 2 10 12 1 TP558 1 2 H1
4 PVID2 ILIM VGATE
4 PVID1 3 6
1

1
4 PVID0 4 5 MAX1717
8.06K PR510 QSOP24A PR504
0603 47.5K 169K
10K*4 1% 0603 0603
1206 1% 1%
2

2
H2

DVMAN
2 21,22 DVMAIN 2
DVCC3T

1
PC12

1
PC536 PC535 + 100U
0.1U 25V
1

PC18 PC17 0.01U 50V

Check PQ1
4

0603 0603

2
0.1U 4.7U
1

0603 1206 PQ1

PR2 50V 16V MTD20N03HDL
2

1
10 DPAK PL500
0603 F5
3

1 2
VCC2.5
K
1

DVCC5T SHORT-SMT4
2

PU4 +
1 20 PR521 PC519 PC521
PR517 SYNC PSAVE 20K 0.1U 56U PD503
0603 50V 7343 RLZ2.7B
2

1 2 2 19
SHDN RESET
A

1% 0603 4V
2

3 18
10K FB ENABLEIO
0603 4 17
VDD1 IOS
1

5 16
GND GATEIG PU3
8

PR518
6 15 18.7K D1
CSL VDD2 0603 PL3 VTT
7 14 1% 120Z/100M
CSH BST PL2 2012
2

1
DVCC5T 8 13 D2 5 PR1
V5V DH G1
6 F1 1 2 F2 1 2 F3 1 2F4
9 12 7
DL PHASE
1

1
PC516 PC518

1
0.1U 4.7U 10 11 2.2UH .02 + PC11 PC16 PC511
PGND0 PGND1
1

0603 1206 PC517 SS1005-2R2NSB 2512 PR558 150U 0.1U + 82U_NA

50V 16V 1% 10K 7343 0603 7343
2

SC1401CSS 0.1U 4
SSOP20 0603 0603 2.5V 50V 2.5V

2
G2
50V 1% 20%
2

2
S2 A

2
SI4816DY
2
3

SO8

1
PD2
1 A K PR557 1
47.5K
0603
BAS32L 2 1%

I1

I2

Title
CPU CORE (MAX1717)& VTT(SC1401)

Size Document Rev

C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 20 of 22
A B C D E
 A B C D E

VDD5S

DVMAIN PU5
20,22 DVMAIN
SI4835DY
SO8
8

1
7 3
VDD5S PR548 PR555 22 DBATT DBATT 6 2
475K 100K DVMAIN 20,22
5 1
0603 0603

S
8
1%

G
2

2
3 +
BATT_DEAD PR6

4
1 BATT_DEAD 17
2 - 1 2
PU509A

1
VDD5 100K
4 4

1
PR550 PR556 LMV393M 0603

4
402K PR554 324K SSOP8 PR525
0603 100K 0603 10K

1
1% 0603 1% 0603
PR527
2

D2
PU509B

1
100K

2
1
5 D PQ508 PR553 PC533 0603

D
+ 2N7002 100K
7 G S 0.1U
BAT_T 0603 0603 PQ502

2
6 - D
1% 50V -ADEN 2N7002

S
17 BAT_T

2
17 -ADEN G S

2
1

LMV393M

S
4
PR549 SSOP8

3
100K
0603 PR524
1% 22 ADINP 1 2 2 PQ503
2

DTC144WK
169K
0603
1%
PL7

1
1 2

120Z/100M 2012

PF1 PL6
1 2 1 2
J16

1
6.5A/32VDC 120Z/100M 2012 PR13 1
1

1
PR552 PC24 2
301K 2
0.1U 1 2 3
0603 0603 3
4
1% 50V 4

2
5
0 5

2
6
17 BAT_V BAT_V 0603 6
6P/2.5MM/H4
CEN

1
SB-06A-4.0-A2

1
PC534 PR551
3 100K VDD5S 17 BAT_C BAT_C 3
0.1U
0603 0603
50V 1%

1
PR547

2
1 2 PR11 17 BAT_D BAT_D 22 BATT_GND
4.99K Don't Stuff
VDD5S 1M 0603
0603 1%
1% 17 BAT_T BAT_T

1
PC27 PC28 PC25 PC29

1
47P_NA 47P_NA 0.01U 1000P

1
PR12 PC30 PC26 0603 0603 0603 0603
20K

2
1000P 0.1U
1

PR545 0603 0603 0603

PR544 12.1k 1% 50V

2
4.7K 0603

2
0603 1%
8

8
2

1 2 3 + 5 +
1 -LI_OVP 7 Modify by 12/15 '00
-LI_OVP 22
1 2 2 - 6 - Modify by 12/15 '00
PU507A PU507B
PR536
2

402K LMV393M LMV393M

4

4
SSOP8 SSOP8
1

PQ507 0603 PR535 PC532

1 1% 43.2K 0.1U
SCK431LCSK-5 0603 0603
SOT23N 1% 50V
2
3

DBATT
22 DBATT

2 2
VDD5
1

PR9
470K
0603

PQ6
2

PQ4 VDD5 VDD5S

-SW_VDD5 17
3

S
D
DTC144WK S D

2 G

G
PR10 SI2301DS
100K
0603
1

2
PD6
A K -ADEN
-ADEN 17
3V Resume Power BAS32L
VDD5 VCC3
VCC3 VDD3 SOT89N
JO15 TC55RP3302EMB 3 PQ5
R1 2
1 2 3 2 1
VOUT VIN
1
GND
1

OPEN-SMT4 PC22 DTC144TKA

1

C24 U4 0.1U
2.2U 0603
0805 50V
2

+80-20% VCC5
2

PL5
1 120Z/100M 1
1608
JS4 PU6 G PQ3
G

22 ALWAYS 1 2 8 6
IN 5VTAP
2

2 1 S D
SHORT-SMT4 SENSE OUT
S
D

7 5
SW_VDD5 F/B ERR-
17 SW_VDD5 3 4
SHUTDN GND
1

LP2951-02BM PC19 PC20

SO8 0.1U 10U SI2301DS
0603 1206
50V 10V
2

5V Resume Power
Title
BATTERY CONNECTOR

Size Document Rev

C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 21 of 22
A B C D E
 A B C D E

ADINP
21 ADINP

PU505
SI4835DY
SO8 PU508

4
8 SI4925DY
4 VBATT VADJ2 VADJ1 3 7 SO8
4
PL4 PD5
2 6 6 3
L5 L6 L7 PR546 PR543
1 5 1 2 A K 5 PQ506

D
S
12.30V 0 0 1 2 1 2

D
1

G
EC31QS03L 2N7002

K
PR7 PR8 33UH 8 D
10K 10K PD4 100K 10K -LI_OVP

4
7 1 S G

1
0603 0603 0603 0603
12.45V 0 1 EC31QS03L PC21

S
+ 100U PC522 PC531

1
2

2
C 25V 0.1U 0.1U_NA

A
PQ2 PR5 0603 0603

2
B
50V 50V

2
12.60V 1 0 E 100K
MMBT2222A 0603 DBATT
DBATT 21

2
12.75V 1 1
PD3

1
K A PR540 PR542
11.8K 1M_NA
0603 0603
BAS32L 1% 1%

1
MLL34B PC23

2
10U
2IN+ 1812
25V

2
20%

1
PR522

1
10K PR538 PR539
0603 PR541 453K 210K
PR523 E 8.06K 0603 0603
PQ500 0603 1% 1%
2

1 2 B

2
C
33K MMBT3906L 1%

2
PQ505A
0603

4
NDC7002N
D

PU506
PWM
1

D PC525 PQ504A
-LI_OVP G S 0.1U 9 8 3 VADJ1
E1 C1 VADJ1 17

4
3 21 -LI_OVP PQ501 0603 PC528 0.01U_NA 3
10 7 NDC7002N
E2 GND

1
50V
S

2N7002
2

11 6
C2 RT PR532 PR533 PR537

2
12 5 PQ505B
VCC CT 121K 1K 1K
13 4 3
OUTPUTCTRL DTC
1

6
14 3 1 2 0603 0603 0603
REF FEEDBACK 1% NDC7002N
PR526 15 2 L9 1% 1%
47K 2IN- 1IN- L10

2
16 1
0603 2IN+ 1IN+ VADJ2
1 VADJ2 17

1
BATT_GND 21
TL594C SO16 PR530
2

PQ504B
6.19K

5
PC530

6
PR534 0603
NDC7002N

1
1 2 1 2 PC523 PR528 PC524 PR529 1% PR14
100K 10K

2
1U 1000P
0 0603 0603 0603 0603 .02 PWR_ON
2512 1 PWR_ON 17
1

1
0603 0.01U 10% 1%

2
PC529 PC526 1%
PR531 0603

1
JS502 0.1U 0.1U
CHARGING DCHARGING 10K 0603 0603

5
1 2
17 CHARGING 0603 50V 50V
2

2
SHORT-SMT1
2

PC527
0.1U
2

50V
0603

2 2

P_LPD0 8 1 DP_LPD0
10 P_LPD0 P_LPD1 7 2 DP_LPD1
10 P_LPD1 P_LPD2 6 3 DP_LPD2
10 P_LPD2 P_LPD3 5 4 DP_LPD3
10 P_LPD3 P_LPD4 8 1 DP_LPD4
10 P_LPD4 P_LPD5 J10 DVCC5T
7 2 DP_LPD5
10 P_LPD5 P_LPD6 FIRSEL DP_LPD0 J7
6 3 DP_LPD6 44 43
10 P_LPD6 P_LPD7 10 FIRSEL -SUSC 44 43 DP_LPD1
5 4 DP_LPD7 42 41 1 2
10 P_LPD7 P_SLCT 11,17 -SUSC IRRX 42 41 DP_LPD2
8 1 DP_SLCT 40 39 3 4
10 P_SLCT -P_STB 10 IRRX IRTX 40 39 DP_LPD3 VCC5 DVCC3T
7 2 -DP_STB 38 37 5 6
10 -P_STB -P_AFD -DP_AFD 10 IRTX -DP_ACK 38 37 DP_LPD4
10 -P_AFD 6 3 36 35 7 8
-P_ERR -DP_ERR DP_BUSY 36 35 DP_LPD5
10 -P_ERR 5 4 34 33 9 10
-P_INIT -DP_INIT DP_PE 34 33 DP_LPD6
10 -P_INIT 1 8 32 31 VCC3 11 12 ADINP 21
-P_SLIN -DP_SLIN RP2 -DCOM1RTS 32 31 DP_LPD7
10 -P_SLIN 2 7 30 29 13 14
-P_ACK -DP_ACK 0*4 DCOM1TXD 30 29 DP_SLCT
10 -P_ACK 3 6 28 27 15 16
P_BUSY DP_BUSY 1206 -DCOM1DTR 28 27 -DP_STB
10 P_BUSY 4 5 26 25 20,21 DVMAIN 17 18
P_PE DP_PE R673 1 0 0603 -DCOM1CTS 26 25 -DP_AFD DVMAIN 20,21
10 P_PE 8 1 9 CSYNC 2 24 23 19 20
-COM1RTS -DCOM1RTS R674 1 0 0603 DCOM1RXD 24 23 -DP_ERR
10 -COM1RTS 7 2 9 TV_CRMA 2 22 21
22 21

1
COM1TXD 6 3 DCOM1TXD RP521 R675 1 2 0 0603 -DCOM1DCD 20 19 -DP_INIT C500 C27 C37 HDR/10PX2/H8.4
10 COM1TXD 9 TV_LUMA 20 19

1
-COM1DTR 5 4 -DCOM1DTR 0*4 R676 1 2 0 0603 -DCOM1DSR 18 17 -DP_SLIN 0.1U 0.1U 0.1U PH/PS-D-RA-44-X-X C36 C535 C504 C502
10 -COM1DTR -COM1CTS -DCOM1CTS 9 TV_COMP -DCOM1RI 18 17 -AC_POWER
8 1 1206 16 15 0603 0603 0603 CEN 0.1U 0.1U 0.1U 0.1U
10 -COM1CTS COM1RXD DCOM1RXD -RS232_OFF 16 15 -BATT_LED -AC_POWER 9 50V 50V 50V 0603 0603 0603 0603

2
10 COM1RXD 7 2 11 -RS232_OFF 14 13 -BATT_LED 9
-COM1DCD -DCOM1DCD RP522 14 13 -BATT_G 50V 50V 50V 50V

2
10 -COM1DCD 6 3 12 11 -BATT_G 9
-COM1DSR -DCOM1DSR 0*4/NA +12V 12 11 -BATT_R
10 -COM1DSR 5 4 10 9 -BATT_R 9
-COM1RI -DCOM1RI 1206 VDD5S BLADJ 10 9 ENPBLT
10 -COM1RI 1 2 8 7 ENPBLT 6
17 BLADJ 8 7 PWR_ON
6 5 PWR_ON 17
R12 5VALWAYS 6 5 LEARNING
1 4 3 LEARNING 17
4 3
4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

0 TP500 2 1 ALWAYS
0603 2 1 ALWAYS 21
1

C15
22P FM/22PX2/1.27
0603 B06P-0110-441
5% SPEED
2

1 1
5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8

CP503 CP504 CP506 CP2 CP507 CP508

22P*4 22P*4 22P*4 22P*4 22P*4 22P*4/NA
1206 1206 1206 1206 1206 1206

Title
Battery CHARGER

Size Document Rev

C 411669900014 0A
Number
Date: Friday, May 04, 2001 Sheet 22 of 22

A B C D E
 5 4 3 2 1

SYSTEM POWER (5V 3V 12V)

D D

PL7
BEAD
0805C

1 2
PR504
2 DVMAIN DVMAIN D2 1 2

1 2 PR518 0/NA 0603 10 0603

1
PC9 2 -SUSC 1 2 PC512
PC8
PL8 + 100U 0.1U 0.1U
BEAD 25V 0603 0603
0805C 50V 2 PWR_ON 50V

2
1 2
PU2

2
SI4800DY PR519 0 0603
DVCC3T SO8
PR503

4
1 2

1
5 1 0_NA

S
D
1

6 2 PC525 PR515 PR516 0603

PL502 7 3 0.1U 1K 1K
C 50V 0603 0603 C

2
BEAD 8
VCC3 0805C 0603

1
PL10 PR2 PL1 PR517
2

A4 1 2 1 2 A2 1 2 A1 1M
0603

1
BEAD 0805C PU4
1

PR505 .02 ETQP_CDRH125 SI4832DY

2
PC12

4
100P 32.4K 2512 SO8 PU501
PL9 0603 0603 1% PC511
1 28

G
CSH3 RUN/ON3
1

PC514 PC513 PC515 1% 0.1U

2

1 2 5 1

S
D
1

+ 100U/H2.8 + 100U/H2.8 0.1U FB3 50V

2

6 2 2 27
BEAD 0805C 7343 7343 0603 CSL3 DH3 0603
7 3
10V 10V 50V 8 FB3 3 26 2 1
FB3 LX3
1

PL501
2

PC21 PC22
1

4.7U 0.1U PC15 PR506 +12V 1 2 4 25

12OUT BST3

1
1206 0603 1000P 100K
PC4

1
16V 50V 0603 0603 BEAD PC504 + 100U +RAW_15V
2

5 24
1% I3 0805C 0.1U VDD DL3 JS2
2

25V
50V
2

6 23 1 2 5VALWAYS
A5 I4 0603 SYNC SHDN

2
PD503 SHORT-SMT3
7 22
TIME/ON5 V+
1
PD501 FB3 1 2 8 21 3
GND VL

1
A K +RAW_15V 2 PC20 PC19
PR513 0_NA 9 20 0.1U 4.7U
0603 PR514 REF PGND 0603 1206
1

EC11FS2 PC24 FB5 BAW56 50V 16V

2
PC5 1 2 1 2 10 19
DC2010 + 100U 0.1U SKIP DL5
25V 0603 PR508 0_NA 0 11 18
DVCC5T 50V 0603 RESET BST5
1

4
JS1 0603 FB512
2

PC10 17 2 1
FB5 LX5
1 2 BKL_VMAIN + 100U

G
BKL_VMAIN 2 PC510
5 1 13 16

S
25V

D
SHORT-SMT3 CSL5 DH5 0.1U
2
6 2
1

50V
2

7 3 14 15
PL4 CSH5 SEQ 0603
8

1
MAX1632 SSOP28A
VCC5 BEAD
0805C
PT1 PR509
PU1
B 2 4 SI4800DY 0_NA B
PL6 SO8 0603
2

B3

2
1 2 1 2 1 3
1

PR1 10UH

1
BEAD PR502 .02 IND_CDRH125B PC508
0805C 100K 2512 1U
G
PL5 0603 1% 5 1 0603

S
D
1%

2
1 2 6 2
2

7 3
1

PC505 PC506 PC7 FB5 8

1

BEAD + 100U/H2.8 + 100U/H2.8 0.1U

1

PC6 0805C 7343 7343 50V

4.7U PC14 10V 10V 0603 PR501
1206 97.6K PU3
2

16V 0.1U 0603 SI4832DY

2

50V
1% SO8
0603
2

I5

I6

A A

Title
SYSTEM POWER

Size Document Rev

Custom 411669900004 0B
Number
Date: Wednesday, May 02, 2001 Sheet 1 of 3
5 4 3 2 1
 5 4 3 2 1

JO502
D 1 2 D
PD505 OPEN-SMT4
2 JO501
ALWAYS 3 1 2
1
OPEN-SMT4

BAV70LT1 PQ1
SI4835DY
SO8
8
3 7
2 6
L4 1 5 ADINP ADINP

D
S
2

1
PR5 ENPBLT1 C3 C2
470K 0.1U_NA

4
0.1U
0603 PD2 50V 0603
PR3 DVMAIN 0603 50V
Note : BKL_VMAIN is Power Trace

2
A K DVMAIN 1

1
1 2

1
EC31QS03L ENPBLT1 L6 1 2 BEAD
PC11

1
PR6 D + 100U PR7 0603B J3
PC23
1 2 G S 470K 25V 1000P 10K PD1 1 BKL_VMAIN BKL_VMAIN L5 1 2 BEAD 1
LEARNING
1

1
0603 0603 0603 A K PC13 PC17 0805C 2
HIROSE

Inverter
S
PR507 BLADJ BLADJ L4 BEAD

2
0.1U 1000P 1 2 3
47K 100K PQ501 0603 0603 0603B

2
EC31QS03L 4 ST/MA-10
0603 0603 2N7002 50V

2
PD504 5 DF13-10P-1.25V
SOT23_FET 1 -AC_POWER 8 1 FA1 6
-BATT_LED
2

3 ALWAYS 7 2 7
PL503 120Z/100M 2012 2 -BATT_G 6 3 8
1 2 -BATT_R 5 4 9
BAV70LT1 120OHM/100MHZ 10
L3 1 2 BEAD
J4 PL504 PF501 VDD5S 0805C
1 L1 1 2 L3 1 2

1
2 C1

K
1
3 6.5A/32VDC 0.1U
1

1
JACK-3P/D20/H7W95 PC507 PC501 PC509 PC502 PC3120Z/100M PC503 PR4 0603
0.1U2012 10K 50V

2
IDJ-D22-6T 1U 0.1U 0.1U 0.1U 0.1U
0805 0603 0603 0603 0603 0603 0603
C 25V 50V 50V 50V 50V 50V C
2

A
PD502

2
RLZ24D

B PJ2 B
FIRSEL 44 43 P_LPD0
3 FIRSEL 44 43 P_LPD1 P_LPD0 3
1 -SUSC 42 41 P_LPD1 3
IRRX 42 41 P_LPD2
3 IRRX 40 39 P_LPD2 3
IRTX 40 39 P_LPD3
3 IRTX 38 37 P_LPD3 3
-P_ACK 38 37 P_LPD4
3 -P_ACK 36 35 P_LPD4 3
P_BUSY 36 35 P_LPD5 PJ1
3 P_BUSY 34 33 P_LPD5 3
P_PE 34 33 P_LPD6
3 P_PE 32 31 P_LPD6 3 1 2
32 31 P_LPD7
30 29 P_LPD7 3 VCC5 3 4 DVCC3T
30 29 P_SLCT
28 27 P_SLCT 3 5 6
28 27 -P_STB
26 25 -P_STB 3 DVCC5T 7 8
26 25 -P_AFD
3 CSYNC 24 23 -P_AFD 3 9 10
24 23 -P_ERR
3 TV_CRMA 22 21 -P_ERR 3 VCC3 11 12 ADINP
22 21 -P_INIT
3 TV_LUMA 20 19 -P_INIT 3 13 14
20 19 -P_SLIN
3 TV_COMP 18 17 -P_SLIN 3 15 16
18 17 -AC_POWER
16 15 -AC_POWER 1 DVMAIN 17 18
-RS232_OFF 16 15 -BATT_LED DVMAIN 1
3 -RS232_OFF 14 13 -BATT_LED 19 20
14 13 -BATT_G
12 11 -BATT_G
+12V 12 11 -BATT_R
10 9 -BATT_R HDR/10PX2/H8.49
VDD5S BLADJ 10 9 ENPBLT1
BLADJ 8 7 ENPBLT1 PH-D-RA-44-X-X
8 7 PWR_ON
6 5 PWR_ON 1 CEN
TP501 5VALWAYS 6 5 LEARNING
1 4 3 LEARNING
4 3 ALWAYS
2 1
2 1 ALWAYS

MA/22PX2/1.27
SPEED
G442-8701-441

A A

Title
DC POWER

Size Document Rev

Custom 411669900004 0B
Number
Date: Wednesday, May 02, 2001 Sheet 2 of 3
5 4 3 2 1
 5 4 3 2 1

D D

TV OUT
J5 L503 L501
1 120Z/100M 120Z/100M
1 CSYNC 2
2 1608 1608 VCC3
2 TV_COMP 2
3 1 2 1 2 TV_LUMA
3 TV_LUMA 2
4 1 2 1 2 TV_CRMA
4 TV_CRMA 2
GND1 L504 L502
GND1 120Z/100M 120Z/100M
GND2
GND2

1
1608 1608

4
3
2
1
C10801-10405 C510 C511 R501 R504

1
MINI-DIN/4P C512 C513 100P 100P RP505 100K 10K
100P 100P 0603 0603 75*4/NA 0603 0603
0603 0603 10% 10% 1206

2
10% 10% IRMODE0

2
L505
1 2

5
6
7
8
3
Q501 R1 2
DTC144TKA1 -RS232_OFF 2
JP_BEAD_DFS
GND_TV

L1
C C
1 2

120Z/100M
2012

GND_IO2

MTG2
MTG1 ID2.8/OD7.6
ID2.8/OD6.0
3
2
1

4 12
1

5 11
6 10

VCC5
7
8
9

A
FD1 FD2 FD3 FD4
FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK D1
BAS32L
MTG3 MTG4

K
ID2.8/OD7.6 ID2.8/OD7.6 U501
1

12 13

11 14
3
2
1

3
2
1

0*4 RP501
4 12 4 12 FD501 FD502 FD504 FD503 -P_STB 8 1 -PP_STB 10 15
2 -P_STB -PP_AFD
5 11 5 11 FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK -P_AFD 7 2
2 -P_AFD PP_LPD0
6 10 6 10 P_LPD0 6 3 9 16
2 P_LPD0 -PP_ERR
-P_ERR 5 4
2 -P_ERR
8 17
1206
7
8
9

7
8
9

7 18
0*4 RP502 J1
B P_LPD1 8 1 PP_LPD1 6 19 B
2 P_LPD1 -PP_INIT
-P_INIT 7 2 26
2 -P_INIT PP_LPD2
P_LPD2 6 3 5 20
2 P_LPD2 -PP_SLIN
-P_SLIN 5 4 STB# 1
2 -P_SLIN
4 21 AFD# 14
1206 R503 LPD0 2

Parallel Port Connector

P_LPD3 1 2 PP_LPD3 3 22 ERR# 15
2 P_LPD3
2 23 LPD1 3
FIR Module 0 0603 1 24 INIT# 16
LPD2 4
VCC3_IR SLIN# 17
U1 FIR PAC128401Q LPD3 5
1 QSOP24A 18
VCC LPD4
2 6
FIRSEL AGND
2 FIRSEL 3 19
IRMODE0 FIR_SEL LPD5
4 7
MD0
5 20
VCC3 VCC3_IR MD1 LPD6
6 8
NC
7 21
2 IRRX IRRX GND LPD7
8 9
JL501 R502 2.7 2 IRTX IRTX RXD U502
9 22
TXD ACK#
1 2 1 2 10 12 13 10
LEDA
23
SHORT-SMT4 2010 1% 11 11 14 BUSY 11
GND1
1

C508 C509 0*4 RP503 24

10U_NA 0.1U HSDL-3600 P_LPD4 8 1 PP_LPD4 10 15 PE 12
2 P_LPD4 PP_LPD5
1206 0603 P_LPD5 7 2 25
50V 2 P_LPD5 PP_LPD6
JL502 16V P_LPD6 SLCT
2

2 P_LPD6 6 3 9 16 13
1 2 P_LPD7 5 4 PP_LPD7
2 P_LPD7
8 17 27
SHORT-SMT4 1206
GND_FIR 7 18 PIO
0*4 RP504 GND_IO2 7536S-25G2T GND_IO2
-P_ACK 8 1 -PP_ACK 6 19 SUYIN
2 -P_ACK PP_BUSY
IR Mode Select P_BUSY 7 2
2 P_BUSY PP_PE
P_PE 6 3 5 20
2 P_PE PP_SLCT
P_SLCT 5 4
2 P_SLCT
4 21
1206
IR Mode Select 3 22
2 23
A IRMODE0 IRMODE1 FIRSEL RX Function TX Function 1 24 A

HI LOW X Shutdown Shutdown PAC128401Q

QSOP24A
LOW LOW LOW Full Distance Power GND_IO2 GND_IO2
LOW HI LOW SIR 2/3 Distance Power
HI HI LOW SIR 1/3 Distance Power

LOW LOW HI MIR/FIR Full Distance Power

LOW HI HI MIR/FIR 2/3 Distance Power Title
DC POWER
HI HI HI MIR/FIR 1/3 Distance Power
Size Document Rev
Custom 411669900004 0B
Number
Date: Wednesday, May 02, 2001 Sheet 3 of 3
5 4 3 2 1
 5 4 3 2 1

D D

7170 ESB

EASY START BTN CONNECTOR SW1

KO0 1 3 KI4 SW6
J501 2 4 -PWRSW 1 3
C KO1 1 2 KI1 2 4 C
KO0 3 4 KI2 SMT1-03
-PWRSW 5 6 KI3 SMT1-03
7 8 KI4
9 10
SW2
SPEED KO1 1 3 KI1
S200-0100-101 2 4
HDR/FM/1.27/5PX2
GND GND SMT1-03

SW3
1 3 KI2
2 4

SMT1-03

8
MTG2
SW4 MTG1 2 7 MTG/ID3.75/OD7
1 3 KI3 ID2.2/OD6.0
2 4
3 6
SMT1-03

5
SW5 GND
1 3 KI4
2 4
GND
SMT1-03

B B

FD501 FD502
FIDUCIAL-MARK FIDUCIAL-MARK
1

FD3 FD4
FIDUCIAL-MARK FIDUCIAL-MARK
1

A A

Title
7170 EASY START BOARD

Size Document Rev

C 411669900007 00
Number
Date: Wednesday, April 04, 2001 Sheet 1 of 1
5 4 3 2 1
 5 4 3 2 1

D D

7170 TOUCH PAD BOARD

VCC5
MTG1 MTG2
MTG/ID2.2/OD5.6 MTG/ID2.2/OD5.6

8
1 J502
2 7 2 7 TP_DATA 2
TP_CLK 3 HIROSE
4 ST/MA-4
3 6 3 6
DF13-4P-1.25V

5
VCC5
GND
J501
C GND GND C
GND2
GND1
MTG3 MTG4 SW3
MTG/ID2.2/OD5.6 MTG/ID2.2/OD5.6 8 1 3
7 TP_DATA 2 4
6
5
TP_CLK
TP_RIGHT SMT1-03
RIGHT
1

8
4 TP_LEFT
2 7 2 7 3 SW2
2 SCRL_UP 1 3
1 SCRL_DOWN 2 4
3 6 3 6
SMT1-03
LEFT
ACES
88206-0800
4

5
SW1
HDR/MA-8 GND 1 3
2 4 SCRL UP
SMT1-03
GND GND
SW4
1 3
2 4 SCRL DOWN
SMT1-03

GND
FD1 FD3 FD2 FD4
FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
1

B B

FD501 FD504 FD502 FD503

FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
1

A A

Title
7170 T/P

Size Document Rev

C 411669900006 0B
Number
Date: Monday, May 07, 2001 Sheet 1 of 1
5 4 3 2 1
SERVICE
SERVICE MANUAL
MANUAL &
& TROUBLESHOOTING
TROUBLESHOOTING GUIDE
GUIDE FOR
FOR
7170
7170

Sponsoring Editor : Shoestring Tsai

Author : Richard.Wang

Assistant Editor : Kelly Chiang

Publisher : MITAC INTERNATIONAL CORP.

Address : 4F, NO.18, PU-DING ROAD, HSINCHU, TAIWAN, R.O.C.

TEL : 886-3- 5645850 Fax : 886-3- 5781245

First Edition : Jul. 2001

E-mail : Jesse.Jan @ mic.com.tw