17/06/2020 ASIC-System on Chip-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

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To meet the design challenge of clock distribution, the timing analysis is
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gets stable. Timing Analysis (TA) is a design automation program which
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provides an alternative to the hardware debugging of timing problems. The m
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Static vs. Dynamic Timing Analysis

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Timing analysis can be static or dynamic.

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Static Timing Analysis (STA) works with timing models where as the Dynamic
Backend (Physica
Timing Analysis (DTA) works with spice models. STA has more pessimism Design) Interview
and thus gives maximum delay of the design. DTA overcomes this difficulty Questions and
because it performs full timing simulation. The problem associated with DTA Answers
is the computational complexity involved in finding the input pattern(s) that
Process-Voltage-
produces maximum delay at the output and hence it is slow. The static timing Temperature (PV
analyzer will report the following delays: Register to Register delays, Setup Variations and
times of all external synchronous inputs, Clock to Output delays, Pin to Pin Static Timing
combinational delays. The clock to output delay is usually just reported as Analysis
simply another pin-to-pin combinational delay. Timing analysis reports are
Clock Gating
often pessimistic since they use worst case conditions.
What is the
The wide spread use of STA can be attributed to several factors [2]: difference betwee
FPGA and ASIC?
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17/06/2020 ASIC-System on Chip-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

The basic STA algorithm is linear in runtime with circuit size, allowing analysis Embedded Syste
for Automatic
of designs in excess of 10 million instances.
Washing Machine
using Microchip
The basic STA analysis is conservative in the sense that it will over-estimate PIC18F Series
the delay of long paths in the circuit and under-estimate the delay of short Microcontroller
paths in the circuit. This makes the analysis ”safe”, guaranteeing that the
design will function at least as fast as predicted and will not suffer from hold- READ MORE
time violations.
ASIC
The STA algorithms have become fairly mature, addressing critical timing synthesis (38
issues such as interconnect analysis, accurate delay modeling, false or multi- Synthesis
cycle paths, etc.
(38) verilo
Delay characterization for cell libraries is clearly defined, forms an effective
interface between the foundry and the design team, and is readily available. interview
In addition to this, the Static Timing Analysis (STA) does not require input questions
vectors and has a runtime that is linear with the size of the circuit [9]. (30)
Verification
PVT vs. Delay
(28) ASI
(26) DSP (2
HDL (19) Sta
Sources of variation can be: Timing Analys
(STA) (18) Lo
Process variation (P) Power Technique
Supply voltage (V)
(16) log
synthesis (1
Operating Temperature (T)
FPGA (1
MATLAB (1
Timing Analys
(15) Physic
Process Variation [14] Design (13) Dig
design (9) CMOS
Asynchronous FIF
This variation accounts for deviations in the semiconductor fabrication (7) interview (7) 3
process. Usually process variation is treated as a percentage variation in the ICs (6) P
performance calculation. Variations in the process parameters can be impurity Microcontroller
concentration densities, oxide thicknesses and diffusion depths. These are PIC 16F877A (5) VL
caused bye non uniform conditions during depositions and/or during diffusions (4) Clock Gating
of the impurities. This introduces variations in the sheet resistance and EDA (2) Full Custom
transistor parameters such as threshold voltage. Variations are in the ASIC Jobs (1) AtopTech

dimensions of the devices, mainly resulting from the limited resolution of the Gate Delay (1)

photolithographic process. This causes (W/L) variations in MOS transistors.

Articles

Process variations are due to variations in the manufacture conditions such March 2008 (4)

as temperature, pressure and dopant concentrations. The ICs are produced in

lots of 50 to 200 wafers with approximately 100 dice per wafer. The electrical
properties in different lots can be very different. There are also slighter
differences in each lot, even in a single manufactured chip. There are
variations in the process parameter throughout a whole chip. As a
consequence, the transistors have different transistor lengths throughout the
chip. This makes the propagation delay to be different everywhere in a chip,

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because a smaller transistor is faster and therefore the propagation delay is

smaller.

Supply Voltage Variation [14]

The design’s supply voltage can vary from the established ideal value during
day-to-day operation. Often a complex calculation (using a shift in threshold
voltages) is employed, but a simple linear scaling factor is also used for logic-
level performance calculations.

The saturation current of a cell depends on the power supply. The delay of a
cell is dependent on the saturation current. In this way, the power supply
inflects the propagation delay of a cell. Throughout a chip, the power supply is
not constant and hence the propagation delay varies in a chip. The voltage
drop is due to nonzero resistance in the supply wires. A higher voltage makes
a cell faster and hence the propagation delay is reduced. The decrease is
exponential for a wide voltage range. The self-inductance of a supply line
contributes also to a voltage drop. For example, when a transistor is switching
to high, it takes a current to charge up the output load. This time varying
current (for a short period of time) causes an opposite self-induced
electromotive force. The amplitude of the voltage drop is given by .V=L*dI/dt,
where L is the self inductance and I is the current through the line.

Operating Temperature Variation [14]

Temperature variation is unavoidable in the everyday operation of a design.

Effects on performance caused by temperature fluctuations are most often
handled as linear scaling effects, but some submicron silicon processes
require nonlinear calculations.

When a chip is operating, the temperature can vary throughout the chip. This
is due to the power dissipation in the MOS-transistors. The power
consumption is mainly due to switching, short-circuit and leakage power
consumption. The average switching power dissipation (approximately given
by Paverage = Cload*Vpower supply 2*fclock) is due to the required energy
to charge up the parasitic and load capacitances. The short-circuit power
dissipation is due to the finite rise and fall times. The nMOS and pMOS
transistors may conduct for a short time during switching, forming a direct
current from the power supply to the ground. The leakage power consumption
is due to the nonzero reverse leakage and sub-threshold currents. The
biggest contribution to the power consumption is the switching. The dissipated
power will increase the surrounding temperature. The electron and hole
mobility depend on the temperature. The mobility (in Si) decreases with
increased temperature for temperatures above –50 °C. The temperature,
when the mobility starts to decrease, depends on the doping concentration. A
starting temperature at –50 °C is true for doping concentrations below 1019

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atoms/cm3. For higher doping concentrations, the starting temperature is

higher. When the electrons and holes move slower, then the propagation
delay increases. Hence, the propagation delay increases with increased
temperature. There is also a temperature effect, which has not been
considered. The threshold voltage of a transistor depends on the temperature.
A higher temperature will decrease the threshold voltage. A lower threshold
voltage means a higher current and therefore a better delay performance.
This effect depends extremely on power supply, threshold voltage, load and
input slope of a cell. There is a competition between the two effects and
generally the mobility effect wins.

The following figure shows the PVT operating conditions.

The best and worst design corners are defined as follows:

Best case: fast process, highest voltage and lowest temperature

Worst case: slow process, lowest voltage and highest

temperature

On Chip Variation

On-chip variation is minor differences on different parts of the chip within one
operating condition. On-Chip variation (OCV) delays vary across a single die
due to:
Variations in the manufacturing process (P)

Variations in the voltage (due to IR drop)

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Variations in the temperature (due to local hot spots etc)

This need is to be modeled by scaling the coefficients. Delays have

uncertainty due to the variation of Process (P), Voltage (V), and Temperature
(T) across large dies. On-Chip variation allows you to account for the delay
variations due to PVT changes across the die, providing more accurate delay
estimates.

Timing Analysis With On-Chip Variation

For cell delays, the on-chip variation is between 5 percent above

and 10 percent below the SDF back-annotated values.

For net delays, the on-chip variation is between 2 percent above

and 4 percent below the SDF back-annotated values.

For cell timing checks, the on-chip variation is 10 percent above

the SDF values for setup checks and 20 percent below the SDF
values for hold checks.

In Prime Time, OCV derations are implemented using the following

commands:

pt_shell> read_sdf -analysis_type on_chip_variation

my_design.sdf

pt_shell> set_timing_derate -cell_delay -min 0.90 -max 1.05

pt_shell> set_timing_derate -net -min 0.96 -max 1.02

pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10

In the traditional deterministic STA (DSTA), process variation is modeled by

running the analysis multiple times, each at a different process condition. For
each process condition, a so-called corner file is created that specifies the
delay of the gates at that process condition. By analyzing a sufficient number
of process conditions, the delay of the circuit under process variation can be
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bounded.

The uncertainty in the timing estimate of a design can be classified into three
main categories.

Modeling and analysis errors: Inaccuracy in device models, in

the extraction and reduction of interconnect parasitics and in the
timing analysis algorithms.
Manufacturing variations: Uncertainty in the parameters of a
fabricated devices and interconnects from die-to-die and within a
particular die.

Operating context variations: Uncertainty in the operating

environment of a particular device during its lifetime, such as
temperature, supply voltage, mode of operation and lifetime wear-
out.
For instance, the STA tool might utilize a conservative delay noise algorithm
resulting in certain paths operating faster than expected. Environmental
uncertainty and uncertainty due to modeling and analysis errors are typically
modeled using worst-case margins, whereas uncertainty in process is
generally treated statistically.

Taxonomy of Process Variations

As process geometries continue to shrink, the ability to control critical device

parameters is becoming increasingly difficult and significant variations in
device length, doping concentrations and oxide thicknesses have resulted [9].
These process variations pose a significant problem for timing yield prediction
and require that static timing analysis models the circuit delay not as a
deterministic value, but as a random variable.

Process variations can either systematic or random.

Systematic variation: Systematic variations are deterministic in

nature and are caused by the structure of a particular gate and its
topological environment. The systematic variations are the
component of variation that can be attributed to a layout or
manufacturing equipment related effects. They generally show
spatial correlation behavior.

Random variation: Random or non-systematic variations are

unpredictable in nature and include random variations in the
device length, discrete doping fluctuations and oxide thickness
variations. Random variations cannot be attributed to a specific
repeatable governing principle. The radius of this variation is
comparable to the sizes of individual devices, so each device can
vary independently.

Process variations can classified as follow:

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Inter-die variation or die-to-die: Inter-chip variations are

variations that occur from one die to next, meaning that the same
device on a chip has different features among different die of one
wafer, from wafer to wafer and from wafer lot to wafer lot. Die-to-
die variations have a variation radius larger than the die size
including within wafer, wafer to wafer, lot to lot and fab to fab
variations [12].

Intra-die or within-die variation: Intra-die variations are the

variations in device features that are present within a single chip,
meaning that a device feature varies between different locations
on the same die. Intra-chip variations exhibit spatial correlations
and structural correlations.

Front-end variation: Front-end variations mainly refer to the

variations present at the transistor level. The primary components
of the front end variations entail transistor gate length and gate
width, gate oxide thickness, and doping related variations. These
physical variations cause changes in the electrical characteristics
of the transistors which eventually lead to the variability in the
circuit performance.

Back-end variation: Back-end variations refer to the variations on

various levels of interconnecting metal and dielectric layers used
to connect numerous devices to form the required logic gates.
In practice, device features vary among the devices on a chip and the
likelihood that all devices have a worst-case feature is extremely small. With
increasing awareness of process variation, a number of techniques have
been developed which model random delay variations and perform STA.
These can be classified into full-chip analysis and path-based analysis
approaches.

Full Chip Analysis

Full-chip analysis models the delay of a circuit as a random variable and

endeavors to compute its probability distribution. The proposed methods are
heuristic in nature and have a very high worst-case computational complexity.
They are also based on very simple delay models, where the dependence of
gate delay due to slope variation at the input of the gate and load variation at
the output of the gate is not modeled. When run time and accuracy are
considered, full chip STA is not yet practical for industrial designs.

Path Based STA

Path based STA provides statistical information on a path-by-path basis. It

accounts for intra-die process variations and hence eliminates the pessimism
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in deterministic timing analysis, based on case files. It is a more accurate

measure of which paths are critical under process variability, allowing more
correct optimization of the circuit. This approach does not include the load
dependence of the gate delay due to variability of fan out gates and does not
address spatial correlations of intra-die variability.

To compute the intra-die path delay component of process variability, first the
sensitivity of gate delay, output slope and input load with respect to slope,
output load and device length are computed. Finally, when considering
sequential circuits, the delay variation in the buffered clock tree must be
considered.

In general, the fully correlated assumptions will under-estimate the variation in

the arrival times at the leaf nodes of the clock tree which will tend to
overestimate circuit performance.

References

[1]
http://www.ecs.umass.edu/ece/vspgroup/burleson/courses/558/558%20L01.p
df
[2] David Blaauw, Kaviraj Chopra, Ashish Srivastava and Lou Scheffer,
“Statistical Timing Analysis: From basic principles to state-of-the-art.”
Transactions on Computer-Aided Design of Integrated Circuits and Systems
(T-CAD), invited review article, to appear.
[3] Andrew B. Kahng, Bao Liu and Xu Xu, “Statistical Timing Analysis in the
Presence of Signal-Integrity Effects,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 22, no.10, Oct. 2007.
[4] http://eetimes.com/news/design/showArticle.jhtml?articleID=163703301
[5] Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran and Chandu
Visweswariah, “Criticality Computation in Parameterized Statistical Timing,”
DAC 2006: 63-68.
[6] http://www.cdnusers.org/Interviewsstastratosphere/tabid/418/Default.aspx
[7]
http://www.edadesignline.com/showArticle.jhtml;jsessionid=1ISIZARO0KMGM
QSNDLOSKH0CJUNN2J
[8] A. Nardi, E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, T.Lin and J. Song,
“Use of Statistical timing Analysis on Real Designs” Proceedings of the IEEE
Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, April
2007.
[9] Agarwal, A. Blaauw, D. Zolotov, V. Sundareswaran, S. Min Zhao Gala, K.
and Panda, R., “Statistically Delay computation considering spatial
correlations,” Proceedings of the ASP-DAC 2003, pp.271-276, Jan 2003.
[10] Aseem Agarwal, David Blaauw and Vladimir Zolotov, “Statistical Timing
Analysis for Intra-Die process Variations with spatial correlations” IEEE
Transactions on Computer-Aided Design, pp. 900-907, Nov 2003.
[11] Aseem Agarwal, David Blaauw and Vladimir Zolotov, “Statistical Clock
Skew Analysis Considering Intra-Die Process Variations,” IEEE Transactions
on Computer-Aided Design, vol. 23, no. 8, pp. 1231-1242, Aug, 2004.
[12] Ayhan Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, and

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17/06/2020 ASIC-System on Chip-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

Long-Ching Yeh, “An Exploratory Study on Statistical Timing Analysis and

Parametric Yield Optimization,” Proceedings of the 8th International
Symposium on Quality Electronic Design, pp. 677-684, 2007.
[13] Robert B.Hitchcock, Sr, Gordon L. Smith, David D. Cheng, “Timing
Analysis of Computer Hardware,” IBM Journal, vol. 26, no. 1, Jan 1981.

Below link in contributed by Rajneesh. Thanks Raj.

(14) "Investigation of typical 0.13 μm CMOS technology timing effects in a
complex digital system on-chip", www.diva-portal.org/diva/getDocument?
urn_nbn_se_liu_diva-2118-1__fulltext.pdf

Authors
1)Sowmya yadala, MS in VLSI System Design from MSRSAS, Bangalore.
She can be reached at: [email protected]
2) Myself !

Tags: PVT vs STA, Static Timing Analysis (STA), Timing Analysis

15 comments:

Anonymous March 31, 2008 at 11:54 AM

Hi,
can someone illustrate the co-relation between Common Path Pessimism (CPP)
& On-Chop Variation(OCV)
Reply

Murali March 31, 2008 at 1:20 PM

In On Chip Variation mode, in setup analysis, maximum delays for launch and
data path are considered; while minimum delays for capture path are
considered. If there is a common shared segment in clock path which is
common to both launch and capture path, then max and min delays of the
shared segment is used at a time which is non realistic. This situation is known
as Clock Reconvergence Pessimism. This adds more pessimism to the timing
analysis. To make it more accurate, find difference of max and min delays of the
shared segment and subtract from the capture path for setup analysis.

rgds
murali
Reply

Unknown July 17, 2008 at 3:18 PM

Hello Murali sir
This blogspot has very good material for learning VLSI...If possible please
upload the Application notes of Astro.

Regards
Sudeendra
NIT Rourkela
Reply

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17/06/2020 ASIC-System on Chip-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

Anonymous November 7, 2008 at 2:34 PM

Hi, I guess you used a very important reference material but have failed to
indicate this in your reference section. The material that i am referring to is
available at www.diva-portal.org/diva/getDocument?urn_nbn_se_liu_diva-2118-
1__fulltext.pdf and has the title of "Investigation of typical 0.13 μm CMOS
technology timing effects in a complex digital system on-chip".

My apologies if you have already indicated this at some place, but i was not able
to find it.

Regards,
Rajneesh
Reply

Murali November 7, 2008 at 3:44 PM

ya ..you are right... may be the reference i used might have used the document
you specified as their reference..... thanks for the document link......readers like
you make this blog more valuable....i welcome your take on other articles
Reply

Gk November 7, 2008 at 3:57 PM

1
Reply

Grigor December 14, 2008 at 1:23 AM

Hello Murali,

I have set for max_capacitance constraint to 0.07pf.

In worst cornet I don't have max cap violation but in best I have.
Does this have any explanation?
Reply

Anonymous March 13, 2011 at 12:23 AM

Hi,

Could you please help me understand intuitively, why threshold voltage

decreases with increase in temperature?

Thanks !
Reply

Replies

Unknown February 17, 2014 at 11:03 AM

Because when temperature increase then mobility of electron will
decrease so threshold voltage will reduce.
Vt is inversely proportional to temperature.

Shyam Krish March 30, 2020 at 12:11 PM

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17/06/2020 ASIC-System on Chip-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

Threshold voltage is a voltage above which, if applied to gate, inversion

happens.

Resistivity of semiconductor decreases with increase in temperature. In

other words, we have more charge carriers in conduction band and
hence the decrease in threshold voltage.

Reply

Anonymous June 30, 2011 at 4:06 PM

Hi
can any one help me to get the notes for low power vlsi,which is an elective for
Mtech students
Reply

Hiran June 14, 2012 at 11:46 AM

Hi,

Thanks for the detailed explanation on PVT...

Can you please explain how 'temperature inversion' is modeled in a VLSI
design?
Reply

Vinod March 27, 2013 at 11:43 PM

Hi,

Thanks for the details on on-chip variation.

Can you please explain why hold is more sensitive to on-chip variation than
setup, as you have mentioned the percentage change for cell delay, net delay
and setup/hold timing checks.
Reply

Vinod March 27, 2013 at 11:45 PM

Hi.

Thanks for details...

Can you please explain why setup is more sensitive to on-chip variation than
hold? as you have indicated in cell delay, net delay and setup/hold timing
checks.
Reply

Unknown November 27, 2016 at 12:32 PM

Thank you
Ajit
NITR
Reply

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