Bluetooth Low Energy 4.2 Soc General Description: Final

DA14580
Bluetooth Low Energy 4.2 SoC FINAL
General Description  42 kB System SRAM

 84 kB ROM
The DA14580 integrated circuit has a fully integrated
 8 kB Retention SRAM
radio transceiver and baseband processor for Blue-
 Power management
tooth® low energy. It can be used as a standalone
 Integrated Buck/Boost DC-DC converter
application processor or as a data pump in hosted sys-
 P0, P1, P2 and P3 ports with 3.3 V tolerance
tems.
 Easy decoupling of only 4 supply pins
The DA14580 supports a flexible memory architecture  Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application battery cells
code, which can be updated over the air (OTA). The  10-bit ADC for battery voltage measurement
qualified Bluetooth low energy protocol stack is stored  Digital controlled oscillators
in a dedicated ROM. All software runs on the ARM®  16 MHz crystal (±20 ppm max) and RC oscillator
Cortex®-M0 processor via a simple scheduler.  32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
The Bluetooth low energy firmware includes the
 General purpose, Capture and Sleep timers
L2CAP service layer protocols, Security Manager
 Digital interfaces
(SM), Attribute Protocol (ATT), the Generic Attribute
 General purpose I/Os: 14 (WLCSP34 package),
Profile (GATT) and the Generic Access Profile (GAP).
24 (QFN40 package), 32 (QFN48 package)
All profiles published by the Bluetooth SIG as well as
 2 UARTs with hardware flow control up to 1 MBd
custom profiles are supported.
 SPI+™ interface
The transceiver interfaces directly to the antenna and  I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.2 standard.  3-axes capable Quadrature Decoder
 Analog interfaces
The DA14580 has dedicated hardware for the Link
 4-channel 10-bit ADC
Layer implementation of Bluetooth low energy and
 Radio transceiver
interface controllers for enhanced connectivity capabili-
 Fully integrated 2.4 GHz CMOS transceiver
ties.
 Single wire antenna: no RF matching or RX/TX
switching required
Features  Supply current at VBAT3V:
 Complies with Bluetooth V4.2, ETSI EN 300 328 and TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15  0 dBm transmit output power
(US) and ARIB STD-T66 (Japan)  -20 dBm output power in “Near Field Mode”
 Processing power  -93 dBm receiver sensitivity
 16 MHz 32 bit ARM Cortex-M0 with SWD inter-  Packages:
face  WLCSP 34 pins, 2.436 mm x 2.436 mm
 Dedicated Link Layer Processor  QFN 40 pins, 5 mm x 5 mm
 AES-128 bit encryption Processor  QFN 48 pins, 6 mm x 6 mm
 Memories  KGD (wafer, dice)
 32 kB One-Time-Programmable (OTP) memory
________________________________________________________________________________________________
System Diagram
Datasheet Revision 3.4 09-Nov-2016

CFR0011-120-01 1 of 234 © 2014 Dialog Semiconductor
DA14580
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 11.4 GENERAL CLOCK CONSTRAINTS . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 OTP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12.1 OPERATING MODES . . . . . . . . . . . . . . . . . . 33

12.2 AHB MASTER INTERFACE . . . . . . . . . . . . . 33
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
13 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
13.1 I2C BUS TERMS . . . . . . . . . . . . . . . . . . . . . . 34
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 13.1.1 Bus Transfer Terms . . . . . . . . . . . . . . . 35
13.2 I2C BEHAVIOR . . . . . . . . . . . . . . . . . . . . . . . 35
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 9
13.2.1 START and STOP Generation . . . . . . . 36
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13.2.2 Combined Formats . . . . . . . . . . . . . . . 36
4.1 INTERNAL BLOCKS . . . . . . . . . . . . . . . . . . . . 10 13.3 I2C PROTOCOLS . . . . . . . . . . . . . . . . . . . . . 36
4.2 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 10 13.3.1 START and STOP Conditions . . . . . . . 36
4.3 OTP MEMORY LAYOUT . . . . . . . . . . . . . . . . .11 13.3.2 Addressing Slave Protocol. . . . . . . . . . 36
4.3.1 OTP Header. . . . . . . . . . . . . . . . . . . . . . .11 13.3.3 Transmitting and Receiving Protocols . 37
4.4 SYSTEM START PROCEDURE . . . . . . . . . . . 12 13.4 MULTIPLE MASTER ARBITRATION . . . . . . 39
4.4.1 Power/Wake-Up Sequence . . . . . . . . . . 13 13.5 CLOCK SYNCHRONIZATION . . . . . . . . . . . 40
4.4.2 OTP Mirroring . . . . . . . . . . . . . . . . . . . . 14 13.6 OPERATION MODES . . . . . . . . . . . . . . . . . . 41
4.4.3 BootROM Sequence . . . . . . . . . . . . . . . 15 13.6.1 Slave Mode Operation . . . . . . . . . . . . . 41
4.5 POWER SUPPLY CONFIGURATION . . . . . . 17 13.6.2 Master Mode Operation . . . . . . . . . . . . 43
4.5.1 Power Domains . . . . . . . . . . . . . . . . . . . 17 13.6.3 Disabling the I2C Controller . . . . . . . . . 43
4.5.2 Power Modes . . . . . . . . . . . . . . . . . . . . . 18
14 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5.3 Retention Registers . . . . . . . . . . . . . . . . 18
14.1 UART (RS232) SERIAL PROTOCOL . . . . . . 45
5 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14.2 IRDA 1.0 SIR PROTOCOL . . . . . . . . . . . . . . 45
5.1 POR, HW AND SW RESET . . . . . . . . . . . . . . 20 14.3 CLOCK SUPPORT . . . . . . . . . . . . . . . . . . . . 46
14.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . 47
6 ARM Cortex-M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
14.5 PROGRAMMABLE THRE INTERRUPT . . . . 47
6.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 22
14.6 SHADOW REGISTERS . . . . . . . . . . . . . . . . 49
6.2 SYSTEM TIMER (SYSTICK). . . . . . . . . . . . . . 23
14.7 DIRECT TEST MODE . . . . . . . . . . . . . . . . . . 49
6.3 WAKE-UP INTERRUPT CONTROLLER. . . . . 23
6.4 REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 SPI+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.1 OPERATION WITHOUT FIFOS . . . . . . . . . . 50
7 AMBA Bus Overview. . . . . . . . . . . . . . . . . . . . . . . . 24
15.2 9 BITS MODE . . . . . . . . . . . . . . . . . . . . . . . . 51
8 Patch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16 Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . 54
9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17 Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . 28
18 General Purpose Timers. . . . . . . . . . . . . . . . . . . . 56
10.1 ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . 28
18.1 TIMER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . 29 18.2 TIMER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 CRYSTAL OSCILLATORS . . . . . . . . . . . . . . 29
19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.1.1 Frequency Control (16 MHz Crystal) . . 29
11.1.2 Automated Trimming Mechanism . . . . 29 20 Keyboard Controller . . . . . . . . . . . . . . . . . . . . . . . 61
11.2 RC OSCILLATORS . . . . . . . . . . . . . . . . . . . . 30 20.1 KEYBOARD SCANNER . . . . . . . . . . . . . . . . 61
11.2.1 Frequency Calibration . . . . . . . . . . . . . 30 20.2 GPIO INTERRUPT GENERATOR . . . . . . . . 61
11.3 SYSTEM CLOCK GENERATION . . . . . . . . . 31

DA14580
21 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . 63
21.1 PROGRAMMABLE PIN ASSIGNMENT . . . . 63
21.2 GENERAL PURPOSE PORT REGISTERS . 63
21.2.1 Port Data Register . . . . . . . . . . . . . . . . 64
21.2.2 Port Set Data Output Register . . . . . . . 64
21.2.3 Port Reset Data Output Register . . . . . 64
21.3 FIXED ASSIGNMENT FUNCTIONALITY . . . 64
22 General Purpose ADC. . . . . . . . . . . . . . . . . . . . . . 65

22.1 INPUT CHANNELS AND INPUT SCALE . . . 65
22.2 STARTING THE ADC AND SAMPLING RATE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
22.3 NON-IDEAL EFFECTS . . . . . . . . . . . . . . . . . 66
22.4 CHOPPING . . . . . . . . . . . . . . . . . . . . . . . . . . 66
22.5 OFFSET CALIBRATION . . . . . . . . . . . . . . . . 66
22.6 ZERO-SCALE ADJUSTMENT . . . . . . . . . . . 67
22.7 COMMON MODE ADJUSTMENT. . . . . . . . . 67
22.8 INPUT IMPEDANCE, INDUCTANCE AND IN-
PUT SETTLING. . . . . . . . . . . . . . . . . . . . . . . . 67
22.9 DELAY COUNTER . . . . . . . . . . . . . . . . . . . . 68
23 Power Management. . . . . . . . . . . . . . . . . . . . . . . . 69
24 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
24.1 EXCHANGE MEMORY . . . . . . . . . . . . . . . . . 72
24.2 PROGRAMMING BLE WAKE UP IRQ . . . . . 74
24.3 SWITCH FROM ACTIVE MODE TO DEEP
SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . 74
24.4 SWITCH FROM DEEP SLEEP MODE TO AC-
TIVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . 75
24.4.1 Switching at Anchor Points . . . . . . . . . 75
24.4.2 Switching Due to an External Event . . 77
25 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.1 RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.2 SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . 78
25.3 TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . 78
25.4 RFIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.5 BIASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.6 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
27 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
28 Package Information . . . . . . . . . . . . . . . . . . . . . . 230

28.1 MOISTURE SENSITIVITY LEVEL (MSL) . . 230
28.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . 230
28.3 SOLDERING INFORMATION . . . . . . . . . . . 230
28.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . 231

DA14580
1 Block Diagram
24 April 2012
DCDC
ARM Cortex M0 RC RC RCX
(BUCK/BOOST)
XTAL XTAL 16 MHz 32 kHz
32.768 kHz 16 MHz LDO LDO LDO
LDO
LDO
CORE SYS RET SYS
SYS
RF POReset
BLE Core
SWD (JTAG)
Radio
LINK LAYER
System/ AES-128 Transceiver
HARDWARE
Exchange
RAM
42 kB
Ret. RAM
Memory Controller
2 kB
APB bridge
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4 SW TIMER
Management (PMU)
KEYBOARD
DECODER
1 kB
POWER/CLOCK
WAKE UP
GP ADC
UART2
TIMER
QUAD
UART
CTRL
SPI
I2C
OTP DMA Timer 0
1x PWM
FIFO
FIFO
FIFO
32 kB OTPC
Timer 2
ROM 3x PWM GPIO MULTIPLEXING
84 kB
Figure 1: DA14580 Block Diagram

DA14580
2 Pinout • Quad Flat Package No Leads (QFN) with 48 pins

The DA14580 comes in three packages: • Quad Flat Package No Leads (QFN) with 40 pins
• Wafer Level Chip Scale Package (WLCSP) with 34 The actual pin/ball assignment is depicted in the follow-
balls ing figures:
1 2 3 4 5 6
F
M
D
16
A
C_
P
O
O
VP
FI
AL
FI
G
D
R
R
C
XT
VD
p
M
16
_3
_1
_0
B
D
AL
N
P1
P0
P0
G
XT
LK
3
C
ND
_C
_
P1
P0
P0
SW
G
IO
_5
D
D
4
D _1
_
N
D
P0
P0
P1
G
SW
F
V
_R
0
E
1
_6
_7
T
_
AT
RS
AT
P1
P0
P0
VB
VB
Km
Kp
H
V
C
32
D
CD
32
3
IT
AT
AL
G
AL
SW
VD
XT
VB
Figure 2: WLCSP34 ball assignment XT
VDCDC_RF
RFIOm
RFIOp
P3_7
P2_0
P2_9
P2_8
P2_7
P2_6
P2_5
VPP
NC
48
47
46
45
44
43
42
41
40
39
38
37
P0_0 1 36 P3_6
P0_1 2 35 XTAL16Mm
P0_2 3 34 XTAL16Mp
P0_3 4 33 P1_3
P3_0 5 32 P1_2
P0_4 6 DA14580 31 SW_CLK
P0_5 7 30 SWDIO
(Top View)
P2_1 8 29 P1_1
P0_6 9 28 VBAT1V
P3_1 10 27 P1_0
P0_7 11 26 SWITCH
P3_2 12 25 P3_5
13
14
15
16
17
18
19
20
21
22
23
24
Pin 0: GND plane

VBAT_RF
P3_4
XTAL32Kp
P3_3
P2_2
RST
XTAL32Km
GND
P2_3
P2_4
VDCDC
VBAT3V
Figure 3: QFN48 Pin Assignment

DA14580
VDCDC_RF
RFIOm
RFIOp
P2_0
P2_9
P2_8
P2_7
P2_6
P2_5
VPP
40
39
38
37
36
35
34
33
32
31
P0_0 1 30 XTAL16Mm
P0_1 2 29 XTAL16Mp
P0_2 3 28 P1_3
P0_3 4 27 P1_2
NC 5 DA14580 26 SW_CLK
P0_4 6 25 SWDIO
(Top View)
P0_5 7 24 P1_1
P2_1 8 23 VBAT1V
P0_6 9 22 P1_0
P0_7 10 21 SWITCH
11
12
13
14
15
16
17
18
19
20
VBAT_RF
VBAT3V
XTAL32Kp
P2_2
P2_3
XTAL32Km
VDCDC
P2_4
RST
GND
Pin 0: GND
plane
Figure 4: QFN40 Pin Assignment
Table 1: Pin Description
Drive Reset
Pin Name Type Description
(mA) State
General Purpose I/Os
P0_0 DIO 4.8 I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
P0_1 DIO I-PD enabled during and after reset. General purpose I/O port bit or
P0_2 DIO I-PD alternate function nodes. Contains state retention mechanism
P0_3 DIO I-PD during power down.
P0_4 DIO I-PD
P0_5 DIO I-PD
P0_6 DIO I-PD
P0_7 DIO I-PD
P1_4/SWCLK DIO I-PD This signal is the JTAG clock by default
P1_5/SW_DIO DIO I-PU This signal is the JTAG data I/O by default
P2_4 DIO I-PD NOTE: This port is only available on the QFN40/QFN48 pack-
P2_5 DIO I-PD ages.
P2_6 DIO I-PD
P2_7 DIO I-PD
P2_8 DIO I-PD
P2_9 DIO I-PD

DA14580
Drive Reset
(mA) State
P3_2 DIO I-PD alternate function nodes. Contain state retention mechanism dur-
P3_3 DIO I-PD ing power down.
P3_4 DIO I-PD NOTE: This port is only available on the QFN48 package.
P3_5 DIO I-PD
P3_6 DIO I-PD
P3_7 DIO I-PD
Debug Interface
SWDIO/P1_5 DIO 4.8 I-PU INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
SW_CLK/ DIO 4.8 I-PD INPUT JTAG clock signal. Can also be used as a GPIO
P1_4
Clocks
XTAL16Mp AI INPUT. Crystal input for the 16 MHz XTAL
XTAL16Mm AO OUTPUT. Crystal output for the 16 MHz XTAL
XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL
XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL
Quadrature Decoder
QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports
QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports
QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports
QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports
QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports
QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports
SPI Bus Interface
SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports
SPI_DI DI INPUT. SPI Data input. Mapped on Px ports
SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports
SPI_EN DI INPUT. SPI Clock enable (active LOW). Mapped on Px ports
I2C Bus Interface
SDA DIO/DIOD INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on
Px ports
SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port. In open
drain mode, SCL is monitored to support bit stretching by a
slave. Mapped on Px ports.
UART Interface
UTX DO OUTPUT. UART transmit data. Mapped on Px ports
URX DI INPUT. UART receive data. Mapped on Px ports
URTS DO OUTPUT. UART Request to Send. Mapped on Px ports
UCTS DI INPUT. UART Clear to Send. Mapped on Px ports
UTX2 DO OUTPUT. UART 2 transmit data. Mapped on Px ports
URX2 DI INPUT. UART 2 receive data. Mapped on Px ports
URTS2 DO OUTPUT. UART 2 Request to Send. Mapped on Px ports
UCTS2 DI INPUT. UART 2 Clear to Send. Mapped on Px ports

DA14580
Drive Reset
(mA) State
Analog Interface
ADC[0] AI INPUT. Analog to Digital Converter input 0. Mapped on P0[0]
Radio Transceiver
RFIOp AIO RF input/output. Impedance 50 
RFIOm AIO RF ground
Miscellaneous
RST DI INPUT. Reset signal (active high). Must be connected to GND if
not used.
VBAT_RF AIO Connect to VBAT3V on the PCB
VDCDC_RF AIO Connect to VDCDC on the PCB
VPP AI INPUT. This pin is used while OTP programming and testing.
OTP programming: VPP = 6.7 V ± 0.1 V
OTP Normal operation: leave VPP floating
Power Supply
VBAT3V AIO INPUT/OUTPUT. Battery connection. Used for a single coin bat-
tery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to
pin VBAT1V, this is the second output of the DC-DC converter.
VBAT1V AI INPUT. Battery connection. Used for an alkaline or a NiMh bat-
tery (1.5 V). If a single coin battery (3 V) is attached to pin
VBAT3V,this pin must be connected to GND.
SWITCH AIO INPUT/OUTPUT. Connection for the external DC-DC converter
inductor.
VDCDC AO Output of the DC-DC converter
GND AIO - - Ground

DA14580
3 Ordering Information
Table 2: Ordering Information (Samples)
Part Number Package Size (mm) Shipment Form Pack Quantity

DA14580-01UNA WLCSP34 2.436 x 2.436 Mini-reel 50/100/1000
DA14580-01A31 QFN48 6x6 Tray 50
DA14580-01AT1 QFN40 5x5 Tray 50
Table 3: Ordering Information (Production)
Part Number Package Size (mm) Shipment Form Pack Quantity

DA14580-01UNA WLCSP34 2.436 x 2.436 Mini-reel 5000
DA14580-01A32 QFN48 6x6 Reel 4000
DA14580-01AT2 QFN40 5x5 Reel 5000
DA14580-01WO4 KGD wafer Contact Dialog Semiconductor sales office
DA14580-01WC4 KGD dice Contact Dialog Semiconductor sales office
Table 4: Ordering Information (Preprogrammed OTP)
Part Number Package Shipment Form Pack Quantity Description

DA14580-01PxA31 QFN48 Tray 50 Preprogrammed OTP, version x
DA14580-01PxAT1 QFN40 Tray 50 Preprogrammed OTP, version x
DA14580-01PxUNA WLCSP34 Mini-reel 5000 Preprogrammed OTP, version x
DA14580-01PxA32 QFN48 Reel 4000 Preprogrammed OTP, version x
DA14580-01PxAT2 QFN40 Reel 4000 Preprogrammed OTP, version x
Part Number Legend:

DA14580-nn[ABC]XYZ
nn: chip revision number
A, AB or ABC: special version (optional)
XY: package code
Z: packing method

DA14580
4 System Overview (RC16M and RC32K) with low precision (> 500 ppm)
and an 10.5 kHz oscillator (RCX) with high precision
4.1 INTERNAL BLOCKS (< 500 ppm). The RCX oscillator can be used as a
The DA14580 contains the following blocks: sleep clock replacing the XTAL32K oscillator to further
improve the power dissipation of the system while
ARM Cortex M0 CPU with Wake-up Interrupt Control- reducing the bill of materials of the system. The
ler (WIC). This processor provides 0.9 dMIPS/MHz and RC16M oscillator is used to provide a clock used for
is used for assisting the Bluetooth low energy protocol the mirroring of the OTP code into the SysRAM while
implementation, providing processing power for calcu- the XTAL16M oscillator is settling directly after power/
lations or data fetches required by the application and wake up.
finally housekeeping, including controlling of the power
scheme of the system. Software Timer. This block contains a 16-bit general
purpose timer (Timer0) with PWM capability as well as
BLE Core. This is the baseband hardware accelerator a 14-bits timer (Timer2) which controls 3 PWM signals
for the Bluetooth low energy protocol. with respect to frequency and duty cycle.
ROM. This is a 84 kB ROM containing the Bluetooth Wake-Up Timer. This is a timer for capturing external
low energy protocol stack as well as the boot code events and it can be used as a wake-up trigger based
sequence. on a programmable number of external events on any
OTP. This is a 32 kB One-Time Programmable memory of the GPIO ports.
array, used to store the application code as well as Quadrature Decoder. This block decodes the pulse
Bluetooth low energy profiles. It also contains the sys- trains from a rotary encoder to provide the step and the
tem configuration and calibration data. direction of the movement of an external device. Three
System SRAM. This is a 42 kB system SRAM (Sys- axes (X, Y, Z) are supported.
RAM) which is primarily used for mirroring the program Keyboard Controller. This circuit enables the reading
code from the OTP when the system wakes/powers and debouncing of a programmable number of GPIOs
up. It also serves as Data RAM for intermediate vari- and generates an interrupt upon a configurable action.
ables and various data that the protocol requires.
Optionally, it can be used as extra memory space for AHB/APB Bus. Implements the AMBA Lite version of
the BLE TX and RX data structures. the AHB and APB specifications.
Retention RAMs. These are 4 special low leakage Power Management. A sophisticated power manage-
SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store ment circuit with a Buck/Boost DC-DC converter and
various data of the Bluetooth low energy protocol as several LDOs that can be turned on/off via software.
well as the system’s global variables and processor A more detailed description of each of the components
stack when the system goes into Deep Sleep mode. of the DA14580 is presented in the following sections.
Storage of this data ensures secure and quick configu-
ration of the BLE Core after the system wakes up. 4.2 FUNCTIONAL MODES
Every cell can be powered on or off according to the The DA14580 is optimized for deeply embedded appli-
application needs for retention area when in Deep cations such as health monitoring, sports measuring,
Sleep mode. human interaction devices etc. Customers are able to
UART and UART2. These asynchronous serial inter- develop and test their own applications. Upon comple-
faces implement hardware flow control with FIFO tion of the development, the application code can be
depths of 16 bytes each. programmed into the OTP. In general, the system has
three functional modes of operation:
SPI. This is the serial peripheral interface with master/
slave capability and a FIFO of 2 16-bit words. A. Development Mode: During this phase application
code is developed using the ARM Cortex-M0 SW envi-
I2C. This is Master/Slave I2C interface used for sen- ronment. The compiled code is then downloaded into
sors and/or host MCUs communication. It comprises a the System RAM or any Retention RAMs by means of
32 places 9-bits wide FIFO. SWD (JTAG) or any serial interface (e.g. UART).
General Purpose (GP) ADC. This is a 10-bits analog- Address 0x00 is remapped to the physical memory that
to-digital converter with 4 external input channels. contains the code and the CPU is configured to reset
and execute code from the remapped device. This
Radio Transceiver. This block implements the RF part mode is enabling application development, debugging
of the Bluetooth low energy protocol. and on-the-fly testing.
Clock Generator. This block is responsible for the B. Normal Mode: After the application is ready and
clocking of the system. It contains 2 XTAL oscillators: verified, the code can be burned into the OTP. When
one running at 16 MHz (XTAL16M) which is used for the system boots/wakes up, the DMA of the OTP con-
the active mode of the system and one running at troller will automatically copy the program code from
32.768 kHz (XTAL32K) which is used for the sleep the OTP into the system RAM. Next, a SW reset or a
modes of the system. There are also three RC oscilla- jump to the System RAM occurs and code execution is
tors available: a 16 MHz and a 32 kHz oscillator started. Hence, in this mode, the system is autono-
DA14580
mous, contains the required SW in OTP and is ready The OTP memory comprises 8K of 32-bit words. The
for integration into the final product. contents are described below:
C. Calibration Mode: Between Development and Nor- • Interrupt Vectors: These are the vectors of the
mal mode, there is an intermediate stage where the interrupt service routines always residing at address
chip needs to be calibrated with respect to two impor- 0x0. This is part of the application (customer) code.
tant features: The size of this vector list is 64 words.
• Programming of the Bluetooth device address • Customer Code: contains the application and the
profiles that a customer has developed. The size is
• Programming of the trimming value for the external
known and fixed before mass production and pro-
16 MHz crystal.
gramming of the OTP.
This mode of operation applies to the final product and
• Patch Area: contains changes that have to be
is performed by the customer. During this phase, cer-
applied on the Customer Code. Each patch area
tain fields in the OTP should be programmed as
comprises a Header and a Payload. Multiple patch
described in section 4.3.1.
areas are possible, however a single word must be
4.3 OTP MEMORY LAYOUT left unprogrammed between the Customer Code
area and the Patch Area. The patching mechanism
The One Time Programmable memory has to be pro- is described in detail in Application Note AN-B-002.
grammed according to a specific layout, which struc-
tures information to be easily accessible from the • OTP Header: contains various information about the
BootROM code as well as the actual application. An configuration of the system as well as Bluetooth low
overview of the layout scheme is presented in the fol- energy specific data.
lowing figure:
4.3.1 OTP Header
The OTP header breakdown is presented in the follow-
ing table:
0x0000
Table 5: OTP Header
Interrupt Vectors
(64 words)
Description
Address
(single byte values apply to all 4 bytes)
CUSTOMER
0x7FFC SWD enable flag:
CODE 0x00 = JTAG is enabled
(variable but known size) 0xAA = JTAG is disabled
0x7FF8 OTP DMA length (number of 32-bit
words)
0x7FF4 Reserved. Keep to 0x0
0x7FDC Customer Specific Field (6 32-bit words)
to 0x7FF0
0x7FD4 to Bluetooth Device Address (2 32-bit
OTP
. 0x7FDB words). It is handled as a string of bytes.
.
. Leftmost number will be programmed at
0x7FD4 etc.
Patch Payload 2 0x7FD0 Signature Algorithm Selector:
0x00 = None
Patch Header 2 0xAA = MD5
0x55 = SHA-1
0xFF = CRC32
Patch Payload 1 0x7F94 to Signature of Customer Code
0x7FCC (15 32-bit words)
Patch Header 1
0x7F00 0x7F90 Trim value for the VCO
OTP Header 0x7F8C Trim value for the XTAL16M oscillator
(64 words) 0x7F88 Trim value for the RC16M oscillator
0x7FFC
0x7F84 Trim value for the BandGap
Figure 5: OTP Layout Scheme 0x7F80 Trim value for the RFIO capacitance
0x7F7C Trim value for the LNA

DA14580
Table 5: OTP Header range of frequencies. However, this trimming is done

during production tests by Dialog Semiconductor.
Description
Address Trimming values for the VCO, Bandgap reference, the
(single byte values apply to all 4 bytes)
RFIO capacitance and the LNA of the Radio are also
0x7F78 Calibration Flags: stored in the OTP header. These values are generated
Bit[31:16] - and programmed during production testing by Dialog
0xA5A5 = at least 1 calibration was Semiconductor.
done
0x0000 = no calibration was done The Calibration Flags defines whether the chip has
Bit[15:6] - Reserved been already calibrated and if so, which trim values are
Bit[5] - 1 = VCO trim value is valid valid. The 32 kHz Source Flag indicates to the applica-
Bit[4] - 1 = XTAL16M trim value is valid tion software whether an external 32 kHz crystal is
Bit[3] - 1 = RC16M trim value is valid used or not.
Bit[2] - 1 = BandGap trim value is valid The Package Flag defines which package is used: the
Bit[1] - 1 = RFIO trim value is valid 34 balls WLCSP, the 40 pins QFN or the 48 pins QFN.
Bit[0] - 1 = LNA trim value is valid
The IQ Trim value contains the value of respective
0x7F74 Sleep Clock Source Flag: radio configuration fields and is delivered at production
0x00 = External crystal (XTAL32K) testing.
0xAA = Internal RCX oscillator (RCX)
Two more flags are indicating if the application code
0x7F70 Package Flag: has indeed been programmed (burned) into the OTP.
0x00 = WLCSP34 Both flags are read by the BootROM software desig-
0xAA = QFN40 nating that the system is now in Normal mode and not
0x55 = QFN48 in Development mode, as explained in the next sec-
0x99 = KGD tion.
0x7F64 to Reserved
0x7F6C 4.4 SYSTEM START PROCEDURE
0x7F10 to Customer Specific Field (21 32-bit The actual start procedure consists of the following dis-
0x7F60 words) tinct stages that are sequentially combined to form the
preferred system start sequence:
0x7F0C CRC for Trim and Calibration values
1. The Power/Wake-up sequence
0x7F08 IQ Trim value
0x7F04 Application Programmed Flag #2 2. The OTP mirroring sequence
0xA5A51234 = Application is in OTP 3. The BootROM booting sequence
0x7F00 Application Programmed Flag #1 The Power/Wake-up sequence is a hardwired state
0x1234A5A5 = Application is in OTP machine that enables the LDOs and prepares the sys-
tem’s internal voltages.
The first word (at address 0x7FFC) is a flag which
The OTP mirroring is a hardwired state machine which
defines whether SWD (JTAG) is mapped on pins or
instructs the copying of the OTP contents into the Sys-
not. Default value is activating the SDW on the respec-
RAM even before the ARM CPU starts.
tive pins. The Length field (0x7FF8) specifies the num-
ber of 32-bit words to be copied to the SRAM. The BootROM code will only be executed when the
system is powered up or a hardware reset occurs.
The Bluetooth device address is stored at 0x7FD4 (2
32-bit words). The relation between the aforementioned sequences is
presented in the following figure:
The next field (0x7FD0) identifies the algorithm to be
used for creating a signature on the OTP payload. The
actual signature value is stored in the next fields (if a
signature algorithm is selected). This is an optional fea-
ture to guarantee trusted OTP images.
The next memory locations contain the trim values for
the XTAL16M and the RC16M oscillators. Since every
crystal is different, an extra calibration step is required
in the production line process, to identify the correct
trimming value for the XTALs so that they provide the
precision required by the Bluetooth low energy proto-
col. Since the crystal is an external component, this
step has to be performed during the calibration phase.
A similar procedure is required for the trimming of the
RC capacitance to keep the RC clock within a certain

DA14580
the status of these blocks and continues with the

power-up sequence. The timeout can be disabled by
software via SYS_CTRL_REG[TIMEOUT_DISABLE].
Power ON When no timeout occurs, the time required from the
Power/Wake-up until the state that the chip is powered
correctly and either the BootROM (in the case of a cold
Power/Wake Up Sequence start) or the OTP mirroring (in the case of a pro-
grammed wake up) takes over, is ranging from 1.2 ms
up to 1.5 ms depending on the supply voltage.
Power Up Is it Power Up or Wake Up

Wake Up ?
BootROM code booting
(includes OTP Mirroring)
Is OTP Mirroring
enabled?
Is SP pointing
Yes close to 0x00? YES
No
Remap OTP Mirroring
(Register is retainable)
SW Reset
Application SW
takes over
Figure 6: General Startup Flow
The system will enter the Power/Wake-Up sequence

after cold power up or after waking up from one of the
Sleep modes, which are described in section 4.5.2.
The distinction is done by means of a Flip-Flop which is
set to ‘1’ to indicate that the system has been just pow-
ered up (cold start). The whole process from power on
up to the point that the system starts advertising (con-
sidering a typical application) takes around 145 ms.
4.4.1 Power/Wake-Up Sequence

The Power/Wake-up sequence is a hardwired state
machine that is activated every time the system is pow-
ered up (cold start) or woken up from one of the Sleep
modes. This state machine uses information from inter-
nal analog comparators to reliably identify whether the
system is set up in BUCK (VBAT3V > 2 V) or BOOST
(VBAT1B > 0.5 V) mode automatically.
Initially, it checks whether the voltage at the VBAT1V
pin is above the threshold indicating that the system is
in BOOST mode and if so, it activates the DC-DC con-
verter accordingly. If not, it continues enabling the
Bandgap, the digital LDO and the OTP LDO to provide
a stable 1.2 V for the core and 2.4 V for the OTP cell.
Next, the XTAL16M oscillator is started while a second
check overwrites the programming of the DC-DC con-
verter in the correct mode.
Since LDOs as well as the XTAL16M oscillator take
sometime to settle, the state machine is polling on sig-
nals indicating that the startup of these blocks has
occurred successfully. However, if these signals are
not set in a timely manner, the state machine ignores

DA14580
Extended/Deep‐Sleep OFF
NO
POR
Wakeup ?
YES
Disable: BANDGAP,
DCDC-CONVERTER,
LDOs, XTAL16M
PMU_CTRL_REG
[FORCE_BOOST,
FORCE_BUCK]
FORCE_BOOST = ‘1’ FORCE_BOOST = ‘0’
FORCE_BUCK = don’t care FORCE_BUCK = ‘1’
FORCE_BOOST = ‘0’
FORCE_BUCK = ‘0’
VBAT1V > 0.5V

Is PCB BUCK or BUCK
BOOST
BOOST ?
No clear
Enable: BANDGAP, decision Enable: BANDGAP,
BOOST-
BUCK-CONVERTER,
CONVERTER,
LDO_SYS, XTAL16M
LDO_SYS, XTAL16M
‘1’
SYS_CTRL_REG
Voltages OK
[TIMEOUT_DISABLE] NO
within >64ms?
YES
‘0’
System Power UP
END
Active
Go into Extended/
Deep‐sleep
Figure 7: Power/Wake-Up Sequence
4.4.2 OTP Mirroring

This is one of the two branches of the decision regard-
ing Power-up or Wake-up as illustrated in Figure 6.
During the OTP mirroring process, the contents of the
OTP memory are copied into the SysRAM, so that the
ARM CPU can start executing code from there instead
of the power hungry OTP memory. This task is pro-
grammable (via SYS_CTRL_REG[OTP_COPY]). In
case of a Power Up, this task is performed by SW in
the BootROM, i.e. the ARM CPU takes care of the mir-
roring of the application code into the SysRAM. How-
ever, in case of a Wake-up, the BootROM code is not
executed and a small hardware state machine per-
forms the mirroring as shown in the following figure.
DA14580
can be calibrated. In the second case, the BootROM

code recognizes the OTP to be malfunctioning due to
power issues (e.g. battery life is ending and thus the
Interrupt Wake Up Start OTP LDO cannot generate the required voltages) and
continues to activate the peripherals so that the system
is still usable and can be debugged.
HW FSM activates the OTP The booting process of the DA14580 is presented in
Controller to start the following figure:
mirroring
OTP Controller starts
copying OTPC_NWORDS
words via DMA into
SysRAM
OTP Controller notifies HW
FSM that mirroring is done
HW FSM enables ARM CPU
clock
Wake Up End
Figure 8: Wake-Up OTP Mirroring
The flow chart of Figure 8 assumes that the OTP con-

troller is aware of the number of words that need to be
copied from the OTP memory. This value resides in the
OTP Header (see Table 5) and at power up will be cop-
ied by the BootROM code (i.e. the ARM CPU) into the
OTPC_NWORDS register. This is done only once,
since the OTPC_NWORDS register retains its value
even when the system goes into any of the Sleep
modes. In this way, the number of words to be trans-
ferred from the OTP memory into the SysRAM by the
OTP controller DMA engine is always available.
The typical time required for a full OTP mirroring (all
32 kB) using a trimmed RC16M clock is close to
1.2 ms.
4.4.3 BootROM Sequence

The BootROM code identifies whether the chip is in
Development mode of Normal mode by reading the
“Application Programmed” flags from the OTP header
(see Table 5). The OTP contains all zeros when it is not
programmed.
If the predefined value is identified this ensures that the
OTP is functional and that the application code has
been programmed. However, if the predefined value is
not identified, either the OTP is not programmed (all
zeros) or the OTP memory is not operational (random
data).
In the first case, the system enters Development mode
where the application can be developed and values

DA14580
Default clock is
XTAL16M
Boot start
Avoid voltage
drops due to Wait for 100 ms
battery contact
Switch to RC16M
No (timeout 64 ms)
Enable OTP LDO
OTP LDO
voltage OK?
Yes OR timeout
Read OTP “Application Flags”
OTP not
programmed but
Magic Number
App operational
identified App
Yes programmed No Flag=0x0000 Yes
Calibration has
? ? been performed
Calibration has
been performed once
once Calibration Calibration
Flag=0xA5A5 Flag=0xA5A5
? ?
Yes
Yes
MODE
CALIBRATION
Read from OTP
and program Read and program Read and program
registers on the trim values
PD_AON domain No respective trim values No
No
Read and program
32 kHz source config.
Length register
will be
Switch to XTAL16M
automatically
Read and program
read by the OTP
controller after DMA length
Initialise peripheral
wake-up
devices
Enable/disable JTAG
Start copy of Boot from Ext SPI

Yes
OTP to SRAM SPI Master Master?
No No
ARM is polling
OTPC_STAT_REG
Copy Boot from
Yes UART?
done? UART
No
Yes
NORMAL MODE
Run patching function Boot from Ext SPI

Yes
If the application SPI Slave Slave?
is built for having
SysRAM at
address 0x00, No No
the stack pointer
will point to an Boot from
address relative Yes I2C?
DEVELOPMENT MODE
I2C
to 0x00
SP  Download code No
Enable watchdog
0x2000... to SRAM
5 times
No Yes
looped?
Remap SysRAM to address
0x00 and SW reset Enable JTAG
Yes
Boot end
Figure 9: BootROM Sequence

DA14580
When in Development Mode, the BootROM code ini- When in Normal Mode, the ARM CPU programs OTP
tializes all peripheral devices from which the DA14580 header configuration information into actual registers,
might download code: UART, SPI (both Master and some of them retaining this value even if the system
Slave) and I2C. The code searches for a valid enters one of the Sleep modes. Next, the actual Appli-
response on various combinations of I/Os one after the cation Code is mirrored into the System RAM and the
other. The step sequence and GPIO mapping is pre- patching function is executed to ensure that SW
sented in the following tables: updates are applied. The patching mechanism is
described in detail in Application Note AN-B-002.
Table 6: Development Mode Peripheral Pin Finally, the Remap register
Mapping (SYS_CTRL_REG[REMAP_ADR0]) is programmed to
ensure that address zero is now pointing to the System
Signal Step A Step B Step C Step D RAM.
SPI SCK P0_0 P0_0 A SW reset as a last step, instructs the ARM CPU to
Master CS P0_3 P0_1 reboot running code from the SRAM.
MISO P0_6 P0_2 4.5 POWER SUPPLY CONFIGURATION
MOSI P0_5 P0_3
4.5.1 Power Domains
UART TX P0_0 P0_2 P0_4 P0_6
The DA14580 comprises several different power
RX P0_1 P0_3 P0_5 P0_7
domains, that are controlled by power switching ele-
SPI SCK P0_0 ments, thus eliminating leakage currents by totally
Slave CS P0_3 powering them down. The partitioning of the
DA14580’s resources with respect to the various power
MOSI P0_6 domains is presented in the following table:
MISO P0_5
I2C SCL P0_0 P0_2 P0_4 P0_6
SDA P0_1 P0_3 P0_5 P0_7 Table 8: Power Domains
Power
Description
Domain
Table 7: Development Mode Peripheral Search PD_AON Always ON: This power line connects
Sequence to all the resources that must be pow-
ered constantly: the ARM/WIC, the
Sequence Action LLP/Timer, the Retention SRAM, the
PMU/CRG, the Capture Timer, the
0 SPI Master Step A Quadrature Decoder, the padring and
1 SPI Master Step B various registers required for the Wake
Up sequence.
2 UART Step A
PD_SYS System: This power line connects to all
3 UART Step B
the resources that should be powered
4 UART Step C only when the ARM M0 is running:
5 UART Step D the AHB bus, the OTP cell and control-
lers, the ROM, the System RAM the
6 SPI Slave Step A Watchdog, the SW Timer and the GPIO
7 I2C Step A port multiplexing.
8 I2C Step B PD_PER Peripherals: This power line connects
9 I2C Step C to the peripherals that can be switched
off after completing their operation: the
10 I2C Step D UARTs, the SPI, the I2C the Keyboard
controller and the ADC.
At each step, the BootROM code sends a certain char- PD_DBG Debug: Powers the debug part of the
acter to the peripheral controller waiting for an answer. ARM Cortex-M0 processor.
If no answer is received within a certain amount of
time, a timeout instructs the code to continue to the PD_RAD Radio: This is the power domain that
next step. If a response is detected, a specific protocol includes the digital part of the Radio
is executed and communication between the DA14580 (DPHY) and the BLE Core.
and the external device is established. The protocol The power management of the Radio
and the timeout values are described in detail in Appli- (RF) subsystem is controlled via sev-
cation Note AN-B-001. eral dedicated LDOs.

DA14580
Table 8: Power Domains off except for the PD_AON, the programmed
PD_RRx and the PD_SR. Since the SysRAM
Power retains its data, not OTP mirroring is required
Description
Domain upon waking up the system.
PD_RR Retention_RAM: This is a separate 4. Deep Sleep Mode: All power domains are off
power line that only controls the 2 kB except for the PD_AON and the programmed
Retention SRAM. If this memory cell is PD_RRx. This mode dissipates the minimum
not needed, it should always be OFF. leakage power. However, since the SysRAM has
PD_RR2 Retention_RAM2: This is a separate not retained its data, an OTP mirror action is
power line that only controls the 3 kB required upon waking up the system.
Retention SRAM. If this memory cell is The first two power modes do not include any special
not needed, it should always be OFF power gating or manipulation of power domains. The
PD_RR3 Retention_RAM3: This is a separate Extended Sleep and Deep Sleep modes are activated
power line that only controls the second in almost the same way with a small difference. The
2 kB Retention SRAM. If this memory entering into the Extended Sleep and Deep Sleep
cell is not needed, it should always be modes is summarized in the following table:
OFF
PD_RR4 Retention_RAM4: This is a separate
power line that only controls the 1 kB Table 9: Activating Power Modes
Retention SRAM. If this memory cell is
not needed, it should always be OFF Power
Activation Steps
Mode
PD_SR System_RAM: This is a separate
power line that only powers the 42 kB Extended SYS_CTRL_REG[RET_SYSRAM] = 1;
SysRAM. This power line keeps the Sleep SCB->SCR |= 1<<2;
SysRAM’s contents retained but not enables the SLEEPDEEP bit on the Sys-
accessible. tem Control Register of the ARM CPU
Deep SCB->SCR |= 1<<2;
4.5.2 Power Modes Sleep enables the SLEEPDEEP bit on the Sys-
There are four different power modes in the DA14580: tem Control Register of the ARM CPU
1. Active Mode: System is active and operates at

However, the above Power modes which involve power
full speed.
gating do not turn off all power domains automatically.
2. Sleep Mode: No power gating has been pro- Certain power domains need to be powered off prior to
grammed, the ARM CPU is idle, waiting for an activating the Extended Sleep or Deep Sleep modes.
interrupt. PD_SYS is on. PD_PER and The following table summarizes the effect of the
PED_RAD depending on the programmed Extended/Deep Sleep mode activation with regards to
enabled value. specific power domains.
3. Extended Sleep Mode: All power domains are
Table 10: Power Domain Manipulation when Activating Extended Sleep or Deep Sleep Mode
Power
PD_SYS PD_PER PD_DBG PD_RAD PD_RRx PD_SR Analog
Mode
Extended Automati- Must be pro- Automati- Must be pro- Must be pro- Automati- Automati-
Sleep cally OFF grammed cally OFF grammed grammed cally ON cally OFF
Deep Automati- Must be pro- Automati- Must be pro- Must be pro- Automati- Automati-
Sleep cally OFF grammed\ cally OFF grammed grammed cally OFF cally OFF
The “Analog” column in Table 10 refers to the Band- amount of data transmitted or received per connection.
gap, the DC-DC converter, the XTAL16M oscillator, the Based on these parameters a time threshold for the
RC oscillators, the ADC and the respective LDOs. connection interval can be calculated, above which
These blocks are not part of a single power domain but Deep Sleep mode performs better than Extended
the HW will turn them off upon activation of either the Sleep mode. This is elaborated upon in Application
Extended Sleep or the Deep Sleep mode. Note AN-B-008.
The use of the Extended Sleep vs. the Deep Sleep
4.5.3 Retention Registers
mode depends heavily on the Bluetooth low energy
application and its specific parameters such as the A number of the registers in the DA14580 needs to
required connection interval, the duty cycle and the retain their values when the system enters one of the

DA14580
Sleep modes described in the previous section. These

registers and their power domains are described in the
following table.
Table 11: Retention Registers and Power Domains
Address Range
Power Domain Retention Register Notes
Start End
PD_RAD 0x4000.0000 0x4000.7FFF BLE_CNTL2_REG Retained bit fields are:
BLE_RSSI_SEL
SW_RPL_SPI
BB_ONLY
RADIO_ONLY
BLE_CLK_SEL
RADIO_PWRDN_ALLOW
MON_LP_CLK
DIAGPORT_REVERSE
DIAGPORT_SEL
EMACCERRMSK
EMACCERRSTAT
DEBUG_REG Retained bit fields are:
DEBUGS_FREEZE_EN
PD_SYS 0x4000.8000 0x4000.83FF OTPC_NWORDS_REG Contains the number of
words to be copied from the
OTP memory into the Sys-
RAM.
0x5000.3000 0x5000.3FFF GP_CONTROL_REG Retained bit fields are:
EM_MAP
PD_AON 0x5000.0000 0x5000.0FFF All registers are retainable
PD_PER 0x5000.1000 0x5000.1FFF No registers are retainable

DA14580
5 Reset The typical latency of the RST pad is in the range of

2 s.
The DA14580 comprises an RST pad which is active
high. It contains an RC filter for spikes suppression 5.1 POR, HW AND SW RESET
with 400 k and 2.8 pF for the resistor and the capaci-
The Power On Reset (POR) signal is generated inter-
tor respectively. It also contains a 25 k pull-down
nally and will release the system’s flip flops as soon as
resistor. This pad should be connected to ground if not
the VDD voltage crosses the minimum threshold value.
needed by the application. The response is illustrated
There are two main reset signals in the DA14580, both
in the following figure which displays the voltage (V) on
active high. The HW reset which is basically triggered
the vertical axis and the time (s) on the horizontal
by the RST pad and the SW reset which is triggered by
axis:
writting the SYS_CTRL_REG[SW_RESET] bit.
The HW reset can also be automatically activated upon
1.4V
waking up of the system from an Extended Sleep or
1.2V Deep Sleep mode by programming bit
1V
PMU_CTRL_REG[RESET_ON_WAKEUP]. The HW
reset will basically run the cold start-up sequence and
0.8V the BootROM code will be executed.
0.6V
The SW reset is the logical OR of a signal from the
0.5V ARM CPU (triggered by writing SCB->AIRCR =
0.2V
0x05FA0004) and the SYS_CTRL_REG[SW_RESET]
bit. This is mainly used to reboot the system after the
0
0 1us 2us 3us 4us 5us base address has been remapped.
Certain registers are reset by POR only or by POR and
Pad_reset_signal RC Reset_signal_to_core
the HW reset signal, but not by the SW reset. These
registers are listed in the following table:
Figure 10: RST Pad Latency
Table 12: Reset Signals and Registers
Reset by POR Only Reset by POR or HW Reset Reset by POR, HW or SW Reset

OTPC_NWORDS_REG CLK_FREQ_TRIM_REG The rest of the Register File
BANDGAP_REG CLK_RADIO_REG
RF registers containing the trimming All RF calibration registers
values for the VCO, the LNA and the BLE_CNTL2_REG
I/O capacitance
CLK_CTRL_REG
PMU_CTRL_REG
SYS_CTRL_REG
CLK_32K_REG_I
CLK_16M_REG_I
CLK_RCX32K_REG
TRIM_CTRL_REG
DEBUG_REG[DEBUGS_FREEZE_EN]
GP_CONTROL_REG[EM_MAP]

DA14580
6 ARM Cortex-M0 avoids the overhead of switching between two instruc-

tion sets.
The Cortex-M0 processor is a 32-bit Reduced Instruc-
tion Set Computing (RISC) processor with a von Neu- In total, the Cortex-M0 processor supports only 56
mann architecture (single bus interface). It uses an base instructions, although some instructions can have
instruction set called Thumb, which was first supported more than one form. Although the instruction set is
in the ARM7TDMI processor; however, several newer small, the Cortex-M0 processor is highly capable
instructions from the ARMv6 architecture and a few because the Thumb instruction set is highly optimized.
instructions from the Thumb-2 technology are also Academically, the Cortex-M0 processor is classified as
included. Thumb-2 technology extended the previous load-store architecture, as it has separate instructions
Thumb instruction set to allow all operations to be car- for reading and writing to memory, and instructions for
ried out in one CPU state. The instruction set in arithmetic or logical operations that use registers.
Thumb-2 includes both 16-bit and 32-bit instructions;
most instructions generated by the C compiler use the A simplified block diagram of the Cortex-M0 is shown
16-bit instructions, and the 32-bit instructions are used in Figure 11.
when the 16-bit version cannot carry out the required
operations. This results in high code density and
Power Management
Interface
Interrupt Request
and NMI
Connection to
W akeUp Interrupt Controller Serial-W ire Debugger
(W IC) Debug Interface
Nested Vector
Interrupt Processor Debug
Controller Core Subsystem
(NVIC)
Internal Bus System
AHB Lite bus interface unit
Memory and Peripherals
Figure 11: ARM Cortex-M0 Block Diagram
Features • The design is configured to respond to exceptions

(e.g. interrupts) as soon as possible (minimum 16
• Thumb instruction set. Highly efficient, high code
clock cycles).
density and able to execute all Thumb instructions
from the ARM7TDMI processor. • Non maskable interrupt (NMI) input for safety critical
systems.
• High performance. Up to 0.9 DMIPS/MHz (Dhrys-
tone 2.1) with fast multiplier. • Easy to use and C friendly. There are only two
modes (Thread mode and Handler mode). The
• Built-in Nested Vectored Interrupt Controller (NVIC).
whole application, including exception handlers, can
This makes interrupt configuration and coding of
be written in C without any assembler.
exception handlers easy. When an interrupt request
is taken, the corresponding interrupt handler is exe- • Built-in System Tick timer for OS support. A 24-bit
cuted automatically without the need to determine timer with a dedicated exception type is included in
the exception vector in software. the architecture, which the OS can use as a tick
timer or as a general timer in other applications with-
• Interrupts can have four different programmable pri-
out an OS.
ority levels. The NVIC automatically handles nested
interrupts. • SuperVisor Call (SVC) instruction with a dedicated
SVC exception and PendSV (Pendable SuperVisor
DA14580
service) to support various operations in an embed- • Supports Serial Wire Debug (SWD) connections.
ded OS. The serial wire debug protocol can handle the same
debug features as the JTAG, but it only requires two
• Architecturally defined sleep modes and instructions
wires and is already supported by a number of
to enter sleep. The sleep features allow power con-
debug solutions from various tools vendors.
sumption to be reduced dramatically. Defining sleep
modes as an architectural feature makes porting of • Four (4) hardware breakpoints and two (2) watch
software easier because sleep is entered by a spe- points.
cific instruction rather than implementation defined
• Breakpoint instruction support for an unlimited num-
control registers.
ber of software breakpoints.
• Fault handling exception to catch various sources of
• Programmer’s model similar to the ARM7TDMI pro-
errors in the system.
cessor. Most existing Thumb code for the
• Support for 24 interrupts. ARM7TDMI processor can be reused. This also
makes it easy for ARM7TDMI users, as there is no
• Little endian memory support.
need to learn a new instruction set.
• Wake up Interrupt Controller (WIC) to allow the pro-
cessor to be powered down during sleep, while still 6.1 INTERRUPTS
allowing interrupt sources to wake up the system. This section lists all 24 interrupt lines, except the NMI
• Halt mode debug. Allows the processor activity to interrupt, and describes their source and functionality.
stop completely so that register values can be The overview of the interrupts is illustrated in the fol-
accessed and modified. No overhead in code size lowing table:
and stack memory size.
• CoreSight technology. Allows memories and periph-
erals to be accessed from the debugger without halt-
ing the processor.
Table 13: Interrupt List
IRQ
Number
IRQ Name Description
(Inherent
Priority)
0 BLE_WAKEUP_LP_IRQn Wake-up from Low Power (Deep Sleep) interrupt from BLE.
1 BLE_FINETGTIM_IRQn Fine Target Timer interrupt generated when Fine Target timer expired.
Timer resolution is 625 s base time reference.
2 BLE_GROSSTGTIM_IRQn Gross Target Timer interrupt generated when Gross Target timer expired.
Timer resolution is 16 times 625 s base time reference.
3 BLE_CSCNT_IRQn 625 s base time reference interrupt, available in active modes.
4 BLE_SLP_IRQn End of Sleep mode interrupt.
5 BLE_ERROR_IRQn Error interrupt, generated when undesired behavior or bad programming
occurs in the BLE Core.
6 BLE_RX_IRQn Receipt interrupt at the end of each received packets.
7 BLE_EVENT_IRQn End of Advertising / Scanning / Connection events interrupt.
8 SWTIM_IRQn Software Timer interrupt.
9 WKUP_QUADEC_IRQn Combines the Wake up Capture Timer interrupt, the GPIO interrupt and
the QuadDecoder interrupt
10 BLE_RF_DIAG_IRQn Baseband or Radio Diagnostics Interrupt. Triggered by internal events of
the Radio or Baseband selected by the BLE_RF_DIAGIRQ_REG. For
Debug purposes only.
11 BLE_CRYPT_IRQn Encryption / Decryption interrupt, generated either when AES and/or
CCM processing is finished.
12 UART_IRQn UART interrupt.
13 UART2_IRQn UART2 interrupt.
14 I2C_IRQn I2C interrupt.
15 SPI_IRQn SPI interrupt.

DA14580
Table 13: Interrupt List
IRQ
Number
IRQ Name Description
(Inherent
Priority)
16 ADC_IRQn Analog-Digital Converter interrupt.
17 KEYBRD_IRQn Keyboard interrupt.
18 RFCAL_IRQn RF Calibration Interrupt.
19 GPIO0_IRQn GPIO interrupt through debounce.
Interrupt priorities are programmable by the ARM Cor- The default SysTick Timer configuration will be using
tex-M0. The lower the priority number, the higher the the (fixed) external reference clock STCLKEN
priority level. The priority level is stored in a byte-wide (STCSR[CLKSOURCE]=0). When necessary, higher
register, which is set to 0x0 at reset. Interrupts with the clock frequencies can be used with STCSR[CLK-
same priority level follow a fixed priority order using the SOURCE]=1 but the software should take the
interrupt number listed in Table 13 (lower interrupt HCLK_DIV dependent core clock SCLK into account
number has higher priority level). w.r.t. the timing.
To access the Cortex-M0 NVIC registers, CMSIS func- 6.3 WAKE-UP INTERRUPT CONTROLLER
tions can be used. The input parameter IRQn of the
CMSIS NVIC access functions is the IRQ number. This The Wake-up Interrupt Controller (WIC) is a peripheral
can be the IRQ number or (more convenient) the corre- that can detect an interrupt and wake the processor
sponding IRQ name listed in Table 13. The corre- from deep sleep mode. The WIC is enabled only when
sponding interrupt handler name in the vector table for the DEEPSLEEP bit in the SCR is set to 1 (see System
IRQ#15 is e.g. SPI_Handler. For more information on Control Register on page 4-16 of the Cortex-M0 User
the ARM Cortex-M0 interrupts and the corresponding Guide Reference Material).
CMSIS functions, see a.o. section 4.2 Nested Vectored The WIC is not programmable, and does not have any
Interrupt Controller on pag. 4-3 in the Cortex™-M0 registers or user interface. It operates entirely from
User Guide Reference Material. hardware signals. When the WIC is enabled and the
The Watchdog interrupt is connected to the NMI input processor enters deep sleep mode, the power man-
of the processor. agement unit in the system can power down most of
the Cortex-M0 processor. This has the side effect of
6.2 SYSTEM TIMER (SYSTICK) stopping the SysTick timer. When the WIC receives an
interrupt, it takes a number of clock cycles to wake-up
The Cortex-M0 System Timer (SysTick) can be config- the processor and restore its state, before it can pro-
ured for using 2 different clocks. The SysTick Control & cess the interrupt. This means interrupt latency is
Status (STCSR) register specifies which clock should increased in Deep Sleep mode.
be used by the counter.
STCSR[CLKSOURCE]=0; use the (fixed) external ref- 6.4 REFERENCE
erence clock STCLKEN of 1 MHz. For more information on the ARM Cortex-M0, see the
ARM documents listed in Table 14.
STCSR[CLKSOURCE]=1; use the (HCLK_DIV depen-
dent) processor clock SCLK (e.g. 2, 4, 8 or 16 MHz).
Table 14: ARM Documents List
Document Title ARM Document Number

1 Cortex™-M0 User Guide Reference Material ARM DUI 0467B (available on the ARM website)
2 Cortex™-M0 r0p0 Technical Reference Manual ARM DDI 0432C (available on the ARM website)
3 ARMv6-M Architecture Reference Manual ARM DDI 0419C (can be downloaded by registered
ARM customers)

DA14580
7 AMBA Bus Overview The AMBA bus organization is presented in the follow-
ing figure:
The DA14580 is based on an AMBA 2.0 AHB and APB
components. The AHB is an AMBA Lite version which
requires a single master on the system, i.e. in the
DA14580 the ARM CPU. The APB interface imple-
ments 3 different decoding slaves which are grouped
according to the power domain structure of the chip.
GPIO
SYSTEM
PD_AON
WakeUp Timer SW Timer
AON
Quad Decoder GPRG
PMU/CRG WatchDog
APB UART
PD_RRx
UART2
PD_PER
RET ROM Bridge
PERIPH
RAMs I2C
Memory
AMBA APB
AMBA AHB SPI
Controller
Sys
PD_SR
ADC
RAM
OTP
Access from Controller
PD_RAD
BLE Controller AHB master RFCU
& Memory
BLE Controller
Remap
Patch
AHB master
ARM M0 Access to Memory
Controller
PD_SYS
Figure 12: AMBA Bus Architecture and Power Domains
Since the DA14580 consists of several different power The rest of the system is mapped on the system power
domains that are digitally controlled and can be shut domain and contains APB blocks (the GPIO multiplex-
down completely, various slave resources especially ing, the Software Timer, the General Purpose Regis-
on the APB bus are grouped together to reduce signal ters and the WatchDog timer) as well as AHB blocks
isolation requirements. (OTP, Memory and ROM controller).
On the AHB Lite bus, the CPU is the master while OTP,
BLE Core, Memory and ROM controllers are the
slaves. Furthermore, on the APB subsystem, the
Always On power domain consists of the following
blocks:
• Wake-up Timer
• Quadrature Decoder
• Power Management Unit / Clock Reset Generator
• Retention RAMs (not mapped on APB but accessi-
ble through the Memory Controller)
The APB peripherals power domain comprises:
• UART and UART2
• SPI
• I2C
• GP ADC
The radio power domain contains both AHB and APB
peripherals i.e. the Radio Frequency Control Unit
(RFCU) and the Bluetooth Low Energy controller.

DA14580
8 Patch Block Features

The patch block provides a multiplexer on the databus • Direct patching on ROM databus
of the ROM Controller able to modify (patch) the con- • Up to 8x 32 bit patch entries
tents of the data read from ROM. This feature provides
a repair mechanism of a ROM image. • Enable/disable patch entries
• Priority scheme allows off-loads software
• Patch data can be stored internally in OTP or exter-
nally in EEPROM or QSPI
ROM 0
AHB32
PATCH_DATAx_REG 1 AHB32
(data)
Address Comparator
Match[x]
PATCH_ADDRx_REG
PATCH_VALID_REG
PATCH_VALID_SET_REG
PATCH_VALID_RESET_REG
Figure 13: Patch Block
The patch block’s registers are accessible via the AHB Disabling/Enabling Patch Entries
bus. The patch unit resides in the System Power
Patch entries can be disabled by writing a ‘1’ to the
domain. It is clocked by the system bus clock (HCLK)
write-only register PATCH_VALID_RESET_REG[x].
and must be initialized after each power-up.
Disabled entries can be re-enabled by writing a ‘1’ to
There are 8 patching entries of two 32-bit words each. write-only register PATCH_VALID_SET_REG[x]
A patch entry consists of a 32-bit address register
To introduce new patches, the SW must check the
PATCH_ADDRx_REG and one 32-bit data register
available patch entries, evaluate the priorities (e.g. if it
PATCH_DATAx_REG, implemented as sequential reg-
will use two patch entries for the same 32-bit address)
ister pairs. The programmer must program the address
and program the corresponding register pair.
register first followed by the data register. As soon as
both registers are written, the corresponding bit
PATCH_VALID_REG[x] is automatically set.
Patch Address Comparators
The patch unit has an octal address comparator to
compare AHB address bus with PATCH_ADDRx_REG
With enabled patch entries, upon an address match,
the data bus value is replaced with the corresponding
PATCH_DATAx_REG. Matching uses priorities starting
with highest priority at the last entry
(PATCH_ADDR7_REG) and lowest priority at the first
entry (PATCH_ADDR0_REG). This priority scheme
helps SW to add more patches without having to check
the previous entries with a lower entry number.

DA14580
9 Memory Map
Table 15: Memory Map
Address Description
0x00000000 Boot/BLE ROM
0x00014FFF Contains 6 kB of Boot ROM code and 78 kB of Bluetooth low energy protocol related code
0x00015000 RESERVED
0x0001FFFF
0x00020000 Boot/BLE ROM
0x00034FFF Contains 6 kB of Boot ROM code and 78 kB of Bluetooth low energy protocol related code
0x00035000 RESERVED
0x0003FFFF
0x00040000 OTP
0x00047FFF Contains the OTP cell actual memory space
0x00048000 RESERVED
0x0007FFFF
0x00080000 Retention RAM (Note 2)
0x000807FF 2 kB of retained memory space.
0x00080800 Retention RAM2 (Note 2)
0x000813FF 3 kB of retained memory space.
0x00081400 Retention RAM3 (Note 2)
0x00081BFF 2 kB of retained memory space.
0x00081C00 Retention RAM4 (Note 2)
0x00081FFF 1 kB of retained memory space.
0x00082000 RESERVED
0x1FFFFFFF
0x20000000 System RAM (Note 2)
0x2000A7FF 42 kB. Contains OTP code, data for the application
0x2000A800 RESERVED
0x3FFFFFFF
0x40000000 AHB/BLE-Regs
0x40007FFF Contains the control registers of the Bluetooth low energy Link Layer Processor
0x40008000 AHB/OTP-Regs
0x400083FF Contains the control registers of the OTP Subsystem
0x40008400 AHB/Patch-Regs
0x400087FF Contains the registers for the HW patching
0x40008800 RESERVED
0x4FFFFFFF
0x50000000 APB/PMU-CRG
0x500000FF Contains the control registers of the Power Management Unit and the Clock Generator
0x50000100 APB/wake-up
0x500001FF Contains an event capture timers that can wake up the system
0x50000200 APB/Quadrature Decoder
0x500002FF Contains Logic that implements a step counter for X and Y axis from a rotary encoder
0x50000300 RESERVED
0x50000FFF
0x50001000 APB/UART
0x500010FF Contains the control registers of the UART
0x50001100 APB/UART2
0x500011FF Contains the control registers of the UART2
0x50001200 APB/SPI
0x500012FF Contains the control registers of the SPI interface

DA14580
Table 15: Memory Map
Address Description
0x50001300 APB/I2C
0x500013FF Contains the control registers of the I2C interface
0x50001400 APB/Kbrd
0x500014FF Contains the registers of the Keyboard controller
0x50001500 APB/ADC
0x500015FF Contains the registers of the 4 channels ADC
0x50001600 APB/AnaMisc
0x500016FF Contains registers for various analog blocks
0x50001700 RESERVED
0x50001FFF
0x50002000 APB/Radio
0x50002FFF Contains the control registers of the Bluetooth low energy Radio
0x50003000 APB/Ports
0x500030FF Contains the mode and direction registers of the GPIOs
0x50003100 APB/Watchdog
0x500031FF Contains the control registers of the Watchdog timer
0x50003200 APB/Version
0x500032FF Contains the version/revision of the chip
0x50003300 APB/Gen Purpose
0x500033FF Contains general purpose control registers
0x50003400 APB/Timer
0x500034FF Contains the control registers of the SW Timer
0x50003500 RESERVED
0xDFFFFFFF
0xE0000000 Internal Private Bus
0xE00FFFFF Contains various registers of the ARM Cortex-M0
Note 1: 1 kB = 1024 bytes. 1 Mbit = 1024*1024 bits. 1 GB = 1024*1024*1024 bytes.

Note 2: For Exchange memory configurations please refer to Figure 61.

DA14580
10 Memory Controller • The BLE Controller. This master can also access
both resources through its proprietary memory bus.
The Memory Controller implements smart multiplexing
and arbitration of three different masters accessing 2 The block diagram is presented in Figure 14.
memory resources, namely the System RAM and the Features
Retention RAM cells. The masters that require access
to these memories are: • Meets all timing constraints for any access to the
physical cells.
• The CPU over the system AHB bus. This master has
full access to both resources. • Transparently interfaces AHB busses to memory sig-
nalling
• The OTP Controller. This master can access the
System RAM only through a dedicated AHB bus. • Fixed arbitration algorithm with time sharing.
OTP AHB Bus System AHB Bus
BLE memory bus
Arbiter Arbiter
RetRAM2 3KB
RetRAM3 2KB
RetRAM4 1KB
RetRAM 2KB
System
RAM
42KB
Memory Controller
Figure 14: Memory Controller Block Diagram
10.1 ARBITRATION
The arbitration is a mixture of highest priority and a fair
use policy. If more masters request access, time divi-
sion is employed. This to make sure none of the bus-
ses is able to stall another for a long period. The OTP
and BLE accesses are handled as very critical and
therefore they have highest priority. In general BLE and
OTP accesses are mutual exclusive i.e. no BLE
accesses occur while OTP requests. OTP has highest
priority and will only occur during the OTP mirroring i.e.
the system has not yet started executing application
code. When OTP mirroring is done, BLE gets highest
priority and only one every 3 cycles the CPU is allowed
to get access. If none of the interfaces requests
access, the IDLE or power down state is selected.

DA14580
11 Clock Generation
CLK_FREQ_TRIM_REG
11.1 CRYSTAL OSCILLATORS
The Digital Controlled Xtal Oscillator (DXCO) is a 10 9 8 7 6 ... 1 0
Pierce configured type of oscillator designed for low
power consumption and high stability. There are two
such crystal oscillators in the system, one at 16 Decoding
MHz(XTAL16M) and a second at 32.768 kHz 3 --> 7
(XTAL32K). The 32.768 kHz oscillator has no trimming
capabilities and is used as the clock of the Extended/ ...
Deep Sleep modes. The 16 MHz oscillator can be
trimmed.
The principle schematic of the two oscillators is shown ...
in Figure 15 below. No external components to the 3.2 pF 3.2 pF 1.6 pF ... 27 fF 13 fF
DA14580 are required other than the crystal itself. If
the crystal has a case connection, it is advised to con-
nect the case to ground.
Figure 16: Frequency Trimming
16 MHz 32.768 kHz Table 16: CLK_FREQ_TRIM_REG Decoding 3 --> 7

XTAL16Mm
XTAL32Km
XTAL16Mp
XTAL32Kp
Input[2:0] Output[6:0]
2 1 0 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1
0-22.4 pF
0 1 0 0 0 0 0 0 1 1
0 1 1 0 0 0 0 1 1 1
clock16MHz 1 0 0 0 0 0 1 1 1 1
clock32kHz
1 0 1 0 0 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1
Figure 15: Crystal Oscillator Circuits 1 1 1 1 1 1 1 1 1 1
11.1.1 Frequency Control (16 MHz Crystal) Trimming might cause phase jumps in the oscillator
signal. To reduce these phase jumps the user should
Register CLK_FREQ_TRIM_REG controls the trim-
only change one switch at a time (this especially
ming of the 16 MHz crystal oscillator. The frequency is
applies to the seven larger capacitors). Use bits 10 to 8
trimmed by two on-chip variable capacitor banks. Both
for coarse adjustment and always increment or decre-
capacitor banks are controlled by the same register.
ment this value by 1. Wait approximately 200 s to
The capacitance of both variable capacitor banks var- allow the adjustment to settle.
ies from minimum to maximum value in 2048 equal
Bits 7...0 are used for fine adjustment.
steps. With CLK_FREQ_TRIM_REG = 0x000 the max-
imum capacitance and thus the minimum frequency is As an example, the recommended way to change the
selected. With CLK_FREQ_TRIM_REG = 0x7FF the frequency trim register from 0x7FF to 0x100 is first to
minimum capacitance and thus the maximum fre- decrement the value of the three most significant bits
quency is selected. by 1 at a time, and then change the least significant
bits until the desired frequency is reached:
The eight least significant bits of
0x7FF --> 0x6FF -->0x5FF --> 0x4FF --> 0x3FF -->
CLK_FREQ_TRIM_REG directly control eight binary
0x2FF --> 0x1FF --> 0x100.
weighted capacitors, as shown in Figure 16. The three
most significant bits are decoded according to Table
11.1.2 Automated Trimming Mechanism
16. Each of the seven outputs of the decoder controls a
capacitor (value is 256 times the value of the smallest There is provision in the DA14580 for automating the
capacitor). actual trimming of the 16 MHz crystal oscillator. This is
a special hardware block that realizes the XTAL trim-
ming in a single step.

DA14580
Two programmable parameters are involved in the 11.2.1 Frequency Calibration

trimming of the XTAL16M oscillator:
The output frequency of the 32 kHz crystal oscillator
• TRIM_CTRL_REG[TRIM_TIME] and the three RC-oscillators can be measured relative
This field controls the time that elapses between the to the 16 MHz crystal oscillator using the on-chip refer-
enabling of the XTAL and the application of the trim ence counter.
value specified by CLK_FREQ_TRIM_REG. The
The measurement procedure is as follows:
TRIM_TIME value counts cycles of 250 s. As soon
as TRIM_TIME*250 s time has passed, the 1. REF_CNT_VAL = N (the higher N, the more
SYS_STAT_REG[XTAL16_TRIM_READY] bit accurate and longer the calibration will be)
becomes ‘1’. This is the point that the trim value will
2. CLK_REF_SEL_REG = 0x0006 (XTAL32K) or
be applied at the oscillator. If TRIM_TIME = 0000 the
CLK_REF_SEL_REG = 0x0005 (RC16M) or
trim value is applied immediately when XTAL16M
CLK_REF_SEL_REG = 0x0004 (RC32K) or
starts up, to reduce time.
CLK_REF_SEL_REG = 0x0007 (RCX)
• TRIM_CTRL_REG[SETTLE_TIME]
3. Wait until
This field controls a counter that counts 250 s inter-
CLK_REF_SEL_REG[REF_CAL_START] = 0
vals starting when XTAL16_TRIM_READY has been
asserted. Upon completion of the SETTLE_TIME 4. Read CLK_REF_VAL_H_REG and
periods, the XTAL_SETTLED bit in the CLK_REF_VAL_H_REG = M (32-bits values)
SYS_STAT_REG becomes ‘1’, indicating that
5. Frequency = (N/M) * 16 MHz
XTAL16M clock is settled and trimmed and may be
safely used as the system clock. In the case of using the RCX as a sleep clock, the fre-
quency calibration should be implemented on each
An initial manual frequency measuring action is
active time of a connection interval to guarantee cor-
required to store the wanted value in the OTP header
rect operation.
(See "OTP Memory Layout" on page 11).
11.2 RC OSCILLATORS
There are 3 RC oscillators in the DA14580: one provid-
ing 16 MHz (RC16M), one providing 32 kHz (RC32K)
and one providing a frequency in the range of 10.5 kHz
(RCX).
The 16 MHz RC oscillator is powered by the Digital
LDO i.e. the VDD = 1.2 V which is available for the core
logic during Active or Sleep mode. The output clock is
slightly slower than 16 MHz and is used to clock the
system during the OTP mirroring procedure after wake-
up, while the XTAL16M oscillator is settling. It is impor-
tant to keep the 16 MHz RC oscillator at a frequency
equal or below 16 MHz to guarantee correct behavior
of the digital circuits. This is why the reset value of
CLK_16M_REG[RC16M_TRIM] is equal to the mini-
mum value.
The simple RC oscillator (RC32K) operates on
VDD = 1.2 V and provides 32 kHz. The enhanced RC
oscillator (RCX) provides a stable 18 kHz and operates
only if the external voltage is > 1.8 V (i.e. either on pin
VBAT1V in BOOST mode or on pin VBAT3V in BUCK
mode). The main usage of the RC32K oscillator is for
internal clocking during startup.
The RCX oscillator can be used to replace a
32.768 kHz crystal, since it has a precision of
< 500 ppm, while its output frequency is quite stable
over temperature. Although a different frequency is
used, the accuracy is good enough to ensure that the
correct number of slots (625 s) is counted for the
Sleep time.

DA14580
11.3 SYSTEM CLOCK GENERATION XTAL32Kp/XTAL32Km for the 16 MHz and 32.768 kHz
The DA14580 clock generation overview is presented oscillators respectively.
in the following figure. External clock sources of the
device are pins XTAL16Mp/XTAL16Mm and pins
CLK_AMBA_REG[OTP_ENABLE]
otp_clk
CLK_PER_REG[WAKEUPCT_ENABLE]
CLK_CTRL_REG[SYS_CLK_SEL] wakeupct_clk
Divide by
XTAL16M apb_clk
PCLK_DIV
OSC System
0 hclk clocks
RC16M sys_clk Divide by
1 ble_hclk
OSC HCLK_DIV
2
CLK_RCX20K_REG[RCX20K_SELECT]
arb_clk
CLK_PER_REG[SPI_ENABLE]
Divide by
RC32K spi_clk
SPI_DIV
OSC 0 CLK_PER_REG[I2C_ENABLE]
i2c_clk
RCX 1 0 CLK_PER_REG[UART1_ENABLE]
OSC
uart_clk
1 CLK_PER_REG[UART2_ENABLE]
XTAL32K
uart2_clk
OSC
CLK_PER_REG[QUAD_ENABLE]
SYS_CTRL_REG[CLK32_SOURCE] quad_clk
CLK_PER_REG[TMR_ENABLE]
TIMER0_CTRL_REG[TIM0_CTRL] Peripheral
CLK_PER_REG[TMR_ENABLE] 0 clocks
Divide by tmr0_clk
TMR_DIV 1
1
TIMER0_CTRL_REG[TIM0_CLK_SEL] tmr0_on_clk
Divide by 0
10
TIMER0_CTRL_REG[TIM0_CLK_DIV]
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]
tmr2_clk
GP_ADC_CTRL_REG[GP_ADC_EN]
1
gp_adc_clk
Internal ADC 0
osc GP_ADC_CTRL_REG[GP_ADC_CLK_SEL]
CLK_RADIO_REG[RFCU_ENABLE]
Divide by
RFCU_DIV
rfcu_clk
CLK_RADIO_REG[BLE_ENABLE]
Divide by
BLE_DIV
ble_master1_clk
BLE & radio
ble_master2_clk clocks
ble_crypt_clk
ble_lp_clk
Figure 17: Clock Generation Block Diagram
Each of the clocks is generated by either a divider or a Table 17: Generated Clocks Description
clock gate. Both dividers and clock gates are able to
start/stop the clock of the module they drive. The con- Clock Name Description
trol of the peripheral clocks is provided by apb_clk AMBA APB interface clock
CLK_PER_REG.
otp_clk OTP controller clock. This is also
The clock names depicted in Figure 17 are explained in used for the OTP macro cell and
the following Table: should not be higher than 16 MHz
hclk AMBA AHB interface clock
ble_hclk AMBA AHB clock for the BLE core
Table 17: Generated Clocks Description
spi_clk Clock for the SPI controller. This
Clock Name Description clock is further divided by 2, 4, 8
or 14 as defined by
wakeupct_clk This is the clock for the wake-up
SPI_CTRL_REG[SPI_CLK]
capture timer.

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Table 17: Generated Clocks Description
Clock Name Description Table 18: Actual UART Baud Rates

i2c_clk Clock for the I2C controller. This
Target Actual
clock is further divided to provide Divisor Error
Baud Rate Baud Rate
100 kHz or 400 kHz as defined by Value (%)
(kBd) (kBd)
I2C_CON_REG[I2C_SPEED]
uart_clk Clock for the UART 115.2 9 111.1 3.54
uart2_clk Clock for the UART2 57.6 17 58.82 2.12
quad_clk Clock for the quadrature decoders 38.4 26 38.46 0.16
rfcu_clk Clock for the RF control unit of the 28.8 35 28.57 0.79
Radio 19.2 52 19.23 0.16
tmr0_clk, Timer0/2 clocks 9.6 104 9.61 0.16
tmr2_clk
tmr0_on_clk Timer0 ON counter clock If there is a hard requirement for having an average
baud rate deviation of no more than 5 % on both ends
gp_adc_clk General Purpose ADC conver-
sion clock of the UART connection, a baud rate with an error of
maximum 2.5 % should be selected from the table
ble_crypt_clk Clock for the Crypto block of the above.
BLE core
ble_master1_clk Internal clock for the BLE core
ble_master2_clk Internal clock for the BLE core
arb_clk Clock for the memory controller
arbiter
ble_lp_clk BLE core low power clock
11.4 GENERAL CLOCK CONSTRAINTS

There are certain constraints on various clocks regard-
ing their frequency relations or the effectiveness. This
section summarizes these rules:
• Minimum hclk clock should be 8 MHz. This is also
the clock of the ARM CPU and ensures the required
MIPS for the Bluetooth low energy Protocol han-
dling.
• hclk should always be greater or equal to the
ble_*_clks. This is required for the proper operation
of the protocol. For example, hclk at 16 MHz and
BLE clocks at 8 MHz is an acceptable combination
but not the other way around.
• When the SPI block is set to Slave mode, then the
spi_clk (as depicted in Figure 17) should be at least
4x the clock frequency provided by the external SPI
Master. This is required for proper sampling of the
data line.
• The UART clock is derived from the system clock as
follows: baud rate = (system clock DIV 16) / divisor.
The division by 16 is hard coded and hence, the
baud rate is generated by the divisor on the 1 MHz
input. This results in a certain error percentage with
respect to the well defined baud rates as presented
in the following table:

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12 OTP Controller • Embedded DMA engine for fast mirroring of the OTP
contents into the System RAM.
The OTP Controller realizes all functions of the OTP
macro cell in an automated and transparent way. The • Embedded DMA supports reading in bursts of 4 32-
controller facilitates all data transfers (reading and pro- bit words
gramming), while implementing the required OTP test • Standby state consumes minimum power
modes in hardware. The block diagram is presented in
Figure 18. • Hardwired handshaking with the PMU to realize the
mirroring procedure
Features
• Emulation of the mirroring procedure for the Devel-
• Implements all timing constraints for any access to opment mode.
the physical memory cells.
• Transparent random address access to the OTP
memory cells via the AHB slave memory interface.
AHB Bus
A H B S la v e A H B S la v e M a s te r
R e g is te r s M e m o ry M e m o ry
Copy C o n tr o lle r
R e q /A c k DMA
O T P C o n t r o lle r
O T P M a c r o c e ll O T P M a c r o c e ll
Upper Bank Low Bank
Figure 18: OTP Controller Block Diagram
12.1 OPERATING MODES The APROG mode gives the ability for programming
There are two different functional modes of operation large data blocks into the macro cell. The programming
for reading and programming respectively: manual is an automated procedure, during which it is only nec-
(MREAD, MPROG) and automatic (AREAD, APROG). essary to feed the controller with the required data.
The OTP operating mode is programmable at Data blocks can be fetched in two ways:
OTPC_MODE_REG[OTPC_MODE_MODE]. • Via the AHB master interface, i.e. the DMA
The MREAD mode enables the use of the memory • Via the AHB memory interface
slave interface. By activating this mode the contents of
the macro cell are transparently mapped onto the spe- In the latter case, data are pumped into the OTP con-
cific AHB slave address space. This mode can be used troller through a register, which acts as a port providing
for execution of software in place (XIP). access to a FIFO.
The AREAD mode provides the ability for reading data 12.2 AHB MASTER INTERFACE
from the macro cell in bursts, without the use of the The AHB master interface is controlled by a DMA
slave interface. This mode is used for copying large engine with an internal FIFO of 8 32-bit words. The
data blocks from the macro cell, as in the case of the DMA engine supports AHB reads and writes. The AHB
OTP mirroring into the System RAM. address where memory access should begin, is pro-
The MPROG mode implements the single step of the grammed into the DMA engine at
program/verify sequence. In this mode, when the pro- OTPC_AHBADR_REG[OTPC_AHBADR]. The num-
gramming of a bit fails, the controller does not automat- ber of 32-bit words (minus 1) of a transfer must be
ically try to reprogram the bit. Hence, reprogramming specified in OTPC_NWORDS_REG[OTP_NWORDS].
should be triggered by software. The value and the The DMA engine internally supports the following burst
address of the bit are defined through a configuration types:
register (OTPC_PCTRL_REG), for both macro cell
banks. The programming sequence can be enabled or • Four words incremental burst
disabled for each of the memory banks. The result of • Unspecified incremental burst of 2 or 3 words
the program/verify is stored in register
OTPC_STAT_REG. There is a status bit for each one • Single word access
of the two memory banks.

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13 I2C Interface • Clock synchronization

The I2C interface is a programmable control bus that • 32 deep transmit/receive FIFOs
provides support for the communications link between • Master transmit, Master receive operation
Integrated Circuits in a system. It is a simple two-wire
bus with a software-defined protocol for system control, • 7 or 10-bit addressing
which is used in temperature sensors and voltage level • 7 or 10-bit combined format transfers
translators to EEPROMs, general-purpose I/O, A/D
and D/A converters. • Bulk transmit mode
Features • Default slave address of 0x055
• Two-wire I2C serial interface consists of a serial data • Interrupt or polled-mode operation
line (SDA) and a serial clock (SCL) • Handles Bit and Byte waiting at both bus speeds
• Two speeds are supported: • Programmable SDA hold time
• Standard mode (0 to 100 kbit/s)
• Fast mode (<= 400 kbit/s)
I2 C
A M B A B u s S la v e S ta te M a s te r S ta te
R e g is te r F ile M a c h in e
In te r fa c e U n it M a c h in e
C lo c k
G e n e r a to r R x S h ift T x S h ift R x F ilte r
In te r r u p t
T o g g le S y n c h r o n ize r
C o n tr o lle r
R X F IF O T X F IF O
Figure 19: I2C Controller Block Diagram
The I2C Controller block diagram is shown in Figure • Rx Filter. Detects the events in the bus; for example,
19. It contains the following sub-blocks: start, stop and arbitration lost.
• AMBA Bus Interface Unit. Interfacing via the APB • Toggle. Generates pulses on both sides and toggles
interface to access the register file. to transfer signals across clock domains.
• Register File. Contains configuration registers and is • Synchronizer. Transfers signals from one clock
the interface with software. domain to another.
• Master State Machine. Generates the I2C protocol • Interrupt Controller. Generates the raw interrupt and
for the master transfers. interrupt flags, allowing them to be set and cleared.
• Clock Generator. Calculates the required timing to • RX FIFO/TX. Holds the RX FIFO and TX FIFO regis-
do the following: ter banks and controllers, along with their status lev-
els.
• Generate the SCL clock when configured as a
master 13.1 I2C BUS TERMS
• Check for bus idle The following terms relate to how the role of the I2C
• Generate a START and a STOP device and how it interacts with other I2C devices on
the bus.
• Setup the data and hold the data
• Transmitter. the device that sends data to the bus. A
• Rx Shift. Takes data into the design and extracts it in transmitter can either be a device that initiates the
byte format. data transmission to the bus (a master-transmitter)
• Tx Shift. Presents data supplied by CPU for transfer or responds to a request from the master to send
on the I2C bus. data to the bus (a slave-transmitter).

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• Receiver. The device that receives data from the START or RESTART condition. The level of the SDA
bus. A receiver can either be a device that receives data line changes from high to low, while the SCL
data on its own request (a master-receiver) or in clock line remains high. When this occurs, the bus
response to a request from the master (a slave- becomes busy.
receiver).
• STOP. data transfer is terminated by a STOP condi-
• Master. The component that initializes a transfer tion. This occurs when the level on the SDA data line
(START command), generates the clock (SCL) sig- passes from the low state to the high state, while the
nal and terminates the transfer (STOP command). A SCL clock line remains high. When the data transfer
master can be either a transmitter or a receiver. has been terminated, the bus is free or idle once
again. The bus stays busy if a RESTART is gener-
• Slave. The device addressed by the master. A slave
ated instead of a STOP condition.
can be either receiver or transmitter.
Note 3: START and RESTART conditions are functionally identical.
These concepts are illustrated in Figure 20.
13.2 I2C BEHAVIOR
The I2C can be only be controlled via software to be an
I2C master only, communicating with other I2C slaves;
The master is responsible for generating the clock and
controlling the transfer of data. The slave is responsible
for either transmitting or receiving data to/from the
master. The acknowledgement of data is sent by the
device that is receiving data, which can be either a
master or a slave. As mentioned previously, the I2C
protocol also allows multiple masters to reside on the
I2C bus and uses an arbitration procedure to deter-
Figure 20: Master/Slave and Transmitter/Receiver mine bus ownership.
Relationships Each slave has a unique address that is determined by
the system designer. When a master wants to commu-
• Multi-master. The ability for more than one master to nicate with a slave, the master transmits a START/
co-exist on the bus at the same time without collision RESTART condition that is then followed by the slave’s
or data loss. address and a control bit (R/W) to determine if the
master wants to transmit data or receive data from the
• Arbitration. The predefined procedure that autho- slave. The slave then sends an acknowledge (ACK)
rizes only one master at a time to take control of the pulse after the address.
bus. For more information about this behavior, refer
to Multiple Master Arbitration chapter If the master (master-transmitter) is writing to the slave
(slave-receiver), the receiver gets one byte of data.
• Synchronization. The predefined procedure that syn- This transaction continues until the master terminates
chronizes the clock signals provided by two or more the transmission with a STOP condition. If the master
masters. For more information about this feature, is reading from a slave (master-receiver), the slave
refer to Clock Synchronization chapter transmits (slave-transmitter) a byte of data to the mas-
• SDA. Data signal line (Serial DAta) ter, and the master then acknowledges the transaction
with the ACK pulse. This transaction continues until the
• SCL. Clock signal line (Serial CLock) master terminates the transmission by not acknowl-
edging (NACK) the transaction after the last byte is
13.1.1 Bus Transfer Terms received, and then the master issues a STOP condition
The following terms are specific to data transfers that or addresses another slave after issuing a RESTART
occur to/from the I2C bus. condition. This behavior is illustrated in Figure 21.
• START (RESTART). data transfer begins with a
Figure 21: Data Transfer on the I2C Bus

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The I2C is a synchronous serial interface. The SDA To initiate combined format transfers,
line is a bidirectional signal and changes only while the I2C_CON.I2C_RESTART_EN should be set to 1. With
SCL line is low, except for STOP, START, and this value set and operating as a master, when the I2C
RESTART conditions. The output drivers are open- Controller completes an I2C transfer, it checks the
drain or open-collector to perform wire-AND functions transmit FIFO and executes the next transfer. If the
on the bus. The maximum number of devices on the direction of this transfer differs from the previous trans-
bus is limited by only the maximum capacitance speci- fer, the combined format is used to issue the transfer. If
fication of 400 pF. Data is transmitted in byte packages. the transmit FIFO is empty when the current I2C trans-
fer completes, a STOP is issued and the next transfer
13.2.1 START and STOP Generation is issued following a START condition.
When operating as an I2C master, putting data into the 13.3 I2C PROTOCOLS
transmit FIFO causes the I2C Controller to generate a
START condition on the I2C bus. Allowing the transmit The I2C Controller has the following protocols:
FIFO to empty causes the I2C Controller to generate a • START and STOP Conditions
STOP condition on the I2C bus.
• Addressing Slave Protocol
When operating as a slave, the I2C Controller does not
• Transmitting and Receiving Protocol
generate START and STOP conditions, as per the pro-
tocol. However, if a read request is made to the I2C • START BYTE Transfer Protocol
Controller, it holds the SCL line low until read data has
been supplied to it. This stalls the I2C bus until read 13.3.1 START and STOP Conditions
data is provided to the slave I2C Controller, or the I2C
When the bus is idle, both the SCL and SDA signals
Controller slave is disabled by writing a 0 to
are pulled high through external pull-up resistors on the
I2C_ENABLE.
bus. When the master wants to start a transmission on
the bus, the master issues a START condition. This is
13.2.2 Combined Formats
defined to be a high-to-low transition of the SDA signal
The I2C Controller supports mixed read and write com- while SCL is 1. When the master wants to terminate
bined format transactions in both 7-bit and 10-bit the transmission, the master issues a STOP condition.
addressing modes. This is defined to be a low-to-high transition of the SDA
line while SCL is 1. Figure 22 shows the timing of the
The I2C Controller does not support mixed address
START and STOP conditions. When data is being
and mixed address format.that is, a 7-bit address
transmitted on the bus, the SDA line must be stable
transaction followed by a 10-bit address transaction or
when SCL is 1.
vice versa.combined format transactions.
Figure 22: START and STOP Conditions
Note 4: The signal transitions for the START/STOP conditions, as depicted in Figure 21, reflect those observed at the output signals of the Master
driving the I2C bus. Care should be taken when observing the SDA/SCL signals at the input signals of the Slave(s), because unequal line
delays may result in an incorrect SDA/SCL timing relationship.
13.3.2 Addressing Slave Protocol

There are two address formats: the 7-bit address for-
mat and the 10-bit address format.
7-bit Address Format
During the 7-bit address format, the first seven bits
(bits 7:1) of the first byte set the slave address and the
LSB bit (bit 0) is the R/W bit as shown in Figure 23.
When bit 0 (R/W) is set to 0, the master writes to the
slave. When bit 0 (R/W) is set to 1, the master reads
from the slave.

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Figure 23: 7-bit Address Format
10-bit Address Format slaves address bits 9:8, and the LSB bit (bit 0) is the R/
W bit. The second byte transferred sets bits 7:0 of the
During 10-bit addressing, two bytes are transferred to
slave address. Figure 24 shows the 10-bit address for-
set the 10-bit address. The transfer of the first byte
mat, and Table 19 defines the special purpose and
contains the following bit definition. The first five bits
reserved first byte addresses.
(bits 7:3) notify the slaves that this is a 10-bit transfer
followed by the next two bits (bits 2:1), which set the
Figure 24: 10-bit Address Format
Table 19: I2C Definition of Bits in First Byte
Slave Address R/W Bits Description

0000 000 0 General Call Address. I2C Controller places the data in the receive buffer and
issues a
General Call interrupt.
0000 000 1 START byte. For more details, refer to “START BYTE Transfer Protocol” 0000
0000 001 X CBUS address. I2C Controller ignores these accesses
0000 010 X Reserved
0000 011 X Reserved
0000 1XX X High-speed master code (for more information, refer to “Multiple Master Arbitra-
tion”
1111 1XX X Reserved
1111 0XX X 10-bit slave addressing
I2C Controller does not restrict you from using these from the master to either transmit data or receive data
reserved addresses. However, if you use these to/from the bus, acting as either a slave-transmitter or
reserved addresses, you may run into incompatibilities slave-receiver, respectively.
with other I2C components.
Master-Transmitter and Slave-Receiver
13.3.3 Transmitting and Receiving Protocols All data is transmitted in byte format, with no limit on
the number of bytes transferred per data transfer. After
The master can initiate data transmission and recep-
the master sends the address and R/W bit or the mas-
tion to/from the bus, acting as either a master-transmit-
ter transmits a byte of data to the slave, the slave-
ter or master-receiver. A slave responds to requests
receiver must respond with the acknowledge signal
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(ACK). When a slave-receiver does not respond with If the master-transmitter is transmitting data as shown
an ACK pulse, the master aborts the transfer by issuing in Figure 25, then the slave-receiver responds to the
a STOP condition. The slave must leave the SDA line master-transmitter with an acknowledge pulse after
high so that the master can abort the transfer. every byte of data is received.
Figure 25: Master-Transmitter Protocol
Master-Receiver and Slave-Transmitter When a master does not want to relinquish the bus
with a STOP condition, the master can issue a
If the master is receiving data as shown in Figure 26
RESTART condition. This is identical to a START con-
then the master responds to the slave-transmitter with
dition except it occurs after the ACK pulse. The master
an acknowledge pulse after a byte of data has been
can then communicate with the same slave or a differ-
received, except for the last byte. This is the way the
ent slave.
master-receiver notifies the slave-transmitter that this
is the last byte. The slave-transmitter relinquishes the
SDA line after detecting the No Acknowledge (NACK)
so that the master can issue a STOP condition.
Figure 26: Master-Receiver Protocol

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START BYTE Transfer Protocol device requires it. This protocol consists of seven zeros
being transmitted followed by a 1, as illustrated in
The START BYTE transfer protocol is set up for sys-
Figure 27. This allows the processor that is polling the
tems that do not have an on-board dedicated I2C hard-
bus to under-sample the address phase until 0 is
ware module. When the I2C Controller is addressed as
detected. Once the microcontroller detects a 0, it
a slave, it always samples the I2C bus at the highest
switches from the under sampling rate to the correct
speed supported so that it never requires a START
rate of the master.
BYTE transfer. However, when I2C Controller is a mas-
ter, it supports the generation of START BYTE trans-
fers at the beginning of every transfer in case a slave
Figure 27: START BYTE Transfer
The START BYTE procedure is as follows: defined by the system designer and is set by writing to
the High Speed Master Mode Code Address Register,
1. Master generates a START condition.
I2C_HS_MADDR. Because the codes are unique, only
2. Master transmits the START byte (0000 0001). one master can win arbitration, which occurs by the
end of the transmission of the high-speed master code.
3. Master transmits the ACK clock pulse. (Present
only to conform with the byte handling format Control of the bus is determined by address or master
used on the bus) code and data sent by competing masters, so there is
no central master nor any order of priority on the bus.
4. No slave sets the ACK signal to 0.
Arbitration is not allowed between the following condi-
5. Master generates a RESTART (R) condition.
tions:
A hardware receiver does not respond to the START
• A RESTART condition and a data bit
BYTE because it is a reserved address and resets after
the RESTART condition is generated. • A STOP condition and a data bit
13.4 MULTIPLE MASTER ARBITRATION • A RESTART condition and a STOP condition

The I2C Controller bus protocol allows multiple mas- Slaves are not involved in the arbitration process.
ters to reside on the same bus. If there are two masters
on the same I2C-bus, there is an arbitration procedure
if both try to take control of the bus at the same time by
generating a START condition at the same time. Once
a master (for example, a microcontroller) has control of
the bus, no other master can take control until the first
master sends a STOP condition and places the bus in
an idle state.
Arbitration takes place on the SDA line, while the SCL
line is 1. The master, which transmits a 1 while the
other master transmits 0, loses arbitration and turns off
its data output stage. The master that lost arbitration
can continue to generate clocks until the end of the
byte transfer. If both masters are addressing the same
slave device, the arbitration could go into the data
phase. Figure 28 illustrates the timing of when two
masters are arbitrating on the bus.
For high-speed mode, the arbitration cannot go into the
data phase because each master is programmed with
a unique high-speed master code. This 8-bit code is

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Figure 28: Multiple Master Arbitration
13.5 CLOCK SYNCHRONIZATION goes into a HIGH wait state until the SCL clock line
When two or more masters try to transfer information transitions to 1.
on the bus at the same time, they must arbitrate and All masters then count off their high time, and the mas-
synchronize the SCL clock. All masters generate their ter with the shortest high time transitions the SCL line
own clock to transfer messages. Data is valid only dur- to 0. The masters then counts out their low time and
ing the high period of SCL clock. Clock synchronization the one with the longest low time forces the other mas-
is performed using the wired-AND connection to the ter into a HIGH wait state. Therefore, a synchronized
SCL signal. When the master transitions the SCL clock SCL clock is generated, which is illustrated in Figure
to 0, the master starts counting the low time of the SCL 29. Optionally, slaves may hold the SCL line low to
clock and transitions the SCL clock signal to 1 at the slow down the timing on the I2C bus.
beginning of the next clock period. However, if another
master is holding the SCL line to 0, then the master
Figure 29: Multiple Master Clock Synchronization

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13.6 OPERATION MODES 1. The other I2C master device initiates an I2C transfer
This section provides information on the following top- with an address that matches the slave address in the
ics: I2C_SAR register of the I2C Controller.
• Slave mode operation 2. The I2C Controller acknowledges the sent address
and recognizes the direction of the transfer to indicate
• Master mode operation that it is acting as a slave-transmitter.
• Disabling I2C Controller 3. The I2C Controller asserts the RD_REQ interrupt (bit
Note 5: It is important to note that the I2C Controller should only be 5 of the I2C_RAW_INTR_STAT register) and holds the
set to operate as an I2C Master, or I2C Slave, but not both SCL line low. It is in a wait state until software
simultaneously. This is achieved by ensuring that bit 6 responds. If the RD_REQ interrupt has been masked,
(I2C_SLAVE_DISABLE) and 0 (I2C_MASTER_MODE) of due to I2C_INTR_MASK[5] register (M_RD_REQ bit
the I2C_CON register are never set to 0 and 1, respectively. field) being set to 0, then it is recommended that a
hardware and/or software timing routine be used to
13.6.1 Slave Mode Operation instruct the CPU to perform periodic reads of the
I2C_RAW_INTR_STAT register.
This section includes the following procedures:
a. Reads that indicate I2C_RAW_INTR_STAT[5]
• Initial Configuration (R_RD_REQ bit field) being set to 1 must be treated as
• Slave-Transmitter Operation for a Single Byte the equivalent of the RD_REQ interrupt being
asserted.
• Slave-Receiver Operation for a Single Byte
b. Software must then act to satisfy the I2C transfer.
• Slave-Transfer Operation For Bulk Transfers
c. The timing interval used should be in the order of 10
times the fastest SCL clock period the I2C Controller
Initial Configuration
can handle. For example, for 400 kb/s, the timing inter-
To use the I2C Controller as a slave, perform the fol- val is 25us.
lowing steps: Note 8: The value of 10 is recommended here because this is
1. Disable the I2C Controller by writing a ‘0’ to bit 0 of approximately the amount of time required for a single byte
the I2C_ENABLE register. of data transferred on the I2C bus.
4. If there is any data remaining in the TX FIFO before
2. Write to the I2C_SAR register (bits 9:0) to set the receiving the read request, then the I2C Controller
slave address. This is the address to which the I2C asserts a TX_ABRT interrupt (bit 6 of the
Controller responds. I2C_RAW_INTR_STAT register) to flush the old data
3. Write to the I2C_CON register to specify which type from the TX FIFO.
of addressing is supported (7- or 10-bit by setting bit 3). Note 9: Because the I2C Controller’s TX FIFO is forced into a
Enable the I2C Controller in slave-only mode by writing flushed/reset state whenever a TX_ABRT event occurs, it is
a ‘0’ into bit 6 (I2C_SLAVE_DISABLE) and a ‘0’ to bit 0 necessary for software to release the I2C Controller from this
(MASTER_MODE).
state by reading the I2C_CLR_TX_ABRT register before
Note 6: Slaves and masters do not have to be programmed with the attempting to write into the TX FIFO. See register
same type of addressing 7- or 10-bit address. For instance, a I2C_RAW_INTR_STAT for more details.
slave can be programmed with 7-bit addressing and a mas- If the TX_ABRT interrupt has been masked, due to of
ter with 10-bit addressing, and vice versa. I2C_INTR_MASK[6] register (M_TX_ABRT bit field)
being set to 0, then it is recommended that re-using the
4. Enable the I2C Controller by writing a ‘1’ in bit 0 of timing routine (described in the previous step), or a
the I2C_ENABLE register. similar one, be used to read the
Note 7: Depending on the reset values chosen, steps 2 and 3 may I2C_RAW_INTR_STAT register.
not be necessary because the reset values can be config- a. Reads that indicate bit 6 (R_TX_ABRT) being set to
ured. For instance, if the device is only going to be a master, 1 must be treated as the equivalent of the TX_ABRT
there would be no need to set the slave address because interrupt being asserted.
you can configure the I2C Controller to have the slave dis-
abled after reset and to enable the master after reset. The b. There is no further action required from software.
values stored are static and do not need to be repro- c. The timing interval used should be similar to that
grammed if the I2C Controller is disabled. described in the previous step for the
I2C_RAW_INTR_STAT[5] register.
Slave-Transmitter Operation for a Single Byte
5. Software writes to the I2C_DATA_CMD register with
When another I2C master device on the bus addresses the data to be written (by writing a ‘0’ in bit 8).
the I2C Controller and requests data, the I2C Controller
acts as a slave-transmitter and the following steps 6. Software must clear the RD_REQ and TX_ABRT
occur: interrupts (bits 5 and 6, respectively) of the
I2C_RAW_INTR_STAT register before proceeding.

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If the RD_REQ and/or TX_ABRT interrupts have been remote master read request by writing one byte into the
masked, then clearing of the I2C_RAW_INTR_STAT slave’s TX FIFO. When a slave (slave-transmitter) is
register will have already been performed when either issued with a read request (RD_REQ) from the remote
the R_RD_REQ or R_TX_ABRT bit has been read as master (master-receiver), at a minimum there should
1. be at least one entry placed into the slave-transmitter’s
TX FIFO.
7. The I2C Controller releases the SCL and transmits
the byte. I2C Controller is designed to handle more data in the
TX FIFO so that subsequent read requests can take
8. The master may hold the I2C bus by issuing a
that data without raising an interrupt to get more data.
RESTART condition or release the bus by issuing a
Ultimately, this eliminates the possibility of significant
STOP condition.
latencies being incurred between raising the interrupt
Slave-Receiver Operation for a Single Byte for data each time had there been a restriction of hav-
ing only one entry placed in the TX FIFO.
When another I2C master device on the bus addresses
the I2C Controller and is sending data, the I2C Control- This mode only occurs when I2C Controller is acting as
ler acts as a slave-receiver and the following steps a slave-transmitter. If the remote master acknowledges
occur: the data sent by the slave-transmitter and there is no
data in the slave’s TX FIFO, the I2C Controller holds
1. The other I2C master device initiates an I2C transfer
the I2C SCL line low while it raises the read request
with an address that matches the I2C Controller’s slave
interrupt (RD_REQ) and waits for data to be written
address in the I2C_SAR register.
into the TX FIFO before it can be sent to the remote
2. The I2C Controller acknowledges the sent address master.
and recognizes the direction of the transfer to indicate
If the RD_REQ interrupt is masked, due to bit 5
that the I2C Controller is acting as a slave-receiver.
(M_RD_REQ) of the I2C_INTR_STAT register being
3. I2C Controller receives the transmitted byte and set to 0, then it is recommended that a timing routine
places it in the receive buffer. be used to activate periodic reads of the
Note 10: If the RX FIFO is completely filled with data when a byte is
I2C_RAW_INTR_STAT register. Reads of
pushed, then an overflow occurs and the I2C Controller con-
I2C_RAW_INTR_STAT that return bit 5 (R_RD_REQ)
tinues with subsequent I2C transfers. Because a NACK is
set to 1 must be treated as the equivalent of the
not generated, software must recognize the overflow when
RD_REQ interrupt referred to in this section. This tim-
indicated by the I2C Controller (by the R_RX_OVER bit in
ing routine is similar to that described in “Slave-Trans-
the I2C_INTR_STAT register) and take appropriate actions
mitter Operation for a Single Byte”
to recover from lost data. Hence, there is a real time con- The RD_REQ interrupt is raised upon a read request,
straint on software to service the RX FIFO before the latter and like interrupts, must be cleared when exiting the
overflow as there is no way to re-apply pressure to the interrupt service handling routine (ISR). The ISR allows
remote transmitting master. You must select a deep enough you to either write 1 byte or more than 1 byte into the
RX FIFO depth to satisfy the interrupt service interval of their TX FIFO. During the transmission of these bytes to the
system. master, if the master acknowledges the last byte. then
the slave must raise the RD_REQ again because the
4. I2C Controller asserts the RX_FULL interrupt master is requesting for more data.
(I2C_RAW_INTR_STAT[2] register).
If the programmer knows in advance that the remote
If the RX_FULL interrupt has been masked, due to set- master is requesting a packet of n bytes, then when
ting I2C_INTR_MASK[2] register to 0 or setting another master addresses I2C Controller and requests
I2C_TX_TL to a value larger than 0, then it is recom- data, the TX FIFO could be written with n number bytes
mended that a timing routine (described in “Slave- and the remote master receives it as a continuous
Transmitter Operation for a Single Byte”) be imple- stream of data. For example, the I2C Controller slave
mented for periodic reads of the “I2C_STATUS” on continues to send data to the remote master as long as
page 138 register. Reads of the I2C_STATUS register, the remote master is acknowledging the data sent and
with bit 3 (RFNE) set at 1, must then be treated by soft- there is data available in the TX FIFO. There is no
ware as the equivalent of the RX_FULL interrupt being need to hold the SCL line low or to issue RD_REQ
asserted. again.
5. Software may read the byte from the If the remote master is to receive n bytes from the I2C
I2C_DATA_CMD register (bits 7:0). Controller but the programmer wrote a number of bytes
larger than n to the TX FIFO, then when the slave fin-
6. The other master device may hold the I2C bus by
ishes sending the requested n bytes, it clears the TX
issuing a RESTART condition or release the bus by
FIFO and ignores any excess bytes.
issuing a STOP condition.
The the I2C Controller generates a transmit abort
Slave-Transfer Operation for Bulk Transfers
(TX_ABRT) event to indicate the clearing of the TX
In the standard I2C protocol, all transactions are single FIFO in this example. At the time an ACK/NACK is
byte transactions and the programmer responds to a expected, if a NACK is received, then the remote mas-

DA14580
ter has all the data it wants. At this time, a flag is raised Master Transmit and Master Receive
within the slave’s state machine to clear the leftover
The I2C Controller supports switching back and forth
data in the TX FIFO. This flag is transferred to the pro-
between reading and writing dynamically. To transmit
cessor bus clock domain where the FIFO exists and
data, write the data to be written to the lower byte of the
the contents of the TX FIFO is cleared at that time.
IC_DATA_CMD register. The CMD bit [8] should be
written to 0 for I2C write operations.
13.6.2 Master Mode Operation
Subsequently, a read command may be issued by writ-
This section includes the following topics:
ing “don’t cares” to the lower byte of the
• Initial Configuration IC_DATA_CMD register, and a 1 should be written to
the CMD bit.
• Master Transmit and Master Receive
The I2C Controller master continues to initiate trans-
fers as long as there are commands present in the
Initial Configuration
transmit FIFO. If the transmit FIFO becomes empty, the
The procedures are very similar and are only different master inserts a STOP condition after completing the
with regard to where the I2C_10BITADDR_MASTER current transfer.
bit is set (either bit 4 of I2C_CON register or bit 12 of
I2C_TAR register). 13.6.3 Disabling the I2C Controller
To use the I2C Controller as a master perform the fol- The register I2C_ENABLE_STATUS is added to allow
lowing steps: software to unambiguously determine when the hard-
ware has completely shutdown in response to the
1. Disable the I2C Controller by writing 0 to the
I2C_ENABLE register being set from 1 to 0. Only one
I2C_ENABLE register.
register is required to be monitored
2. Write to the I2C_CON register to set the maximum
Procedure
speed mode supported (bits 2:1) and the desired
speed of the I2C Controller master-initiated transfers, 1. Define a timer interval (ti2c_poll) equal to the 10
either 7-bit or 10-bit addressing (bit 4). times the signalling period for the highest I2C transfer
speed used in the system and supported by I2C Con-
Ensure that bit 6 I2C_SLAVE_DISABLE = 1 and bit 0
troller. For example, if the highest I2C transfer mode is
MASTER_MODE =1
400 kb/s, then this ti2c_poll is 25us.
Note 11: Slaves and masters do not have to be programmed with the
same type of addressing 7- or 10-bit address. For instance, a 2. Define a maximum time-out parameter,
slave can be programmed with 7-bit addressing and a mas- MAX_T_POLL_COUNT, such that if any repeated poll-
ter with 10-bit addressing, and vice versa. ing operation exceeds this maximum value, an error is
reported.
3. Write to the I2C_TAR register the address of the I2C 3. Execute a blocking thread/process/function that pre-
device to be addressed (bits 9:0). This register also vents any further I2C master transactions to be started
indicates whether a General Call or a START BYTE by software, but allows any pending transfers to be
command is going to be performed by I2C. completed.
4. Only applicable for high-speed mode transfers. Write Note 13: This step can be ignored if I2C Controller is programmed to
to the I2C_HS_MADDR register the desired master operate as an I2C slave only.
code for the I2C Controller. The master code is pro- 4. The variable POLL_COUNT is initialized to zero.
grammer-defined.
5. Set I2C_ENABLE to 0.
5. Enable the I2C Controller by writing a 1 in bit 0 of the
6. Read the I2C_ENABLE_STATUS register and test
I2C_ENABLE register.
the I2C_EN bit (bit 0). Increment POLL_COUNT by
6. Now write transfer direction and data to be sent to one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit
the I2C_DATA_CMD register. If the I2C_DATA_CMD with the relevant error code.
register is written before the I2C Controller is enabled,
7. If I2C_ENABLE_STATUS[0] is 1, then sleep for
the data and commands are lost as the buffers are kept
ti2c_poll and proceed to the previous step.
cleared when I2C Controller is disabled.
Otherwise, exit with a relevant success code.
This step generates the START condition and the
address byte on the I2C Controller. Once I2C Control-
ler is enabled and there is data in the TX FIFO, I2C
Controller starts reading the data.
Note 12: Depending on the reset values chosen, steps 2, 3, 4, and 5
may not be necessary because the reset values can be con-
figured. The values stored are static and do not need to be
reprogrammed if the I2C Controller is disabled, with the
exception of the transfer direction and data.

DA14580
14 UART • Shadow registers to reduce software overhead and

also include a software programmable reset
The DA14580 contains two identical instances of this
block, i.e. UART and UART2. • Transmitter Holding Register Empty (THRE) inter-
rupt mode
The UART is compliant to the industry-standard 16550
and is used for serial communication with a peripheral, • IrDA 1.0 SIR mode supporting low power mode.
modem (data carrier equipment, DCE) or data set. • Functionality based on the 16550 industry standard:
Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and • Programmable character properties, such as num-
transmitted to the destination device. Serial data is also ber of data bits per character (5-8), optional
received by the UART and stored for the master (CPU) • parity bit (with odd or even select) and number of
to read back. stop bits (1, 1.5 or 2)
There is no DMA support on the UART block since its • Line break generation and detection
contains internal FIFOs. Both UARTs support hardware
flow control signals (RTS, CTS, DTR, DSR). • Prioritized interrupt identification
Features • Programmable serial data baud rate as calculated

by the following: baud rate = (serial clock frequency)/
• 16 bytes Transmit and receive FIFOs (divisor).
• Hardware flow control support (CTS/RTS)
UART
UART2
pclk
FIFO
Block
APB
APB Bus
Interface
Register uart_int
Block
rts_n
Modem
cts_n Sync Sync
Block Block Timeout
Detector
Baud
Clock
uart_clk Generator
uart_rx Serial Receiver Serial Transmitter uart_tx
Figure 30: UART Block Diagram

DA14580
14.1 UART (RS232) SERIAL PROTOCOL

Because the serial communication between the UART
and the selected device is asynchronous, additional
bits (start and stop) are added to the serial data to indi-
cate the beginning and end. Utilizing these bits allows
two devices to be synchronized. This structure of serial
data accompanied by start and stop bits is referred to
as a character, as shown in Figure 31.
Figure 31: Serial Data Format
An additional parity bit may be added to the serial char- ted for exactly the same time duration. This is referred
acter. This bit appears after the last data bit and before to as a Bit Period or Bit Time. One BitTime equals 16
the stop bit(s) in the character structure to provide the baud clocks. To ensure stability on the line the receiver
UART with the ability to perform simple error checking samples the serial input data at approximately the mid
on the received data. point of the Bit Time once the start bit has been
detected. As the exact number of baud clocks that
The UART Line Control Register (UART_LCR_REG) is
each bit was transmitted for is known, calculating the
used to control the serial character characteristics. The
mid point for sampling is not difficult, that is every 16
individual bits of the data word are sent after the start
baud clocks after the mid point sample of the start bit.
bit, starting with the least-significant bit (LSB). These
Figure 32 shows the sampling points of the first couple
are followed by the optional parity bit, followed by the
of bits in a serial character.
stop bit(s), which can be 1, 1.5 or 2.
All the bits in the transmission (with exception to the
half stop bit when 1.5 stop bits are used) are transmit-
Figure 32: Receiver Serial Data Sampling Points
As part of the 16550 standard an optional baud clock Note 14: Attention. Information provided on IrDA SIR mode in this
reference output signal (baudout_n) is supplied to pro- section assumes that the reader is fully familiar with the IrDA
vide timing information to receiving devices that require Serial Infrared Physical Layer Specifications. This specifica-
it. The baud rate of the UART is controlled by the serial tion can be obtained from the following website:
clock (sclk or pclk in a single clock implementation) and http://www.irda.org
the Divisor Latch Register (DLH and DLL).
The data format is similar to the standard serial (sout
14.2 IRDA 1.0 SIR PROTOCOL and sin) data format. Each data character is sent seri-
The Infrared Data Association (IrDA) 1.0 Serial Infrared ally, beginning with a start bit, followed by 8 data bits,
(SIR) mode supports bi-directional data communica- and ending with at least one stop bit. Thus, the number
tions with remote devices using infrared radiation as of data bits that can be sent is fixed. No parity informa-
the transmission medium. IrDA 1.0 SIR mode specifies tion can be supplied and only one stop bit is used while
a maximum baud rate of 115.2 kBaud. in this mode.
Trying to adjust the number of data bits sent or enable

DA14580
parity with the Line Control Register (LCR) has no pulse. The width of each pulse is 3/16th of a normal
effect. When the UART is configured to support IrDA serial bit time. Thus, each new character begins with
1.0 SIR it can be enabled with Mode Control Register an infrared pulse for the start bit. However, received
(MCR) bit 6. When the UART is not configured to sup- data is inverted from transmitted data due to the infra-
port IrDA SIR mode, none of the logic is implemented red pulses energizing the photo transistor base of the
and the mode cannot be activated, reducing total gate IrDA receiver, pulling its output low. This inverted tran-
counts. When SIR mode is enabled and active, serial sistor output is then fed to the UART sir_in port, which
data is transmitted and received on the sir_out_n and then has correct UART polarity. Figure 33 shows the
sir_in ports, respectively. timing diagram for the IrDA SIR data format in compar-
ison to the standard serial format.
Transmitting a single infrared pulse signals a logic
zero, while a logic one is represented by not sending a
Figure 33: IrDA SIR Data Format
As detailed in the IrDA 1.0 SIR, the UART can be con- 14.3 CLOCK SUPPORT
figured to support a low-power reception mode. When The UART has two system clocks (pclk and sclk). Hav-
the UART is configured in this mode, the reception of ing the second asynchronous serial clock (sclk) imple-
SIR pulses of 1.41 s (minimum pulse duration) is pos- mented accommodates accurate serial baud rate
sible, as well as nominal 3/16th of a normal serial bit settings, as well as APB bus interface requirements.
time. Using this low-power reception mode requires
programming the Low Power Divisor Latch (LPDLL/ With the two clock design a synchronization module is
LPDLH) registers. It should be noted that for all sclk implemented for synchronization of all control and data
frequencies greater than or equal to 7.37 MHz (and across the two system clock boundaries.
obey the requirements of the Low Power Divisor Latch A serial clock faster than four-times the PCLK does not
registers), pulses of 1.41 s are detectable. However leave enough time for a complete incoming character
there are several values of sclk that do not allow the to be received and pushed into the receiver FIFO.
detection of such a narrow pulse and these are as fol- However, in most cases, the PCLK signal is faster than
lows: the serial clock and this should never be an issue.
Table 20: Low Power Divisor Latch Register Values The serial clock modules must have time to see new
register values and reset their respective state
Min. Pulse machines. This total time is guaranteed to be no more
Low Power Divisor than eight clock cycles of the slower of the two system
SCLK Width for
Latch Register Value clocks. Therefore, no data should be transmitted or
Detection
received before this maximum time expires, after initial
1.84 MHz 1 3.77 s configuration.
3.69 MHz 2 2.086 s
For a clear view of the baud rate generation and the
5.33 MHz 3 1.584 s constraints, please refer to section 11.4.
When IrDA SIR mode is enabled, the UART operation

is similar to when the mode is disabled, with one
exception; data transfers can only occur in half-duplex
fashion when IrDA SIR mode is enabled. This is
because the IrDA SIR physical layer specifies a mini-
mum of 10 ms delay between transmission and recep-
tion. This 10 ms delay must be generated by software.

DA14580
14.4 INTERRUPTS • Character Timeout (in FIFO mode only)

The assertion of the UART interrupt (UART_INT) • Transmitter Holding Register Empty at/below thresh-
occurs whenever one of the several prioritized interrupt old (in Programmable THRE interrupt mode)
types are enabled and active. The following interrupt
types can be enabled with the IER register: When an interrupt occurs the master accesses the
UART_IIR_REG to determine the source of the inter-
• Receiver Error rupt before dealing with it accordingly. These interrupt
• Receiver Data Available types are described in more detail in Table 21.
Table 21: UART Interrupt Priorities
Interrupt Id Interrupt Set and Reset Functions

Priority
Bits [3-0] Interrupt Type Interrupt Source Interrupt Reset Control
Level
0001 - None
0110 Highest Receiver Line status Overrun/parity/ framing errors or Reading the line status reg-
break interrupt ister
0100 1 Receiver Data Available Receiver data available (non- Reading the receiver buffer
FIFO mode or FIFOs disabled) or register (non-FIFO mode or
RCVR FIFO trigger level reached FIFOs disabled) or the FIFO
(FIFO mode and FIFOs enabled) drops below the trigger level
(FIFO mode and FIFOs
enabled)
1100 2 Character timeout indi- No characters in or out of the Reading the receiver buffer
cation RCVR FIFO during the last 4 register
character times and there is at
least 1 character in it during this
time.
0010 3 Transmitter holding reg- Transmitter holding register Reading the IIR register (if
ister empty empty (Prog. THRE Mode dis- source of interrupt); or, writ-
abled) or XMIT FIFO at or below ing into THR (FIFOs or
threshold (Prog. THRE Mode THRE Mode not selected or
enabled). disabled) or XMIT FIFO
above threshold (FIFOs and
THRE Mode selected and
enabled).
0000 4 Reserved
0111 Lowest Reserved - -
14.5 PROGRAMMABLE THRE INTERRUPT

The UART can be configured to have a Programmable
THRE Interrupt mode available to increase system per-
formance.
When Programmable THRE Interrupt mode is selected
it can be enabled via the Interrupt Enable Register
(IER[7]). When FIFOs and the THRE Mode are imple-
mented and enabled, THRE Interrupts are active at,
and below, a programmed transmitter FIFO empty
threshold level, as opposed to empty, as shown in the
flowchart in Figure 34.

DA14580
Figure 34: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode
This threshold level is programmed into FCR[5:4]. The occurs and there is data to transmit”, instead of waiting
available empty thresholds are: empty, 2, ¼ and ½. until the FIFO is completely empty. Waiting until the
See UART_FCR_REG for threshold setting details. FIFO is empty causes a performance hit whenever the
Selection of the best threshold value depends on the system is too busy to respond immediately.
system's ability to begin a new transmission sequence
Even if everything else is selected and enabled, if the
in a timely manner. However, one of these thresholds
FIFOs are disabled via FCR[0], the Programmable
should prove optimum in increasing system perfor-
THRE Interrupt mode is also disabled. When not
mance by preventing the transmitter FIFO from running
selected or disabled, THRE interrupts and LSR[5] func-
empty.
tion normally (both reflecting an empty THR or FIFO).
In addition to the interrupt change, Line Status Register The flowchart of THRE interrupt generation when not in
(LSR[5]) also switches function from indicating trans- programmable THRE interrupt mode is shown in
mitter FIFO empty, to FIFO full. This allows software to Figure 35.
fill the FIFO each transmit sequence by polling LSR[5]
before writing another character. The flow then
becomes, “fill transmitter FIFO whenever an interrupt
Figure 35: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode

DA14580
14.6 SHADOW REGISTERS

The shadow registers shadow some of the existing
register bits that are regularly modified by software.
These can be used to reduce the software overhead
that is introduced by having to perform read-modify
writes.
• UART_SRBR_REG support a host burst mode
where the host increments it address but still
accesses the same Receive buffer register
• UART_STHR support a host burst mode where the
host increments it address but still accesses the
same transmit holding register.
• UART_SFE_REG accesses the FCR[0] register
without accessing the other UART_FCR_REG bits.
• UART_SRT_REG accesses the FCR[7-6] register
• UART_STER_REG accesses the FCR[5-4] register
14.7 DIRECT TEST MODE

The on-chip UARTS can be used for the Direct Test
Mode required for the final product PHY layer testing. It
can be done either over the HCI layer, which engages
a full CTS/RTS UART or using a 2-wire UART directly
as described in the Bluetooth Low Energy Specification
(Volume 6, Part F).

DA14580
15 SPI+ Interface • Clock speeds up to 16 MHz for the SPI controller.

Programmable output frequencies of SPI source
This interface supports a subset of the Serial Periph- clock divided by 1, 2, 4, 8
eral Interface (SPITM). The serial interface can transmit
and receive 8, 16 or 32 bits in master/slave mode and • SPI clock line speed up to 8 MHz
transmit 9 bits in master mode. The SPI+ interface has • SPI mode 0, 1, 2, 3 support (clock edge and phase)
enhanced functionality with bidirectional 2x16-bit word
FIFOs. • Programmable SPI_DO idle level
SPI is a trademark of Motorola, Inc. • Maskable Interrupt generation
Features • Bus load reduction by unidirectional writes-only and
reads-only modes.
• Slave and Master mode
• Built-in RX/TX FIFOs for continuous SPI bursts.
• 8 bit, 9 bit, 16 bit or 32 bit operation
SPI_INT
SPI_MINT APB bus

Request &
Interrupt
Selection TX-FIFO
tx_req
SPI_TX_REG0 SPI_TX_REG1
clear_tx_req
SPI_SMn SPI_FORCE_DO
SPI clock SPI_DO
IO buffer SPI_RST
SPI_CLK SPI_9BIT_VAL
SPI_ON
rx_req RX-FIFO
SPI_PHA SPI_POL
clear_rx_req SPI_RX_REG0 SPI_RX_REG1
SPI_EN_CTRL
APB bus
Px_MODE_REG[] Port x
SPI_CLK SPI_EN SPI_DO SPI_DI
Figure 36: SPI Block Diagram
15.1 OPERATION WITHOUT FIFOS to be transmitted on SPI_DO. Simultaneously, data is

This mode is the default mode. received on SPI_DI and shifted into the IO buffer. The
transfer cycle finishes after the 8th/9th/16th/32nd clock
Master Mode cycle and SPI_INT_BIT bit is set in the
To enable SPITM operation, first the individual port sig- SPI_CTRL_REG and SPI_INT_PEND bit in
nal must be enabled. Next the SPI must be configured (RE)SET_INT_PENDING_REG is set. The received
in SPI_CTRL_REG, for the desired mode. Finally bit bits in the IO buffer are copied to the
SPI_ON must be set to 1. SPI_RX_TX_REG0 (and SPI_RX_TX_REG1 in case
of 32 bits mode) were they can be read by the CPU.
A SPI transfer cycle starts after writing to the
SPI_RX_TX_REG0. In case of 32 bits mode, the Interrupts to the ICU can be disabled using the
SPI_RX_TX_REG1 must be written first. Writing to SPI_MINT bit. To clear the SPI interrupt source, any
SPI_RX_TX_REG0 also sets the SPI_TXH. As soon value to SPI_CLEAR_INT_REG must be written. Note
as the holding register is copied to the IO buffer, the however that SPI_INT will be set as long as the RX-
SPI_TXH is reset and a serial transfer cycle of 8/9/16/ FIFO contains unread data.
32 clock-cycles is started which causes 8/9/16/32 bits

DA14580
Slave Mode (all 0’s after reset). This means that no dummy writes
are needed for reads only transfers.
The slave mode is selected with SPI_SMn set to 1 and
the Px_MODE_REG must also select SPI_CLK as In Slave Mode transfers only take place if the external
input. The functionality of the IO buffer in slave and master initiates them, but in master mode this means
master mode is identical. The SPI module clocks data that transfers will continue until the RX-FIFO is full. If
in on SPI_DI and out on SPI_DO on every active edge this happens SPI_CTRL_REG1[SPI_BUSY] will
of SPI_CLK. As shown in Figure 37 to Figure 40. The become ‘0’. If exactly N words need to be read from
SPI has an active low clock enable SPI_EN, which can SPI device, first read (N - fifosize+1) words. Then wait
be enabled with bit SPI_EN_CTRL=1. until the SPI_BUSY becomes ‘0’, set
SPI_FIFO_MODE to “00” and finally read the remain-
In slave mode the internal SPI clock must be more than
ing (fifosize +1) words. Here fifosize is 4/2/1 words for
four times the SPI_CLK
8/16/32 bits mode respectively.
In slave mode the SPI_EN serves as a clock enable
If this is not done, more data will be read from the SPI
and bit synchronization If enabled with bit
device until the FIFO is completely filled, or the SPI is
SPI_EN_CTRL. As soon as SPI_EN is deactivated
turned off.
between the MSB and LSB bits, the I/O buffer is reset.
Bidirectional Transfers with FIFO
SPI_POL and SPI_PHA
If SPI_FIFO_MODE is “00“, both registers are used as
The phase and polarity of the serial clock can be
a FIFO. SPI_TXH indicates that TX-FIFO is full,
changed with bits SPI_POL and SPI_PHA in the
SPI_INT indicates that there is data in the RX-FIFO.
SPI_CTRL_REG.
SPI_DO Idle Levels 15.2 9 BITS MODE
The idle level of signal SPI_DO depends on the master The 9 bits mode can be used to support 9 bits displays
or slave mode and polarity and phase mode of the and is selected with SPI_CTRL_REG[SPI_WORD] set
clock. to ‘11’. The value of the 9th bit, set in the
SPI_CTRL_REG1[SPI_9BIT_VAL] and is used to
In master mode pin SPI_DO gets the value of bit determine if the next 8 bits form a command word or
SPI_DO if the SPI is idle in all modes. Also if slave in data word. Because the 9th bit is not part of the data,
SPI modes 0 and 2, SPI_DO is the initial and final idle the FIFOs are still used in the 8 bits mode. The 9th bit
level. is received but not saved because it is shifted out of the
In SPI modes 1 and 3 however there is no clock edge 8 bits shift register upon reception.
after the sampled lsb and pin SPI_DO gets the lsb
value of the IO buffer. If required, the SPI_DO can be
forced to the SPI_DO bit level by resetting the SPI to
the idle state by shortly setting bit SPI_RST to 1.
(Optionally SPI_FORCE_DO can be set, but this does
not reset the IO buffer). The following diagrams show
the timing of the SPITM interface.
Writes Only Mode
In “writes only” mode (SPI_FIFO_MODE = “10“) only
the TX-FIFO is used. Received data will be copied to
the SPI_RX_TX_REGx, but if a new SPI transfer is fin-
ished before the old data is read from the memory, this
register will be overwritten.
SPI_INT acts as a tx_request signal, indicating that
there is still place in the FIFO. It will be ‘0’ when the
FIFO is full or else ‘1’ when it’s not full. This is also indi-
cated in the SPI_CTRL_REG[SPI_TXH], which is ‘1’ if
the TX-FIFO is full. Writing to the FIFO if this bit is still
1, will result in transmission of undefined data. If all
data has been transferred, SPI_CTRL_REG1
[SPI_BUSY] will become ‘0’.
Reads Only Mode
In “reads only” mode (SPI_FIFO_MODE = “01“) only
the RX-FIFO is used. Transfers will start immediately
when the SPI is turned on in this mode. In transmit
direction the SPI_DO pin will transmit the IO buffer
contents being the actual value of the SPI_TX_REGx

DA14580
SPI_CLK
SPI_DO (Master) SPI_DO MSB LSB SPI_DO
SPI_DO 1 (Slave) SPI_DO MSB LSB SPI_DO

^ write to SPI_RX_TX_REG0
SPI_DO 2 (Slave) MSB LSB SPI_DO

SPI_DI MSB LSB
SPI_EN (Slave)
Figure 37: SPI Master/Slave, Mode 0: SPI_POL=0 and SPI_PHA=0
Note 15: If 9 bits SPI mode, the MSB bit in transmit direction is determined by bit SPI_CTRL_REG[SPI_9BIT_VAL]. In receive direction, the MSB is
received but not stored.
SPI_CLK
SPI_DO (Slave) SPI_DO MSB LSB

SPI_DI MSB LSB
SPI_EN (Slave)
For the MSB bit refer to note 15.

DA14580
SPI_CLK
SPI_DO 1 (Slave) SPI_DO MSB LSB SPI_DO

SPI_DO 2 (Slave) MSB LSB SPI_DO

SPI_DI MSB LSB
SPI_EN (Slave)
SPI_CLK
SPI_DO (Slave) SPI_DO MSB LSB

SPI_DI MSB LSB
SPI_EN (Slave)

DA14580
16 Quadrature Decoder
The DA14580 has a integrated quadrature decoder
that can automatically decode the signals for the X, Y
and Z axes of a HID input device, reporting step count
QD_CHA_X
and direction. This block can be used for waking up the
chip as soon as there is any kind of movement from the QD_CHB_X
external device connected to it. The block diagram of
the quadrature decoder is presented in Figure 41.
Figure 43: Moving Backwards on Axis X
Features
• Three 16-bit signed counters that provide the step Depending on whether channel A or channel B is lead-
count and direction on each of the axes (X, Y and Z) ing in phase, the quadrature decoding block calculates
• Programmable system clock sampling at maximum the direction on the related axis. Furthermore, the
16 MHz. signed counter value represents the number of steps
moved.
• APB interface for control and programming
Since six channels are required (two for each axis), all
• Programmable source from P0, P1 and P2 ports
P0 and P1 signals and some of the P2 port can be
• Digital filter on the channel inputs to avoid spikes mapped onto this block. The user can choose which
GPIOs to use for the channels by programming the
QDEC_CTRL2_REG register.
The digital filter eliminates any spike shorter than two
APB Interface
clock periods. The counter holds the movement events
Register File
of the channel. When a channel is disabled the counter
is reset. The counters are accessible via the APB bus.
QD_CHA_X The quadrature decoder operates on the system clock.

Digital
16-bit Counter
Filter
(X Axis) The QDEC_CLOCKDIV register defines the number of

QD_CHB_X
clock cycles of the period at which the decoding logic
samples the data on the channel inputs.
QD_CHA_Y
Digital
16-bit Counter
Filter
QD_CHB_Y (Y Axis)
QD_CHA_Z
Digital
16-bit Counter
Filter
QD_CHB_Z (Z Axis)
Quad_Dec_IRQn
Interrupt Generator
Figure 41: Quadrature Decoder Block Diagram
Channels are expected to provide a pulse train with 90

degrees rotation as displayed in the following figures:
QD_CHA_X
QD_CHB_X
Figure 42: Moving Forward on Axis X

DA14580
17 Wake-Up Timer The block diagram illustrating the Wake-up function is

shown in Figure 44.
The Wake-up timer can be programmed to wake up the
DA14580 from power down mode after a prepro- Features
grammed number of GPIO events. • Monitors any GPIO state change
Each of the GPIO inputs can be selected to generate • Implements debouncing time from 0 up to 63 ms
an event by programming the corresponding
WKUP_SELECT_Px_REG register. When all • Accumulates external events and compares the
WKUP_SELECT_Px_REG registers are configured to number to a programmed value
generate a wake-up interrupt, a toggle on any GPIO • Generates an interrupt to the CPU
will wake up the system.
The input signal edge can be selected by programming
the WKUP_POL_Px_REG register.
P00
wkup_pol_p0_reg[0] +
wkup_select_p0_reg[0] &
. DEBOUNCE TIMER EVENT
. COUNTER WUPCT_IRQ
P37
wkup_pol_p3_reg[7] + .
> key_hit
wkup_select_p3_reg[7] &
WKUP_COMPARE_REG
wkup_ctrl_reg[6]
Figure 44: Wake-Up Timer Block Diagram
A LOW to HIGH level transition on the selected input A minimum pulse duration of 2 sleep clock cycles must
port, while WKUP_POL_Px_REG[y] = 0, sets internal be applied to the GPIO to ensure a successful system
signal “key_hit” to ‘1’. This signal triggers the event wake-up.
counter state machine as shown in Figure 45.
If the event counter is equal to the value set in the
The debounce timer is loaded with value
WKUP_COMPARE_REG register, the counter will be
WKUP_CTRL_REG[WKUP_DEB_VALUE]. The timer
reset and an interrupt will be generated, if it was
counts down every 1 ms. If the timer reaches 0 and the
enabled by WKUP_CTRL_REG[ENABLE_IRQ].
“key_hit” signal is still ‘1’, the event counter will be
incremented. The interrupt can be cleared by writing any value to
register WKUP_RESET_IRQ_REG.
The event counter is edge sensitive. After detecting an
The event counter can be reset by writing any value to
active edge a reverse edge must be detected first
register WKUP_RESET_CNTR_REG.
before it goes back to the IDLE state and from there
The value of the event counter can be read at any time
starts waiting for a new active edge.
by reading register WKUP_COUNTER_REG.
RST
IDLE
key_hit = 1
timer = DEBOUNCE
key_hit = 0 key_hit = 0 and
timer = 0
KEY_PRESSED timer not 0
key_hit = 1
key_hit = 1 and
KEY_RELEASE timer = 0
event_count = event_count +1
Figure 45: Event Counter State Machine for the Wake-Up Interrupt Generator

DA14580
18 General Purpose Timers Features

The Timer block contains 2 timer modules that are soft- • 16-bit general purpose timer
ware controlled, programmable and can be used for • Ability to generate 2 Pulse Width Modulated signals
various tasks. Timer 0 is a 16-bit general purpose timer (PWM0 and PWM1)
with a PWM output capability. Timer 2 is a 14-bit coun-
ter that generates three identical PWM signals in a • Programmable output frequency:
f = ------------------------------------------------------------------------
quite flexible manner. 16, 8, 4, 2 MHz or 32 kHz 
M + 1 + N + 1
18.1 TIMER 0
with N = 0 to (216-1), M = 0 to (216-1)
Timer 0 is a 16-bit general purpose software program-
mable timer, which has the ability of generating Pulse • Programmable duty cycle:
Width Modulated signals, namely PWM0 and PWM1. It M+1
 = --------------------------------------------  100 %
also generates the SWTIM_IRQ interrupt to the ARM M + 1 + N + 1
Cortex-M0. It can be configured in various modes
• Separately programmable interrupt timer:
regarding output frequency, duty cycle and the modula-
T = ------------------------------------------------------------------------
tion of the PWM signals. 16, 8, 4, 2 MHz or 32 kHz 
 ON + 1 
TIMER0_0N_REG TIMER0_RELOAD_N_REG TIMER0_RELOAD_M_REG

Timer 0 LSBreg MSBreg LSBreg MSBreg LSBreg MSBreg
1 0 1 0
loadnew loadnew
LSBshadow MSBshadow LSBshadow MSBshadow
T0-toggle 0 1
T0-counter=0 1 0
ON-counter 1 0
loadnew -1
loadnew LSBreg MSBreg
T0-counter
LSBreg MSBreg
TIM0_INT
Interrupt generation: If T0-counter = 0 then Compare T0_ge_M0
PWM mode: T0_toggle = ~T0_toggle
loadnew if (T0_toggle=0 and
ON-counter=0) OR
TIM0_CTRL =0->1 If PWM_MODE = 1 then AND signal with clock PWM0
to GPIO
If PWM_MODE = 1 then AND signal with clock PWM1
December 13, 2012
Figure 46: Timer 0 Block Diagram
Figure 46 shows the block diagram of Timer 0. The 16 selected by default with bit TIM0_CLK_SEL in the
bits timer consists of two counters: T0-counter and ON- TIMER0_CTRL_REG register. This ‘slow’ clock has no
counter, and three registers: enabling bit. The other four options can be selected by
TIMER0_RELOAD_M_REG, setting the TIM0_CLK_SEL bit and the TMR_ENABLE
TIMER0_RELOAD_N_REG and TIMER0_ON_REG. bit in the CLK_PER_REG (default disabled). This reg-
Upon reset, the counter and register values are ister also controls the frequency via the TMR_DIV bits.
0x0000. Timer 0 will generate a Pulse Width Modulated An extra clock divider is available that can be activated
signal PWM0. The frequency and duty cycle of PWM0 via bit TIM0_CLK_DIV of the timer control register
are determined by the contents of the TIMER0_CTRL_REG. This clock divider is only used
TIMER0_RELOAD_N_REG and the for the ON-counter and always divides by 10.
TIMER0_RELOAD_M_REG registers.
Timer 0 operates in PWM mode. The signals PWM0
The timer can run at five different clocks: 16 MHz, and PWM1 can be mapped to any GPIOs.
8 MHz, 4 MHz, 2 MHz or 32 kHz. The 32 kHz clock is
DA14580
Timer 0 PWM Mode TIMER0_RELOAD_N_REGregister (PWM0 is low).

The counter will then generate an interrupt
If bit TIM0_CTRL in the TIMER0_CTRL_REG is set,
(SWTIM_IRQ). The ON-counter will be reloaded with
Timer 0 will start running. SWTIM_IRQ will be gener-
the value of the TIMER0_ON_REG register. The T0-
ated and the T0-counter will load its start value from
counter as well as the M0-shadow register will be
the TIMER0_RELOAD_M_REG register, and will dec-
loaded with the value of the
rement on each clock. The ON-counter also loads its
TIMER0_RELOAD_M_REG register. At the same time,
start value from the TIMER0_ON_REG register and
the N0-shadow register will be loaded by the
decrements with the selected clock.
TIMER0_RELOAD_N_REG register. Both counters will
When the T0-counter reaches zero, the internal signal be decremented on the next clock again and the
T0-toggle will be toggled to select the sequence will be repeated.
TIMER0_RELOAD_N_REG whose value will be
Note that it is possible to generate interrupts at a high
loaded in the T0-counter. Each time the T0-counter
rate, when selecting a high clock frequency in combi-
reaches zero it will alternately be reloaded with the val-
nation with low counter values. This could result in
ues of the M0- and N0-shadow registers respectively.
missed interrupt events.
PWM0 will be high when the M0-value decrements and
low when the N0-value decrements. For PWM1 the During the time that the ON-counter is non-zero, new
opposite is applicable since it is inverted. If bit values for the ON-register, M0-register and N0-register
PWM_MODE in the TIMER0_CTRL_REG register is can be written, but they are not used by the T0-counter
set, the PWM signals are not HIGH during the ‘high until a full cycle is finished. More specifically, the newly
time’ but output a clock in that stage. The frequency is written values in the TIMER0_RELOAD_M_REG and
based on the clock settings defined in the TIMER0_RELOAD_N_REG registers are only stored
CLK_PER_REG register (also in 32 kHz mode), but into the shadow registers when the ON-counter and
the selected clock frequency is divided by two to get a the T0-counter have both reached zero and the T0-
50 % duty cycle. counter was decrementing the value loaded from the
TIMER0_RELOAD_N_REG register (see Figure 47).
If the ON-counter reaches zero it will remain zero until
the T0-counter also reaches zero, while decrementing
the value loaded from the
clk
TIM0_CTRL
M N M N M N
T0-counter 0 1 0 1 0 1 0 1 0 1 0 1
ON-counter 0 4 3 2 1 0 4 3 2
PWM0 pin
PWM1 pin
SWTIM_IRQ
M0=1 N0=1 ON=4
TIM0580-01
Figure 47: Timer 0 PWM Mode
At start-up both counters and the PWM0 signal are counter registers ON-counter and T0-counter can be
LOW so also at start-up an interrupt is generated. If read. When reading from the address of the ON-regis-
Timer 0 is disabled all flip-flops, counters and outputs ter, the value of the ON-counter is returned. Reading
are in reset state except for the ON-register, the from the address of either the
TIMER0_RELOAD_N_REG register and the TIMER0_RELOAD_N_REG or the
TIMER0_RELOAD_M_REG register. TIMER0_RELOAD_M_REG register, returns the value
of the T0-counter.
The timer input registers ON-register,
TIMER0_RELOAD_N_REGand It is possible to freeze Timer 0 with bit FRZ_SWTIM of
TIMER0_RELOAD_M_REG can be written and the the register SET_FREEZE_REG. When the timer is fro-

DA14580
zen the timer counters are not decremented. This will • Input clock frequency:
freeze all the timer registers at their last value. The
timer will continue its operation again when bit f IN = sys_clk
------------------- with N = 1, 2, 4 or 8
N
FRZ_SWTIM is cleared via register and sys_clk = 16 MHz or 32 kHz
RESET_FREEZE_REG.
• Programmable output frequency:
18.2 TIMER 2 f IN  f IN 
Timer 2 has three Pulse Width Modulated (PWM) out- f OUT =  ------ to  -----------------
-
 2  2 14 – 1
puts. The block diagram in shown in Figure 48.
Features • Three outputs with programmable duty cycle from
0 % to 100 %
• 14-bit general purpose timer
• Used for white LED intensity (on/off) control
• Ability to generate 3 Pulse Width Modulated signals
(PWM2, PWM3 and PWM4)
Timer 2
System bus
13 0 13 0 13 0 13 0
TRIPLE_PWM_FREQ PWM2_DUTY PWM3_DUTY PWM4_DUTY
Reset T2_PWM3
Set
equal3
3x14 bits equal1
Comparators
equal2
Reset
T2_PWM1
14 bits Set
sys_clk DIV
1/2/4/8 T2_DUTY_CNTR
Hold reset
+1
14 bits
/Reset block
=0
T2_FREQ_CNTR
+1 Reset T2_PWM2
TRIPLE_PWM_ENABLE Set
TRIPLE_PWM_CTRL_REG -1
SW_PAUSE_EN
RX_EN
TRIPLE_PWM_CTRL_REG
TX_EN HW_PAUSE_EN
Figure 48: Timer 2 PWM Block Diagram
The Timer 2 is clocked with the system clock divided by duty cycle of the T2_PWMn output signal. After the
TMR_DIV (1, 2, 4 or 8) and can be enabled with block is enabled, the counter starts from 0. If
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]. T2_DUTY_CNTR is equal to the value stored in the
respective PWMn_DUTY_CYCLE register, this resets
T2_FREQ_CNTR determines the output frequency of
the T2_PWMn output to 0. T2_DUTY_CNTR is reset
the T2_PMWn output. This counter counts down from
when TRIPLE_PWM_FREQUENCY is 0.
the value stored in register
TRIPLE_PWM_FREQUENCY. At counter value 0, Note that the value of PWMn_DUTY_CYCLE must be
T2_FREQ_CNTR sets the T2_PWMn output to ‘1’ and less or equal than TRIPLE_PWM_FREQUENCY.
the counter is reloaded again.
The Timer 2 is enabled/disabled by programming the
T2_DUTY_CNTR is an up-counter that determines the TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_EN] bit.

DA14580
The timing diagram of Timer 2 is shown in Figure 49. nals are zero), T2_DUTY_CNTR resumes counting
and finalizes the remaining part of the PWM duty cycle.
Freeze Function
TRIPLE_PWM_CTRL_REG[SW_PAUSE_EN] can be
During RF activity it may be desirable to temporarily
set to ‘0’ to disable the automatic, hardware driven
suppress the PWM switching noise. This can be done
freeze function of the duty counter and keep the duty
by setting
cycle constant.
TRIPLE_PWM_CTRL_REG[HW_PAUSE_EN] = 1.
The effect is that whenever there is a transmission or a Note that the RX_EN and TX_EN signals are not soft-
reception process from the Radio, T2_DUTY_CNTR is ware driven but controlled by the BLE core hardware.
frozen and T2_PWMx output is switched to ‘0’ to dis-
able the selected T2_PWM1, T2_PWM2, T2_PWM3.
As soon as the Radio is idle (i.e. RX_EN or TX_EN sig-
TMR2_CLK
TRIPLE_PWN_EN
T2_DUTY_CNTR 0 0 1 2 2 2 3 .. ... 0 1 2 3
T2_FREQ_CNTR N N N-1 N-2 N-3 ... ... 1 0 N N-1 N-2 N-3
T2_PWMn
Figure 49: Timer 2 PWM Timing Diagram

DA14580
19 Watchdog Timer • Non-Maskable Interrupt (NMI) or WDOG reset.

The Watchdog timer is an 8-bit timer with sign bit that • Optional automatic WDOG reset if NMI handler fails
can be used to detect an unexpected execution to update the Watchdog register.
sequence caused by a software run-away and can • Non-maskable Watchdog freeze of the Cortex-M0
generate a full system reset or a Non-Maskable Inter- Debug module when the Cortex-M0 is halted in
rupt (NMI). Debug state.
Features • Maskable Watchdog freeze by user program.
• 8 bits down counter with sign bit, clocked with a
10.24 ms clock for a maximum 2.6 s time-out.
Freeze Wake-up Timer, Software Timer, BLE master clock

WATCHDOG_CTRL_REG
Reset to 0xFF WATCHDOG_REG[8-0] [NMI_RST] Set
Set Set by Software
Cortex-M0 (debug) by SYS reset Reset
Reset Reset to 0
by SYS reset
DHCSR[S_HALT] Bits[15-9] =0
NMI_RST Write_enable 1
<= 0
1 OR Freeze <= -16 WDOG reset
SET_FREEZE_REG Watchdog timer 0
0 (default)
[FRZ_WDOG] 10.24 ms
Set 1
Reset =0 NMI
RESET_FREEZE_REG 0
[FRZ_WDOG]
Figure 50: Watchdog Timer Block Diagram
The 8 bits watchdog timer is decremented by 1 every address zero. Refer to the “POR/Reset” chapter for an
10.24 ms. The timer value can be accessed through overview of the complete reset circuit and conditions.
the WATCHDOG_REG register which is set to 255
For debugging purposes, the Cortex-M0 Debug
(FF16) at reset. This results in a maximum watchdog
module can always freeze the watchdog by setting the
time-out of ~2.6 s. During write access the DHCSR[DBGKEY | C_HALT | C_DEBUGEN] control
WATCHDOG_REG[WDOG_WEN] bits must be 0. This bits (reflected by the status bit S_HALT). This is
provides extra filtering for a software run-away writing automatically done by the debug tool, e.g. during step-
all ones to the WATCHDOG_REG. If the watchdog by-step debugging. Note that this bit also freezes the
counter reaches 0, the counter value will get a negative Wake-up Timer, the Software Timer and the BLE
value by setting bit 8. The counter sequence becomes master clock. For additional information also see the
1, 0, 1FF16 (-1), 1FE16(-2),...1F016 (-16). DEBUG_REG[DEBUGS_FREEZE_EN] mask register.
If WATCHDOG_CTRL_REG[NMI_RST] = 0, the The C_DEBUGEN bit is not accessible by the user
watchdog timer will generate an NMI if the watchdog software to prevent freezing the watchdog.
timer reaches 0 and a WDOG reset if the counter In addition to the S_HALT bit, the watchdog timer can
becomes less or equal to -16 (1F016). The NMI handler also be frozen if NMI_RST=0 and SET_FREEZE_REG
must write any value > -16 to the WATCHDOG_REG to [FRZ_WDOG] is set to ‘1’. The watchdog timer
prevent the generation of a WDOG reset at counter resumes counting when
value -16 after 16*10.24 = 163.8 ms. RESET_FREEZE_REG[FRZ_WDOG] is set to ‘1’. The
WATCHDOG_CTRL_REG[NMI_RST] bit can only be
If WATCHDOG_CTRL_REG[NMI_RST] = 1, the
set by software and will only be reset on a SYS reset.
watchdog timer generates a WDOG reset if the timer
Note that if the system is not remapped, i.e. SysRAM is
becomes less or equal than 0.
at address 0x20000000, then a watchdog fire will trig-
The WDOG reset is one of the SYS (system) reset ger the BootROM code to be executed again.
sources and resets the whole device, including setting
the WATCHDOG_REG register to 255, except for the
RST pin, the Power On reset, the HW reset and the
DBG (debug module) reset. Since the HW reset is not
triggered, the SYS_CTRL_REG[REMAP_ADR0] bits
will retain their value and the Cortex-M0 will start exe-
cuting again from the current selected memory at
DA14580
20 Keyboard Controller Features

The Keyboard controller can be used for debouncing • Monitors any of the 32 available GPIOs (12 in the
the incoming GPIO signals when implementing a key- WLCSP package, 22 in the QFN40 and 32 in the
board scanning engine. It generates an interrupt to the QFN48)
CPU (KEYBR_IRQ). • Generates a keyboard interrupt on key press or key
In parallel, five extra interrupt lines can be triggered by release
a state change on 32 selectable GPIOs (GPIOx_IRQ). • Implements debouncing time from 0 up to 63 ms
The block diagram of the Keyboard controller is pre- • Supports five separate interrupt generation lines
sented in the Figure 51. from GPIO toggling
INPUT_LEVELx
INPUT_LEVELx
DEBOUNCE TIMER
input1 GPIOx_IRQ
.
. + key_hit
.
edge/leveln
.
input32
INT_SELECTx Interrupt Generator x x = 0 .. 4
KBRD_LEVEL KBRD_Pxx_ENABLE
&
input1
.
+ DEBOUNCE TIMER
. . KEYBR_IRQ
key_hit
.
.
.
input32 + . edge/leveln
Keyboard Scanner
Figure 51: Keyboard Controller Block Diagram
20.1 KEYBOARD SCANNER KBRD_IRQ_IN_SEL0_REG[KBRD_REL] to ‘0’. The

A HIGH-to-LOW transition on one of the port inputs, inputs for the keyboard interface can be selected by
while KBRD_IRQ_IN_SEL0_REG[KBRD_LEVEL] = 0 setting the corresponding bits
and KBRD_IRQ_IN_SELx_REG[KBRD_Pyy_EN] = 1 KBRD_IRQ_IN_SEL0_REG[KBRD_Pxx_EN] to ‘1’.
sets internal signal “key_hit” to 1. This signal triggers The keyboard interrupt service routine can distinguish
the keyboard interface state machine as shown in which input has caused the interrupt by reading the
Figure 52. The debounce timer is loaded with value Px_DATA_REG registers.
GPIO_DEBOUNCE_REG[DEB_VALUE]. The timer
counts down every 1 ms. When the timer reaches 0 20.2 GPIO INTERRUPT GENERATOR
and the “key_hit” signal is still ‘1’, the timer is loaded Five identical GPIO interrupt generators support the
with KBRD_IRQ_IN_SEL0_REG[KEY_REPEAT], gen- generation of up to five interrupts (GPIO0_IRQ to
erating a repeating sequence of interrupts every time GPIO_4_IRQ). One of the GPIO inputs can be selected
the timer reaches 0. to generate an interrupt by programming the corre-
When the key is released (key_hit = 0) and bit sponding GPIO_IRQx_IN_SEL_REG register. The
KBRD_REL (key release) is set to ‘1’, a new debounce input level can be selected by
sequence is started and a KEYBR_IRQ interrupt is GPIO_INT_LEVEL_CTRL_REG[INPUT_LEVELx].
generated after the debounce time. A LOW-to-HIGH level transition on one of the port
The debounce timer can be disabled with inputs, while bit INPUT_LEVELx = 0, sets internal sig-
GPIO_DEBOUNCE_REG[DEB_ENABLE_KBRD] = 0. nal “key_hit” to ‘1’. This signal triggers the GPIO Inter-
The key repeat function can be disabled by setting rupt Generator state machine as shown in Figure 52.
KEY_REPEAT to ‘0’. The debounce timer is loaded with value
GPIO_DEBOUNCE_REG[DEB_VALUE]. The timer
The level for generating an interrupt is programmable counts down every 1 ms. If the timer reaches 0 and the
via bit KBRD_IRQ_IN_SEL0_REG[KBRD_LEVEL]. “key_hit” signal is still ‘1’, an interrupt will be generated.
The key release function can be disabled by setting bit The debounce timer for each interrupt can be disabled

DA14580
with GPIO_DEBOUNCE_REG[DEB_ENABLEx]. For detecting both signal edges the edge polarity
INPUT_LEVELx must be inverted in the
The interrupt flag will remain set until it is reset by writ-
WAIT_FOR_RELEASE state. This will result in
ing to the corresponding bit in the
“key_hit” = 0 and will advance the state machine to the
GPIO_RESET_IRQ_REG register. When the GPIO
Idle state, allowing detection of the next inverted edge.
interrupt is edge sensitive, selected with bit
GPIO_INT_LEVEL_CTRL_REG[EDGE_LEVELNx],
the state machine will progress to state
WAIT_FOR_RELEASE when the interrupt is reset. It
will progress to the IDLE state only after detecting the
non-active edge.
RST KEYBR_IRQ = 0
key_hit = 1
IDLE debounce = 0
key_hit = 1
key_hit = 0 and timer = DEBOUNCE
KEYBR_IRQ = 1 timer = 0
KEY_RELEASED KEY_PRESSED timer not 0
key_hit = 1 and
timer = 0 key_hit = 0 and key_hit = 1 and
key_hit = 0 and KEY_REL = 0 timer = 0
timer = 0
key_hit = 0 KEYB_INT = 0
and KEY_REL = 1
KEY_RELEASING KEY_VALID KEYBR_IRQ
timer = DEBOUNCE
key_hit = 0 and
timer not 0 KEY_REL = 0 KEYBR_IRQ = 1
key_hit = 0 and key_hit = 1 and
KEY_REPEAT != 0 key_hit = 1 and
KEY_REL = 1 and timer = 0
debounce > 0
key_hit = 0 and KEY_REPEAT timer = KEY_REPEAT
KEY_REL = 1 and
debounce = 0 timer not 0
Figure 52: Keyboard Scanner State Machine
RST GPIOx_IRQ = 0
IDLE
key_hit = 1 and DEB_ENABLE_KBRD = 1
key_hit = 0 timer = DEBOUNCE
key_hit = 1
key_hit = 0 and
timer = 0
WAIT_FOR_RELEASE
KEY_PRESSED timer not 0
key_hit = 1 and
GPIOx_IRQ = 0
DEB_ENABLE_KBRD = 0 GPIOx_IRQ = 0
reset_interrupt = 1 and
edge_leveln = 0 key_hit = 1 and
timer = 0
reset_interrupt = 1 and
edge_leveln = 1
KEY_VALID reset_int = 0
GPIOx_IRQ = 1
Figure 53: GPIO Interrupt Generator State Machine

DA14580
21 Input/Output Ports • Fully programmable pin assignment

The DA14580 has software-configurable I/O pin • Selectable 25 k pull-up, pull-down resistors per pin
assignment, organized into ports Port 0, Port1, Port2 • Pull-up voltage either VBAT3V (BUCK mode) or
and Port 3. Port 2 is only available at the QFN40 pack- VBAT1V (BOOST mode) configurable per pin
age while ports 2 and 3 are available at the QFN48
package. • Fixed assignment for analog pin ADC[3:0]
Features • Pins retain their last state when system enters the
Extended or Deep Sleep mode.
• Port 0: 8 pins, Port 1: 6 pins (including SW_CLK and
SWDIO), Port 2: 10 pins, Port 3: 8 pins
Px[y]
Peripheral X input
Px_DATA_REG (input)
VBAT3V or VBAT1V
PUPD
Px_MODE_REG
PID
Peripheral X output
Px[y] Peripheral Y output Px_RESET_OUTPUT_DATA_REG
Px_DATA_REG (output)
Px_SET_OUTPUT_DATA_REG
VSS
Figure 54: Port P0, P1, P2 and P3 with Programmable Pin Assignment
21.1 PROGRAMMABLE PIN ASSIGNMENT Direction Control

The Programmable Pin Assignment (PPA) provides a The port direction is controlled by setting:
multiplexing function to the I/Os of on-chip peripherals.
Any peripheral input or output signal can be freely Pxy_MODE_REG[9-8]
mapped to any I/O port bit by setting: 00 = Input, no resistors selected
Pxy_MODE_REG[4-0]: 01 = Input, pull-up selected
10 = Input, Pull-down selected
0x00 to 0x16: Peripheral IO ID (PID) 11 = Output, no resistors selected
Refer to the Px_MODE_REGs for an overview of the In output mode and analog mode the pull-up/down
available PIDs. Analog ADC has fixed pin assignment resistors are automatically disabled.
in order to limit interference with the digital domain.
The SWD interface (JTAG) is mapped on P1_4 and 21.2 GENERAL PURPOSE PORT REGISTERS
P1_5. The general purpose ports are selected with PID=0.
Priority The port function is accessible through registers:
The firmware has the possibility to assign the same • Px_DATA_REG: Port data input/output register
peripheral output to more than one pin. It is the respon- • Px_SET_OUTPUT_DATA_REG: Port set output reg-
sibility of the user to make a unique assignment. ister
In case more than one input signal is assigned to a • Px_RESET_OUTPUT_DATA_REG: Port reset out-
peripheral input, the left most pin in the lowest port pin put register
number has priority. (e.g P00_MODE_REG has priority
over P01_MODE_REG)

DA14580
21.2.1 Port Data Register 21.2.2 Port Set Data Output Register
The registers input Px_DATA_REG and output Writing a 1 in the set data output register
Px_DATA_REG are mapped on the same address. (Px_SET_OUTPUT_DATA_REG) sets the correspond-
ing output pin. Writing a 0 is ignored.
The data input register (Px_DATA_REG) is a read-only
register that returns the current state on each port pin
21.2.3 Port Reset Data Output Register
even if the output direction is selected, regardless of
the programmed PID, unless the analog function is Writing a 1 in the reset data output register
selected (in this case it reads 0). The ARM CPU can (Px_RESET_OUTPUT_DATA_REG) resets the corre-
read this register at any time even when the pin is con- sponding output pin. Writing a 0 is ignored.
figured as an output.
21.3 FIXED ASSIGNMENT FUNCTIONALITY
The data output register (Px_DATA_REG) holds the
data to be driven on the output port pins. In this config- There are certain signals that have a fixed mapping on
uration, writing to the register changes the output specific general purpose IOs. This assignment is illus-
value. trated in the following table:
Table 22: Fixed Assignment of Specific Signals
GPIO SWD QUAD DEC ADC (Note 16)

P0_0 CHY_A/CHX_A/CHZ_A ADC_0
P0_1 CHY_B/CHX_B/CHZ_B ADC_1
P0_2 CHY_A/CHX_A/CHZ_A ADC_2
P0_3 CHY_B/CHX_B/CHZ_B ADC_3
P0_4 CHY_A/CHX_A/CHZ_A
P0_5 CHY_B/CHX_B/CHZ_B
P1_4 SW_CLK CHY_A/CHX_A/CHZ_A
P1_5 SWDIO CHY_B/CHX_B/CHZ_B
Note 16: The ADC case can be selected by the PID bit field on the respective P port. However, the mapping of the Quad Decoder signals on the
respective pins, is overruled by the QDEC_CTRL_REG[CHx_PORT_SEL] register. Furthermore, the SWD signals mapping is defined by
SYS_CTRL_REG[DEBUGGER_ENABLE]. However, these signals are mapped on the ports by default.

DA14580
22 General Purpose ADC • Ultra low power (5 A typical supply current at

100 ksample/s)
The DA14580 is equipped with a high-speed ultra low
power 10-bit general purpose Analog-to-Digital Con- • Single-ended as well as differential input with two
verter (GPADC). It can operate in unipolar (single input scales
ended) mode as well as in bipolar (differential) mode. • Four single-ended or two differential external input
The ADC has its own voltage regulator (LDO) of 1.2 V, channels
which represents the full scale reference voltage.
• Battery monitoring function
Features
• Chopper function
• 10-bit dynamic ADC with 65 ns conversion time
• Offset and zero scale adjust
• Maximum sampling rate 3.3 Msample/s
• Common-mode input level adjust
GP_ADC_SEL
General Purpose ADC
P0_0
P0_1
GP_ADC_SE
P0_2 VDCDC
1
P0_3 GP_ADC_ATTN3X
1.2V
P0_0 0 LDO
GP_ADC_ATTN3X Vref=1.2V
P0_2
200kOhm
ADC
P0_1 100kOhm
100kOhm
P0_3
VDCDC
VBAT3V
VBAT1V
VDD_RTT
AVS
VDD_REF
GP_ADC_SE
200kOhm
GP_ADC_ATTN3X
GP_ADC_ATTN3X
Figure 55: Block Diagram of the General Purpose ADC
22.1 INPUT CHANNELS AND INPUT SCALE Single-ended or differential operation is selected via bit
The DA14580 has a multiplexer between the ADC and GP_ADC_CTRL_REG[GP_ADC_SEL]. In differential
four specific GPIO ports (P0_0 to P0_3). Furthermore, mode the voltage difference between two GPIO input
the ADC can also be used to monitor the battery volt- ports will be converted. Via bit
age and several internal voltages of the system (see GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] the input
GP_ADC_CTRL_REG). scale can be enlarged by a factor of three, as summa-
rized in Table 23.
Table 23: GPADC Input Channels and Voltage Scale
GP_ADC_ATTN3X GP_ADC_SE Input Channels Input Scale Input Limits

0 1 P0_0, P0_1, P0_2, P0_3 0 V to +1.2 V -0.1 V to +1.3 V
0 0 [P0_0, P0_1], [P0_2, P0_3] -1.2 V to +1.2 V -1.3 V to +1.3 V
1 1 P0_0, P0_1, P0_2, P0_3 0 V to +3.6 V -0.1 V to +3.45 V
1 0 [P0_0, P0_1], [P0_2, P0_3] -3.6 V to +3.6 V -3.45 V to +3.45 V
22.2 STARTING THE ADC AND SAMPLING RATE power, except for the LDO which consumes less than
The GPADC is a dynamic ADC and consumes no static 5 A.

DA14580
Enabling/disabling of the ADC is triggered by configur- to zero. Bit GP_ADC_IDYN enables a 10 A load cur-
ing bit GP_ADC_CTRL_REG[GP_ADC_LDO_EN]. rent during sampling phase so that the load current
After enabling the LDO, a settling time of 20 s is during sampling and conversion phase becomes
required before an AD-conversion can be started. approximately the same.
Each conversion has two phases: the sampling phase 22.4 CHOPPING
and the conversion phase. When bit
GP_ADC_CTRL_REG[GP_ADC_EN] is set to ‘1’, the Chopping is a technique to cancel offset by taking two
ADC continuously tracks (samples) the selected input samples with opposite signal polarity. This method also
voltage. Writing a '1' at bit smooths out other non-ideal effects and is recom-
GP_ADC_CTRL_REG[GP_ADC_START] ends the mended for DC and slowly changing signals.
sampling phase and triggers the conversion phase. Chopping is enabled by setting bit
When the conversion is ready, the ADC resets bit GP_ADC_CTRL_REG[GP_ADC_CHOP] to ‘1’.
GP_ADC_START to ‘0’ and returns to the sampling
phase. The mid-scale value of the ADC is the 'natural' zero
point of the ADC (ADC result = 511.5 = 1FF or 200 Hex
The conversion itself is fast and takes approximately = 01.1111.1111 or 10.0000.0000 Bin). Ideally this corre-
one clock cycle of 16 MHz, though the data handling sponds to Vi = 1.2 V/2 = 0.6 V in single-ended mode
will require several additional clock cycles, depending and Vi = 0.0 V in differential mode.
on the software code style. The fastest code can han-
dle the data in four clock cycles of 16 MHz, resulting to If bit GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] is set
a highest sampling rate of 16 MHz/5 = 3.3 Msample/s. to ‘1’, the zero point is 3 times higher (1.8 V single-
ended and 0.0 V differential).
At full speed the ADC consumes approximately 50 A.
If the data rate is less than 100 ksample/s, the current With bit GP_ADC_CTRL_REG[GP_ADC_MUTE], the
consumption will be in the range of 5 A. ADC input is switched to the centre scale input level,
so the ADC result ideally is 511.5. If instead a value of
22.3 NON-IDEAL EFFECTS 515 is observed, the output offset is +3.5 (adc_off_p =
Besides Differential Non-Linearity (DNL) and Integral 3.5).
Non-Linearity (INL), each ADC has a gain error (linear) With bit GP_ADC_CTRL_REG[GP_ADC_SIGN] the
and an offset error (linear). The gain error of the sign of the ADC input and output is changed. Two sign
GPADC slightly reduces the effective input scale (up to changes have no effect on the signal path, though the
50 mV). The offset error causes the effective input sign of the ADC offset will change.
scale to become non-centred. The offset error of the
GPADC is less than 20 mV and can be reduced by If adc_off_p = 3.5 the ADC_result with opposite
chopping or by offset calibration. GP_ADC_SIGN will be 508. The sum of these equals
515 + 508 = 1023. This is the mid-scale value of an 11-
The ADC result will also include some noise. If the bit ADC, so one extra bit due to the over-sampling by a
input signal itself is noise free (inductive effects factor of two.
included), the average noise level will be ±1 LSB. Tak-
ing more samples and calculating the average value The LSB of this 11-bit word should be ignored if a 10-
will reduce the noise and increase the resolution. bit word is preferred. In that case the result is 511.5, so
the actual output value will be 511 or 512.
With a 'perfect' input signal (e.g. if a filter capacitor is
placed close to the input pin) most of the noise comes 22.5 OFFSET CALIBRATION
from the low-power voltage regulator (LDO) of the A relative high offset caused by a very small dynamic
ADC. Since the DA14580 is targeted for ultra-compact comparator (up to 20 mV, so approximately 20 LSB).
applications, there is no pin available to add a capaci-
tor at this voltage regulator output. This offset can be cancelled with the chopping function,
but it still causes unwanted saturation effects at zero
The dynamic current of the ADC causes extra noise at scale or full scale. With the GP_ADC_OFFP and
the regulator output. This noise can be reduced by set- GP_ADC_OFFN registers the offset can be compen-
ting bits GP_ADC_CTRL2_REG[GP_ADC_I20U] and sated in the ADC network itself.
GP_ADC_CTRL2_REG[GP_ADC_IDYN] to ‘1’. Bit
GP_ADC_I20U enables a constant 20 A load current To calibrate the ADC follow the steps in Table 24.
at the regulator output so that the current will not drop
Table 24: GPADC Calibration Procedure for Single-Ended and Differential Modes
Step Single-Ended Mode (GP_ADC_SE = 1) Differential Mode (GP_ADC_SE = 0)

1 Set GP_ADC_OFFP = GP_ADC_OFFN=0x200; Set GP_ADC_OFFP=GP_ADC_OFFN = 0x200;
GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0 GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0
2 Start conversion Start conversion
3 adc_off_p = GP_ADC_RESULT - 0x200 adc_off_p = GP_ADC_RESULT - 0x200

DA14580
Table 24: GPADC Calibration Procedure for Single-Ended and Differential Modes
Step Single-Ended Mode (GP_ADC_SE = 1) Differential Mode (GP_ADC_SE = 0)

4 Set GP_ADC_SIGN = 0x1 Set GP_ADC_SIGN = 0x1
5 Start conversion Start conversion
6 adc_off_n = GP_ADC_RESULT - 0x200 adc_off_n = GP_ADC_RESULT - 0x200
7 GP_ADC_OFFP = 0x200 - 2*adc_off_p GP_ADC_OFFP = 0x200 - adc_off_p
GP_ADC_OFFN = 0x200 - 2*adc_off_n GP_ADC_OFFN = 0x200 - adc_off_n
Note: The average of GP_ADC_OFFP and GP_ADC_OFFN should be 0x200 (with a margin of 20 LSB)
It is recommended to implement the above calibration scale level so the input impedance is infinite.
routine during the initialization phase of the DA14580.
At 100 ksample/s, zero or full-scale single-ended input
To verify the calibration results, check whether the
signal, this sampling capacitor will load the input with:
GP_ADC_RESULT value is close to 0x200 while bit
ILOAD = V * C * fS = ±0.6 V * 0.2 pF * 100 kHz = ±12 nA
GP_ADC_MUTE = 1.
(differential: ±1.2 V * 0.2 pF * 100 kHz = ±24 nA at both
22.6 ZERO-SCALE ADJUSTMENT pins).
The GP_ADC_OFFP and GP_ADC_OFFN registers During sampling phase a certain settling time is
can also be used to set the zero-scale or full-scale required. A 10-bit accuracy requires at least 7 time
input level at a certain target value. For instance, they constants of the output impedance of the input signal
can be used to calibrate GP_ADC_RESULT to 0x000 source and the 0.2 pF sampling capacitor. The conver-
at an input voltage of exactly 0.0 V, or to calibrate the sion time is approximately one clock cycle of 16 MHz
zero scale of a sensor. (62.5 ns).
22.7 COMMON MODE ADJUSTMENT 7 * ROUT * 0.2 pF - 62.5 ns < 1/fS

The common mode level of the differential signal must => ROUT < (1 + 62.5 ns * fS) / (7 * 0.2 pF * fS)
be 0.6 V (or 1.8 V with GP_ADC_ATTN3X = 1). If the Examples:
common mode input level of 0.6 V cannot be achieved,
the common mode level of the GP_ADC can be ROUT < 7.2 M at fS = 100 kHz
adjusted (the GP_ADC can tolerate a common mode ROUT < 760 k at fS = 1 MHz
margin up to 50 mV) according to Table 25.
The inductance from the signal source to the ADC
Table 25: Common Mode Adjustment input pin must be very small. Otherwise, filter capaci-
tors are required from the input pins to ground (differ-
CM Voltage ential mode: from pin to pin).
GP_ADC_OFFP = GP_ADC_OFFN
(Vcmm) To observe the noise level of the ADC and the voltage
0.3 V 0x300 regulator, bit GP_ADC_CTRL_REG[GP_ADC_MUTE]
must be set to ‘1’. The noise should be less than ±1
0.6 V 0x200 LSB on average, with occasionally a ±2 LSB peak
0.9 V 0x100 value. If a higher noise level is observed on the input
channel(s), applying filter capacitor(s) will reduce the
Any other common mode level between 0.0 V and noise.
1.2 V can be calculated from the table above. Offset The 3x input attenuator is realized with a resistor
calibration can be combined with common mode divider network. When bit
adjustment by replacing the 0x200 value in the offset GP_ADC_CTRL_REG2[GP_ADC_ATTN3X] is set to
calibration routine by the value required to get the ‘1’, the input impedance of the selected ADC input
appropriate common mode level. channel becomes 300 k (typical) instead of infinite. In
Note: The input voltage limits for the ADC in differential addition, the resistor divider network will require more
mode are: -1.3 V to +1.3 V (for GP_ADC_ATTN3X = 0, settling time in the sampling phase. The general guide-
see Table 23). The differential input range of the ADC line with bit GP_ADC_ATTN3X = 1 is: select the input
is: -1.2 V < V[P0_0,P0_1] < +1.2 V. Therefore, if Vcmm channel, then wait 1 s (16 clock cycles) before start-
< 0.5 V or Vcmm > 0.7 V, the input can no longer cover ing the conversion. Only the required sampling time is
the whole ADC range. affected by the attenuator, the conversion time remains
approximately one clock cycle of 16 MHz (62.5 ns).
22.8 INPUT IMPEDANCE, INDUCTANCE AND Note: Selecting the battery measurement channel
INPUT SETTLING
automatically activates the 3x input attenuator (bit
The GPADC has no input buffer stage. During sam- GP_ADC_ATTN3X = 1). Therefore the 1 s waiting
pling phase a capacitor of 0.2 pF is switched to the time also applies when measuring the battery voltage,
input line. The precharge of this capacitor is at mid- otherwise the resulting Vbat level will be too low.

DA14580
22.9 DELAY COUNTER

The GPADC has a delay counter that can be used to
add delays to several ADC control signals. A delay of
up to 32 s can added for the bits GP_ADC_LDO_EN,
GP_ADC_START and GP_ADC_EN via registers
GP_ADC_DELAY_REG and GP_ADC_DELAY2_REG.
The reset values of these two registers are the recom-
mended values for a correct start-up, since it is not
allowed to activate all signals at once.
To make use of the delay counter for a certain signal,
the corresponding bit has to be set in register
GP_ADC_CTRL_REG and the delay counter must be
enabled via bit GP_ADC_DELAY_EN in register
GP_ADC_CTRL2_REG. The delay counter starts
counting when the GP_ADC_START bit is pro-
grammed while the GP_ADC_DELAY_EN bit is set.
The counter is stopped after the conversion is finished.
The delay counter must be reset before reuse, which is
typically only required after the LDO was disabled. Bit
GP_ADC_DELAY_EN must be made zero to reset the
counter. It is recommended to check that this bit is zero
before (re)activating it.

DA14580
23 Power Management • Boost (step-up) converter, starting from 0.9 V,

when running from an Alkaline/NiMH cell.
The DA14580 has a complete power management
function integrated with Buck or Boost DC-DC con- • Buck (step-down) converter for increased effi-
verter and separate LDOs for the different power ciency when running from a Lithium coin-cell or 2
domains of the system. The system diagram of the Alkaline batteries down to 2.35 V.
analog power block is presented in Figure 56. • Battery voltage measurement ADC (multiplexed
Features input from general purpose ADC)
• On-chip LDOs, without external capacitors • Use of small external components (2.2 H inductor
and 1F capacitor)
• Synchronous DC-DC converter which can be config-
ured as either:
< 3.3 V
VBATxV-levels
VBAT1V SWITCH
< 0.9 V GPIO bandg.

VBAT3V
on
VDCDC
boost con.
Alkaline cell
(0.9 V to 1.8 V) LDO LDO LDO
RET SYS various
Lithium coin-cell
VDD
(2.35 V to 3.3 V)
enable_buck on Dig.
buck conv. core ADC
VPP OTP LDO

OTP RF
memory 2.5 V
Retention VDD
PMU 16 MHz
32 kHz memories
Figure 56: Block Diagram of the Analog Power Block and Internal Interconnections
The Power Block contains a DC-DC converter which 4. LDO (various): This a group of LDOs used for the
can be configured to operate as a Step-Up or a Step- elaborate control of the powering up/down of the
Down converter. The converter provides power to four Radio, the GP ADC and the XTAL16M oscillator.
LDO groups in the system:
There are two ways of connecting external batteries to
1. LDO RET: This is the LDO providing power to the the Power Block of the DA14580. They depend on the
Retention domain (PD_AON). It powers the Retention specific battery cell used and its voltage range. Battery
RAMs and the digital part which is always on. cells are distinguished into Lithium coin cells (2.35 V to
3.3 V) and Alkaline cells (1.0 V to 1.8 V). The connec-
2. LDO OTP: This is the LDO powering the OTP macro
tion diagrams are presented in Figure 58 and Figure 57
cell. This is the reason for using the step-up DC-DC
respectively:
converter when running from an Alkaline battery.
3. LDO SYS: This is the LDO providing the system with
the actual VDD power required for the digital part to
operate. Note that the Power Block implements seam-
less switching from the LDO SYS to the LDO RET
when the system enters Deep Sleep mode. In the latter
case, a low voltage is applied to the PD_AON power
domain to further reduce leakage.

DA14580
VDCDC_RF
VBAT_RF
2.35 V to 3.3 V
SWITCH
VBAT3V
VDCDC
Lithium
coin-cell
LDO LDO
LDO
analog/RF
digital analog/RF
retention
VBAT1V
Buck Converter
DA14580
Figure 57: Supply Overview, Coin-Cell Application
0.9 V to 2.0 V
VBAT1V SWITCH
internal supply for boost conv. VBAT3V

< 0.9 V
VDCDC
Alkaline on
or
NiMH
Boost Converter
VDCDC_RF
LDO LDO LDO
VBAT_RF
digital analog/RF
retention
DA14580
Figure 58: Supply Overview, Alkaline-Cell Application
The usage of Boost or Buck mode with respect to the

provided voltage ranges is illustrated in the following
figure which also illustrates the efficiency of the engine
assuming a 10 mA constant load.

DA14580
DC‐DC Efficiency vs Voltage
95%
90%
85%
80%
75%
70%
65%
60%
55%
50% 0.9 1.8 2.35
0 0.5 1 1.5 2 2.5 3 3.5
Buck Boost Boost (Vout > 1.4 V)
Figure 59: DC-DC Efficiency in Buck/Boost Mode at

Various Voltage Levels
The X axis represents the supply voltage. BOOST

mode should be used when voltage ranges from 0.9 V
to 2.0 V to sustain a decent efficiency over 70 %. From
that point on, the power dissipation becomes quite
large.
BUCK mode can operate correctly with voltages in the
range of 2.35 V to 3.3 V.
There are two voltage areas in Figure 59 designated by
dashed lines. The first one (0 V to 0.9 V) indicates that
the DA14580 is not operational when the voltage is
below 0.9 V. This is the absolute threshold for the DC-
DC converter Boost mode.
The second area (1.8 V to 2.2 V) indicates that Deep
Sleep mode is not allowed when the DC-DC converter
is configured in BUCK mode and the voltage is within
this range, because the OTP will not be readable any
more. However, this part of the voltage range can be
covered by the BOOST mode. Furthermore, when
BUCK mode is mandatory, Extended Sleep mode can
be activated instead of Deep Sleep mode, thus not
using the OTP for the code mirroring but retain the
code in SysRAM.
Note: The system should never be cold booted when
the supply voltage is less than 2.5 V. A manual power
up with a power supply less than 2.5 V in buck mode
might create instability.

DA14580
24 BLE Core • FDMA/TDMA/events formatting and synchronization

The BLE (Bluetooth low energy) core is a qualified • Frequency hopping calculation
Bluetooth baseband controller compatible with the • Operating clock 16 MHz or 8 MHz
Bluetooth low energy 4.2 specification and it is in
charge of packet encoding/decoding and frame sched- • Low power modes supporting 32.0 kHz or
uling. 32.768 kHz
The block diagram is presented in Figure 60. • Supports power down of the baseband during the
protocol’s idle periods
Features
• AHB Slave interface for register file access
• All device classes support (Broadcaster, Central,
Observer, Peripheral) • AHB Slave interface for Exchange Memory access
of CPU via BLE core
• All packet types (Advertising / Data / Control)
• AHB Master interface for direct access of BLE core
• Encryption (AES / CCM) to Exchange Memory space
• Bit stream processing (CRC, Whitening)
AHB AHB
Slave Master
BLE Timer Exchange

(Timing Memory
Generators) mapping
Radio BLE Core
Test MUXes Registers Bus Interface
Control
Radio Frequency Interrupt AES
Memory Controller
Controller Selection Generator CCM
Data
Packet Event White List Event
Whitening CRC
Controller Controller Search Scheduler
Figure 60: BLE Core Block Diagram
24.1 EXCHANGE MEMORY

The BLE Core requires access to a memory space
named “Exchange Memory” to store control structures
and frame buffers. The access to Exchange Memory is
performed via the AHB Master interface. The mapping
of the BLE Core address space to the System Bus
address space is controlled via the register bit field
GP_CONTROL_REG[EM_MAP]. Figure 61 illustrates
all the address mapping options.

DA14580
Case 0 Case 1 Case 2 Case 3 Case 4 Case 5 Case 6 Case 7 Case 9 Case 10 Case 11
i.e. no remap (BLE EM: 2 kB) (BLE EM: 3 kB) (BLE EM: 4 kB) (BLE EM: 5 kB) (BLE EM:6 kB) (BLE EM: 7 kB) (BLE EM: 8 kB) (BLE EM: 4 kB) (BLE EM: 5 kB) (BLE EM: 6 kB)
(BLE EM: 0 kB) (SysRAM: 48 kB) (SysRAM: 47 kB) (SysRAM: 46 kB) (SysRAM: 45 kB) (SysRAM: 44 kB) (SysRAM: 43 kB) (SysRAM: 42 kB) (SysRAM: 40 kB) (SysRAM: 40 kB) (SysRAM: 40 kB)
(SysRAM: 42 kB)
0x2000.C000
RetRAM4
1 kB
RetRAM3 RetRAM3
2 kB 2 kB RetRAM4
1 kB
RetRAM4
1 kB
RetRAM2 RetRAM2 RetRAM2
3 kB 3 kB 3 kB RetRAM3 RetRAM3
2 kB 2 kB RetRAM4
1 kB
0x2000.A800
SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM
Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0
2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB
0x2000.A000
SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM SysRAM
Page 1 Page 1 Page 1 Page 1 Page 1 Page 1 Page 1 Page 1 Page 1 Page 1 Page 1
2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB 2 kB
0x2000.9800
~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM
0x2000.0000
0x0008.3000
~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
0x0008.2000
RetRAM4 RetRAM4
1 kB 1 kB
RetRAM3 RetRAM3 RetRAM3

2 kB RetRAM4 2 kB 2 kB
1 kB SysRAM
Page 0
SysRAM 2 kB
Page 0
RetRAM2 RetRAM2 RetRAM2 RetRAM2 RetRAM2 2 kB
3 kB 3 kB 3 kB 3 kB 3 kB SysRAM
RetRAM3 RetRAM3
Page 0
RetRAM4 2 kB RetRAM4 2 kB
2 kB
1 kB 1 kB
0x0008.0800
RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM
0x0008.0000
Case 12 Case 13 Case 14 Case 15 Case 17 Case 18 Case 19 Case 20 Case 21 Case 22 Case 23
(BLE EM: 7 kB) (BLE EM: 8 kB) (BLE EM: 9 kB) (BLE EM:10 kB) (BLE EM: 6 kB) (BLE EM: 7 kB) (BLE EM: 8 kB) (BLE EM: 9 kB) (BLE EM: 10 kB) (BLE EM: 11 kB) (BLE EM: 12 kB)
(SysRAM: 40 kB) (SysRAM: 40 kB) (SysRAM: 40 kB) (SysRAM: 40 kB) (SysRAM: 38 kB) (SysRAM: 38 kB) (SysRAM: 38 kB) (SysRAM: 38 kB) (SysRAM: 38 kB) (SysRAM: 38 kB) (SysRAM: 38 kB)
0x2000.C000
0x2000.A800
0x2000.A000
SysRAM SysRAM SysRAM SysRAM
Page 1 Page 1 Page 1 Page 1
2 kB 2 kB 2 kB 2 kB
0x2000.9800
~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~~ SysRAM ~
0x2000.0000
0x0008.3000
~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~
SysRAM
Page 1
SysRAM 2 kB
Page 1
SysRAM SysRAM 2 kB SysRAM
Page 0 Page 1 Page 0
SysRAM 2 kB SysRAM 2 kB SysRAM 2 kB
0x0008.2000 Page 0 Page 1 Page 0
2 kB RetRAM4 2 kB 2 kB RetRAM4
SysRAM 1 kB SysRAM SysRAM 1 kB
SysRAM 2 kB SysRAM 2 kB SysRAM 2 kB
RetRAM3 RetRAM3 RetRAM3 RetRAM3
RetRAM4 2 kB 2 kB RetRAM4 2 kB 2 kB
2 kB SysRAM 2 kB SysRAM 2 kB
1 kB 1 kB
Page 1 Page 0
2 kB SysRAM 2 kB
Page 0
RetRAM2 RetRAM2 RetRAM2 RetRAM2 2 kB RetRAM2 RetRAM2 RetRAM2 RetRAM2
3 kB 3 kB 3 kB 3 kB SysRAM 3 kB 3 kB 3 kB 3 kB
RetRAM3
Page 0
RetRAM4 2 kB
2 kB
1 kB
0x0008.0800
RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM RetRAM
0x0008.0000
Figure 61: Exchange Memory Mapping Possibilities

DA14580
There are 24 different cases of mapping the Exchange TWEXT: Determines the high period of
Memory onto the 5 physical memories (4 Retention BLE_WAKEUP_LP_IRQ, in the case of an external
RAMs and 1 SysRAM) in pages of 2 kB each. They wake up event (refer to
should be selected according to the application needs GP_CONTROL_REG[BLE_WAKEUP_REQ]). Mini-
regarding the amount of the Exchange Memory. So, for mum value is "TWIRQ_RESET + X", where X is the
example, Case 15 provides 40 kB of SysRAM and number of “ble_lp_clk” clock cycles that
10 kB of Exchange Memory (8 kB using the Retention BLE_WAKEUP_LP_IRQ will be held high. Recom-
and another 2 kB page of the SysRAM cell). Hence, mended value is "TWIRQ_RESET + 1". Note that as
exchange memory requirements can be met by pro- soon as GP_CONTROL_REG[BLE_WAKEUP_REQ]
gramming the respective case in the EM_MAP field of is set to “1” the BLE_WAKEUP_LP_IRQ will be
the GP_CONTROL_REG. asserted.
If the BLE core access an Exchange Memory area that Minimum BLE Sleep Duration: The minimum value of
is out of the boundaries specified by the BLE_DEEPSLWKUP_REG[DEEPSLTIME] time, mea-
GP_CONTROL_REG[EM_MAP], then EMAC- sured in “ble_lp_clk” cycles, is the maximum of (a)
CERRSTAT bit field is asserted, causing “TWIRQ_SET + 1” and (b) the SW execution time from
BLE_ERROR_IRQ to be raised. The Interrupt Service setting BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON]
Routine can detect the error condition by accessing the up to preparing CPU to accept the
EMACCERRSTAT and can acknowledge by writing a BLE_WAKEUP_LP_IRQ (e.g. to call the ARM instruc-
“1” to EMACCERRACK. BLE_ERROR_IRQ is raised tion WFI). If programmed DEEPSLTIME is less than
when either EMACCERRSTAT or ERRORINTSTAT are the aforementioned minimum value, then
asserted. BLE_WAKEUP_LP_IRQ Handler may execute sooner
than the call of ARM WFI instruction for example, caus-
24.2 PROGRAMMING BLE WAKE UP IRQ ing SW instability.
Once BLE core switches to “BLE Deep Sleep mode”
the only way to correctly exit from this state is by ini- 24.3 SWITCH FROM ACTIVE MODE TO DEEP
tially generating the BLE_WAKEUP_LP_IRQ and con- SLEEP MODE
secutively the BLE_SLP_IRQ. This sequence must be Software can set the BLE core into the “BLE Deep
followed regardless of the cause of the termination of Sleep mode”, by first programming the timing of
the “BLE Deep Sleep mode”, i.e. regardless if the BLE BLE_WAKEUP_LP_IRQ generation, then program the
Timer expired or BLE Timer has been stopped due to desired sleep duration at BLE_DEEPSLWKUP_REG
the assertion of BLE_WAKEUP_REQ. and finally set the register bit
BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON]. The
The assertion and de-assertion of BLE Core will switch to the “ble_lp_clk” (32.0 kHz or
BLE_WAKEUP_LP_IRQ is fully controlled via the 32.768 kHz) in order to maintain its internal 625 s tim-
BLE_ENBPRESET_REG bit fields. Detailed descrip- ing reference. Software must poll the state of
tion is following: BLE_CNTL2_REG[RADIO_PWRDN_ALLOW] to
TWIRQ_SET: Number of “ble_lp_clk” cycles before the detect the completion of this mode transition. Once the
expiration of the BLE Timer, when the “ble_lp_clk” is used for base time reference, SW must
BLE_WAKEUP_LP_IRQ must be asserted. It is recom- disable the BLE clocks (“ble_master1_clk”,
mended to select a TWIRQ_SET value larger than the “ble_master2_clk” and “ble_crypt_clk”) by setting to “0”
time required for the XTAL16_TRIM_READY_DELAY the CLK_RADIO_REG[BLE_ENABLE] register bit.
event, plus the IRQ Handler execution time. If the pro- Finally, SW can optionally power down the Radio Sub-
grammed value of TWIRQ_SET is less than the mini- system by using the
mum recommended value, then the system will wake PMU_CTRL_REG[RADIO_SLEEP] and the Peripheral
up but the actual BLE sleep duration (refer to and System power domains as well.
BLE_DEEPSLSTAT_REG) will be larger than the pro- Figure 62 presents the waveforms while entering in
grammed sleep duration (refer to BLE Deep Sleep mode. In this case, SW, as soon as it
BLE_DEEPSLWKUP_REG). detects that RADIO_PWRDOWN_ALLOW is “1”, it sets
TWIRQ_RESET: Number of “ble_lp_clk” cycles before the PMU_CTRL_REG[RADIO_SLEEP] to power down
the expiration of the sleep period, when the the Radio Subsystem. At the following figures, the cor-
BLE_WAKEUP_LP_IRQ will be de-asserted. It is rec- responding BLE Core signals are marked with red
ommended to always set to “1”. while Radio Subsystem is in power down state.

DA14580
ble_lp_clk
ble_master1_gclken
ble_master1_clk
tick_625us_p
deepsltime[31:0] (hld) 0 N
deep_sleep_on
radio_pwrdown_allow
deepsldur[31:0] 0 1 2 3
Figure 62 Entering into BLE Deep Sleep Mode
24.4 SWITCH FROM DEEP SLEEP MODE TO Once the SW decides that BLE Core can wake up, it
ACTIVE MODE must enable the BLE clocks (via
There are two possibilities for BLE Core to terminate CLK_RADIO_REG[BLE_ENABLE]) and power up the
the BLE Deep Sleep mode: Radio Power Domain (refer to
PMU_CTRL_REG[RADIO_SLEEP] and
1. Termination at the end of a predetermined time. SYS_STAT_REG[RAD_IS_UP]).
2. Termination on software wake-up request, due to an After the expiration of the sleep period (as specified in
external event. BLE_DEEPSLWKUP_REG[DEEPSLTIME]) the BLE
Timer will not exit the BLE Deep Sleep mode until it will
24.4.1 Switching at Anchor Points detect that BLE Core is powered up. That means that if
Figure 65 shows a typical deep sleep phase that is ter- the SW requires more time to power up the BLE Core,
minated at predetermined time. After a configurable then the final sleep duration (provided by
time before the scheduled wake up time (configured BLE_DEEPSLSTAT_REG) will be larger than the pre-
via BLE_ENBPRESET_REG register bit fields), the programmed value.
BLE Timer asserts the BLE_WAKEUP_LP_IRQ in When BLE Timer is expired, BLE clocks are enabled
order to wake-up the CPU (powering up the System and BLE Core (Radio Subsystem) is powered up, the
Power Domain). The BLE_WAKEUP_LP_IRQ Interrupt BLE Core exists the “BLE Core Deep Sleep mode” and
Handler will prepare the code environment and the asserts the BLE_SLP_IRQ.
XTAL16M oscillator stabilization (refer to
SYS_STAT_REG[XTAL16_SETTLED]) and will decide
when the BLE Core will be ready to exit from the BLE
Deep Sleep mode.
twirq_reset=1
ble_wakeup_lp_irq
ble_slp_irq
xtal16_settled
ble_enable
rad_is_up
ble_lp_clk
ble_master1_gclken
ble_master1_clk
deepsltime[31:0] (hld) N 0
deepsldur[31:0] N
finecnt[9:0]
clk_status
Figure 63 Exit BLE Deep Sleep Mode at Predetermined Time (Zoom In)

DA14580
twirq_reset=1
ble_wakeup_lp_irq
ble_slp_irq
xtal16_settled
ble_enable
rad_is_up
ble_lp_clk
ble_master1_gclken
ble_master1_clk
deepsldur[31:0] N N+5
finecnt[9:0]
clk_status
Figure 64 Exit BLE Deep Sleep Mode Later Than the Predetermined Time (Zoom In)
(N ‐ twirq_set)
ble_wakeup_lp_irq
ble_slp_irq
sys_state down mirror powerup
xtal16_settled
ble_enable
rad_is_up
ble_master1_gclken
ble_master1_clk
deepsldur[31:0] N
finecnt[9:0]
tick_625us_p
Figure 65 Exit BLE Deep Sleep Mode at Predetermined Time (Zoom Out)

DA14580
24.4.2 Switching Due to an External Event “1” the GP_CONTROL_REG[BLE_WAKEUP_REQ] in

order to force the wake up sequence.
Figure 66 shows a wake up from a deep sleep period
forced by the assertion of register bit In Figure 66 the BLE_WAKEUP_REQ is raised by the
GP_CONTROL_REG[BLE_WAKEUP_REQ]. software as soon as possible, causing
BLE_WAKEUP_LP_IRQ Handler to be executed as
Assume that the system is in Deep Sleep state, i.e. all
soon as possible. It is also possible to raise
Power Domains have been switched off, and both the
BLE_WAKEUP_REQ after the detection of
Wake-up Timer and Wake-up Controller have been
XTAL16_TRIM_READY, causing both
programmed appropriately. Then assume that an event
BLE_WAKEUP_LP_IRQ and BLE_SLP_IRQ Handlers
is detected at one of the GPIOs, causing the System
to execute sequentially. The decision depends on the
Power Domain to wake-up due to
software structure and the application.
WKUP_QUADDEC_IRQ. In that case, the SW will
decide to wake-up the BLE core, then it should set to
twext=1
sys_state down mirror powerup
wakeup_irq
ble_wakeup_req
xtal16_settled
rad_is_up
ble_wakeup_lp_irq
ble_slp_irq
deepsldur[31:0] K<N
finecnt[9:0]
tick_625us_p
Figure 66 Exit BLE Deep Sleep Mode Due to External Event
As soon as bit field BLE_WAKEUP_REQ is set to “1”

the BLE_WAKEUP_LP_IRQ will be asserted. In that
case, the high period of BLE_WAKEUP_LP_IRQ is
controlled via TWEXT. The recommended value of
TWEXT is "TWIRQ_RESET + 1", meaning that
BLE_WAKEUP_LP_IRQ will remain high for one
“ble_llp_clk” period.
As long as the BLE_WAKEUP_REQ is high, entering
the sleep mode is prohibited. Please note that
BLE_WAKEUP_REQ event can be disabled by setting
BLE_DEEPSLCNTL_REG[EXTWKUPDSB].

DA14580
25 Radio
The Radio Transceiver implements the RF part of the Features
Bluetooth low energy protocol. Together with the Blue- • Single ended RFIO interface, 50  matched
tooth 4.2 PHY layer, this provides a 93 dB RF link bud-
get for reliable wireless communication. • Alignment free operation
All RF blocks are supplied by on-chip low-drop out-reg- • -93 dBm receiver sensitivity
ulators (LDOs). The bias scheme is programmable per • 0 dBm transmit output power
block and optimized for minimum power consumption.
• Ultra low power consumption
The Bluetooth LE radio block diagram is given in
Figure 67. It comprises the Receiver, Transmitter, Syn- • Fast frequency tuning minimizes overhead
thesizer, Rx/Tx combiner block, and Biasing LDOs.
IFout
LNA
LNA MIX
MIX IF
IF ADC
ADC DEM
Rx
RFIO /
Tx SYNTH
Bias
LDO TESTMUX TEST[1:0]
PA /N
RFPA
SYNTH_CTRL RFCU
Figure 67: Bluetooth Radio Block Diagram
25.1 RECEIVER 25.3 TRANSMITTER

The RX frontend consists of a selective matching net- The RF power amplifier (RFPA) is an extremely effi-
work, a low noise amplifier (LNA) and an image rejec- cient Class-D structure, providing typically 0 dBm to the
tion down conversion mixer. The LNA gain is controlled antenna. It is fed by the VCO’s divide-by-2 circuit and
by the AGC. delivers its TX power to the antenna pin through the
combined RX/TX matching circuit.
The intermediate frequency (IF) part of the receiver
comprises a complex filter and 2 variable gain amplifi- 25.4 RFIO
ers. This provides the necessary signal conditioning
prior to digitalization. The digital demodulator block The RX/TX combiner block is a unique feature of the
(DEM) provides a synchronous bit stream. DA14580. It makes sure that the received power is
applied to the LNA with minimum losses towards the
25.2 SYNTHESIZER RFPA. In TX mode, the LNA poses a minimal load for
the RFPA and its input pins are protected from the
The RF Synthesizer generates the quadrature LO sig-
RFPA. In both modes, the single ended RFIO port is
nal for the mixer, but also generates the modulated TX
matched to 50 , in order to provide the simplest possi-
output signal. The VCO runs at twice the required fre-
ble interfacing to the antenna on the printed circuit
quency and a dedicated divide-by-2 circuit generates
board.
the 2.4 GHz signals in the required phase relations. Its
frequency is controlled by a classic 3rd order type II 25.5 BIASING
PLL with a passive loop filter, operated in fractional-N
mode. The reference frequency is the 16 MHz crystal All RF blocks are supplied by on-chip low-drop out-reg-
clock. The multi-modulus divider has a nominal divide ulators (LDOs). The bias scheme is programmable per
ratio of 153 which is varied by a  modulator. The block and optimized for minimum power consumption.
modulation of the TX frequency is performed by 2-point
25.6 CONTROL
modulation. The fractional divide ratio also contains the
shaped TX data stream. A second modulation path The radio control unit (RFCU) controls the block timing
feeds the TX data stream directly to the VCO. The lat- and configuration registers. The BLE interfaces directly
ter path is automatically calibrated from time to time to with the RFCU. The DA14580 can be put in test mode
align the low and high frequency parts of the 2-point using a standard Bluetooth tester (e.g.
modulation scheme. Rohde & Schwarz CBT with K57 option) by connecting
the antenna terminal for the RF link and the UART as
described in section 14.7.

DA14580
26 Registers
This section contains a detailed view of the DA14580 registers. It is organized as follows: An overview table is pre-
sented initially, which depicts all register names, addresses and descriptions. A detailed bit level description of each
register follows.
The register file of the ARM Cortex-M0 can be found in the following documents, available on the ARM website:
Devices Generic User Guide:
DUI0497A_cortex_m0_r0p0_generic_ug.pdf
Technical Reference Manual:
DDI0432C_cortex_m0_r0p0_trm.pdf
These documents contain the register descriptions for the Nested Vectored Interrupt Controller (NVIC), the System
Control Block (SCB) and the System Timer (SysTick).

DA14580
Table 26: Register Map
Address Port Description

0x40000000 BLE_RWBTLECNTL_REG BLE Control register
0x40000004 BLE_VERSION_REG Version register
0x40000008 BLE_RWBTLECONF_REG Configuration register
0x4000000C BLE_INTCNTL_REG Interrupt controller register
0x40000010 BLE_INTSTAT_REG Interrupt status register
0x40000014 BLE_INTRAWSTAT_REG Interrupt raw status register
0x40000018 BLE_INTACK_REG Interrupt acknowledge register
0x4000001C BLE_BASETIMECNT_REG Base time reference counter
0x40000020 BLE_FINETIMECNT_REG Fine time reference counter
0x40000024 BLE_BDADDRL_REG BLE device address LSB register
0x40000028 BLE_BDADDRU_REG BLE device address MSB register
0x4000002C BLE_CURRENTRXDESCPTR_REG Rx Descriptor Pointer for the Receive Buffer Chained
List
0x40000030 BLE_DEEPSLCNTL_REG Deep-Sleep control register
0x40000034 BLE_DEEPSLWKUP_REG Time (measured in Low Power clock cycles) in Deep
Sleep Mode before waking-up the device
0x40000038 BLE_DEEPSLSTAT_REG Duration of the last deep sleep phase register
0x4000003C BLE_ENBPRESET_REG Time in low power oscillator cycles register
0x40000040 BLE_FINECNTCORR_REG Phase correction value register
0x40000044 BLE_BASETIMECNTCORR_REG Base Time Counter
0x40000050 BLE_DIAGCNTL_REG Diagnostics Register
0x40000054 BLE_DIAGSTAT_REG Debug use only
0x40000058 BLE_DEBUGADDMAX_REG Upper limit for the memory zone
0x4000005C BLE_DEBUGADDMIN_REG Lower limit for the memory zone
0x40000060 BLE_ERRORTYPESTAT_REG Error Type Status registers
0x40000064 BLE_SWPROFILING_REG Software Profiling register
0x40000070 BLE_RADIOCNTL0_REG Radio interface control register
0x40000074 BLE_RADIOCNTL1_REG Radio interface control register
0x40000080 BLE_RADIOPWRUPDN_REG RX/TX power up/down phase register
0x40000090 BLE_ADVCHMAP_REG Advertising Channel Map
0x400000A0 BLE_ADVTIM_REG Advertising Packet Interval
0x400000A4 BLE_ACTSCANSTAT_REG Active scan register
0x400000B0 BLE_WLPUBADDPTR_REG Start address of public devices list
0x400000B4 BLE_WLPRIVADDPTR_REG Start address of private devices list
0x400000B8 BLE_WLNBDEV_REG Devices in white list
0x400000C0 BLE_AESCNTL_REG Start AES register
0x400000C4 BLE_AESKEY31_0_REG AES encryption key
0x400000C8 BLE_AESKEY63_32_REG AES encryption key
0x400000CC BLE_AESKEY95_64_REG AES encryption key
0x400000D0 BLE_AESKEY127_96_REG AES encryption key
0x400000D4 BLE_AESPTR_REG Pointer to the block to encrypt/decrypt
0x400000D8 BLE_TXMICVAL_REG AES / CCM plain MIC value
0x400000DC BLE_RXMICVAL_REG AES / CCM plain MIC value
0x400000E0 BLE_RFTESTCNTL_REG RF Testing Register

DA14580

0x400000F0 BLE_TIMGENCNTL_REG Timing Generator Register
0x400000F4 BLE_GROSSTIMTGT_REG Gross Timer Target value
0x400000F8 BLE_FINETIMTGT_REG Fine Timer Target value
0x400000FC BLE_SAMPLECLK_REG Samples the Base Time Counter
0x40000200 BLE_CNTL2_REG BLE Control Register 2
0x40000204 BLE_RF_DIAGIRQ_REG BLE/RF Diagnostic IRQ Control Register
0x40008000 OTPC_MODE_REG Mode register
0x40008004 OTPC_PCTRL_REG Bit-programming control register
0x40008008 OTPC_STAT_REG Status register
0x4000800C OTPC_AHBADR_REG AHB master start address
0x40008010 OTPC_CELADR_REG Macrocell start address
0x40008014 OTPC_NWORDS_REG Number of words
0x40008018 OTPC_FFPRT_REG Ports access to fifo logic
0x4000801C OTPC_FFRD_REG Latest read data from the OTPC_FFPRT_REG
0x50000000 CLK_AMBA_REG HCLK, PCLK, divider and clock gates
0x50000002 CLK_FREQ_TRIM_REG Xtal frequency trimming register
0x50000004 CLK_PER_REG Peripheral divider register
0x50000008 CLK_RADIO_REG Radio PLL control register
0x5000000A CLK_CTRL_REG Clock control register
0x50000010 PMU_CTRL_REG Power Management Unit control register
0x50000012 SYS_CTRL_REG System Control register
0x50000014 SYS_STAT_REG System status register
0x50000016 TRIM_CTRL_REG Control trimming of the XTAL16M
0x50000020 CLK_32K_REG 32 kHz oscillator register
0x50000022 CLK_16M_REG 16 MHz RC-oscillator register
0x50000024 CLK_RCX20K_REG 20 kHz RXC-oscillator control register
0x50000028 BANDGAP_REG Bandgap trimming
0x5000002A ANA_STATUS_REG Status bit of analog (power management) circuits
0x50000100 WKUP_CTRL_REG Control register for the wakeup counter
0x50000102 WKUP_COMPARE_REG Number of events before wakeup interrupt
0x50000104 WKUP_RESET_IRQ_REG Reset wakeup interrupt
0x50000106 WKUP_COUNTER_REG Actual number of events of the wakeup counter
0x50000108 WKUP_RESET_CNTR_REG Reset the event counter
0x5000010A WKUP_SELECT_P0_REG Select which inputs from P0 port can trigger wkup
counter
0x5000010C WKUP_SELECT_P1_REG Select which inputs from P1 port can trigger wkup
counter
0x5000010E WKUP_SELECT_P2_REG Select which inputs from P2 port can trigger wkup
counter
0x50000110 WKUP_SELECT_P3_REG Select which inputs from P3 port can trigger wkup
counter
0x50000112 WKUP_POL_P0_REG Select the sensitivity polarity for each P0 input

DA14580

0x50000200 QDEC_CTRL_REG Quad Decoder control register
0x50000202 QDEC_XCNT_REG Counter value of the X Axis
0x50000204 QDEC_YCNT_REG Counter value of the Y Axis
0x50000206 QDEC_CLOCKDIV_REG Clock divider register
0x50000208 QDEC_CTRL2_REG Quad Decoder control register
0x5000020A QDEC_ZCNT_REG Z_counter
0x50001000 UART_RBR_THR_DLL_REG Receive Buffer Register
0x50001004 UART_IER_DLH_REG Interrupt Enable Register
0x50001008 UART_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register
0x5000100C UART_LCR_REG Line Control Register
0x50001010 UART_MCR_REG Modem Control Register
0x50001014 UART_LSR_REG Line Status Register
0x50001018 UART_MSR_REG Modem Status Register
0x5000101C UART_SCR_REG Scratchpad Register
0x50001020 UART_LPDLL_REG Low Power Divisor Latch Low
0x50001024 UART_LPDLH_REG Low Power Divisor Latch High
0x50001030 UART_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register
0x5000103C UART_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register
0x5000107C UART_USR_REG UART Status register.
0x50001080 UART_TFL_REG Transmit FIFO Level
0x50001084 UART_RFL_REG Receive FIFO Level.
0x50001088 UART_SRR_REG Software Reset Register.
0x5000108C UART_SRTS_REG Shadow Request to Send
0x50001090 UART_SBCR_REG Shadow Break Control Register
0x50001094 UART_SDMAM_REG Shadow DMA Mode
0x50001098 UART_SFE_REG Shadow FIFO Enable
0x5000109C UART_SRT_REG Shadow RCVR Trigger
0x500010A0 UART_STET_REG Shadow TX Empty Trigger
0x500010A4 UART_HTX_REG Halt TX
0x500010F4 UART_CPR_REG Component Parameter Register

DA14580

0x500010F8 UART_UCV_REG Component Version
0x500010FC UART_CTR_REG Component Type Register
0x50001100 UART2_RBR_THR_DLL_REG Receive Buffer Register
0x50001104 UART2_IER_DLH_REG Interrupt Enable Register
0x50001108 UART2_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register
0x5000110C UART2_LCR_REG Line Control Register
0x50001110 UART2_MCR_REG Modem Control Register
0x50001114 UART2_LSR_REG Line Status Register
0x50001118 UART2_MSR_REG Modem Status Register
0x5000111C UART2_SCR_REG Scratchpad Register
0x50001120 UART2_LPDLL_REG Low Power Divisor Latch Low
0x50001124 UART2_LPDLH_REG Low Power Divisor Latch High
0x50001130 UART2_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register
0x5000113C UART2_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register
0x5000117C UART2_USR_REG UART Status register.
0x50001180 UART2_TFL_REG Transmit FIFO Level
0x50001184 UART2_RFL_REG Receive FIFO Level.
0x50001188 UART2_SRR_REG Software Reset Register.
0x5000118C UART2_SRTS_REG Shadow Request to Send
0x50001190 UART2_SBCR_REG Shadow Break Control Register
0x50001194 UART2_SDMAM_REG Shadow DMA Mode
0x50001198 UART2_SFE_REG Shadow FIFO Enable
0x5000119C UART2_SRT_REG Shadow RCVR Trigger
0x500011A0 UART2_STET_REG Shadow TX Empty Trigger
0x500011A4 UART2_HTX_REG Halt TX
0x500011F4 UART2_CPR_REG Component Parameter Register
0x500011F8 UART2_UCV_REG Component Version
0x500011FC UART2_CTR_REG Component Type Register
0x50001200 SPI_CTRL_REG SPI control register 0
0x50001202 SPI_RX_TX_REG0 SPI RX/TX register0

DA14580

0x50001204 SPI_RX_TX_REG1 SPI RX/TX register1
0x50001206 SPI_CLEAR_INT_REG SPI clear interrupt register
0x50001208 SPI_CTRL_REG1 SPI control register 1
0x50001300 I2C_CON_REG I2C Control Register
0x50001304 I2C_TAR_REG I2C Target Address Register
0x50001308 I2C_SAR_REG I2C Slave Address Register
0x50001310 I2C_DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register
0x50001314 I2C_SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register
0x50001318 I2C_SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register
0x5000131C I2C_FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register
0x50001320 I2C_FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register
0x5000132C I2C_INTR_STAT_REG I2C Interrupt Status Register
0x50001330 I2C_INTR_MASK_REG I2C Interrupt Mask Register
0x50001334 I2C_RAW_INTR_STAT_REG I2C Raw Interrupt Status Register
0x50001338 I2C_RX_TL_REG I2C Receive FIFO Threshold Register
0x5000133C I2C_TX_TL_REG I2C Transmit FIFO Threshold Register
0x50001340 I2C_CLR_INTR_REG Clear Combined and Individual Interrupt Register
0x50001344 I2C_CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register
0x50001348 I2C_CLR_RX_OVER_REG Clear RX_OVER Interrupt Register
0x5000134C I2C_CLR_TX_OVER_REG Clear TX_OVER Interrupt Register
0x50001350 I2C_CLR_RD_REQ_REG Clear RD_REQ Interrupt Register
0x50001354 I2C_CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register
0x50001358 I2C_CLR_RX_DONE_REG Clear RX_DONE Interrupt Register
0x5000135C I2C_CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register
0x50001360 I2C_CLR_STOP_DET_REG Clear STOP_DET Interrupt Register
0x50001364 I2C_CLR_START_DET_REG Clear START_DET Interrupt Register
0x50001368 I2C_CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register
0x5000136C I2C_ENABLE_REG I2C Enable Register
0x50001370 I2C_STATUS_REG I2C Status Register
0x50001374 I2C_TXFLR_REG I2C Transmit FIFO Level Register
0x50001378 I2C_RXFLR_REG I2C Receive FIFO Level Register
0x5000137C I2C_SDA_HOLD_REG I2C SDA Hold Time Length Register
0x50001380 I2C_TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register
0x50001394 I2C_SDA_SETUP_REG I2C SDA Setup Register
0x50001398 I2C_ACK_GENERAL_CALL_REG I2C ACK General Call Register
0x5000139C I2C_ENABLE_STATUS_REG I2C Enable Status Register
0x500013A0 I2C_IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size
0x50001400 GPIO_IRQ0_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ0
0x5000140C GPIO_DEBOUNCE_REG debounce counter value for GPIO inputs
0x5000140E GPIO_RESET_IRQ_REG GPIO interrupt reset register

DA14580

0x50001410 GPIO_INT_LEVEL_CTRL_REG high or low level select for GPIO interrupts
0x50001412 KBRD_IRQ_IN_SEL0_REG GPIO interrupt selection for KBRD_IRQ for P0
0x50001414 KBRD_IRQ_IN_SEL1_REG GPIO interrupt selection for KBRD_IRQ for P1 and P2
0x50001416 KBRD_IRQ_IN_SEL2_REG GPIO interrupt selection for KBRD_IRQ for P3
0x50001500 GP_ADC_CTRL_REG General Purpose ADC Control Register
0x50001502 GP_ADC_CTRL2_REG General Purpose ADC Second Control Register
0x50001504 GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register
0x50001506 GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register
0x50001508 GP_ADC_CLEAR_INT_REG General Purpose ADC Clear Interrupt Register
0x5000150A GP_ADC_RESULT_REG General Purpose ADC Result Register
0x5000150C GP_ADC_DELAY_REG General Purpose ADC Delay Register
0x5000150E GP_ADC_DELAY2_REG General Purpose ADC Second Delay Register
0x50001600 CLK_REF_SEL_REG Select clock for oscillator calibration
0x50001602 CLK_REF_CNT_REG Count value for oscillator calibration
0x50001604 CLK_REF_VAL_L_REG XTAL16M reference cycles, lower 16 bits
0x50001606 CLK_REF_VAL_H_REG XTAL16M reference cycles, upper 16 bits
0x50003000 P0_DATA_REG P0 Data input / output register
0x50003002 P0_SET_DATA_REG P0 Set port pins register
0x50003004 P0_RESET_DATA_REG P0 Reset port pins register
0x50003006 P00_MODE_REG P00 Mode Register
0x5000300A P02_MODE_REG P02 Mode Register
0x5000300C P03_MODE_REG P03 Mode Register
0x5000300E P04_MODE_REG P04 Mode Register

DA14580

0x50003070 P01_PADPWR_CTRL_REG Ports 0 and 1 Output Power Control Register
0x50003072 P2_PADPWR_CTRL_REG Port 2 Output Power Control Register
0x50003074 P3_PADPWR_CTRL_REG Port 3 Output Power Control Register
0x50003100 WATCHDOG_REG Watchdog timer register.
0x50003102 WATCHDOG_CTRL_REG Watchdog control register.
0x50003200 CHIP_ID1_REG Chip identification register 1.
0x50003203 CHIP_SWC_REG Software compatibility register.
0x50003204 CHIP_REVISION_REG Chip revision register.
0x50003300 SET_FREEZE_REG Controls freezing of various timers/counters.
0x50003302 RESET_FREEZE_REG Controls unfreezing of various timers/counters.
0x50003304 DEBUG_REG Various debug information register.
0x50003306 GP_STATUS_REG General purpose system status register.
0x50003308 GP_CONTROL_REG General purpose system control register.
0x50003400 TIMER0_CTRL_REG Timer0 control register
0x50003402 TIMER0_ON_REG Timer0 on control register
0x50003404 TIMER0_RELOAD_M_REG 16 bits reload value for Timer0
0x50003406 TIMER0_RELOAD_N_REG 16 bits reload value for Timer0
0x50003408 PWM2_DUTY_CYCLE Duty Cycle for PWM2
0x5000340A PWM3_DUTY_CYCLE Duty Cycle for PWM3
0x5000340C PWM4_DUTY_CYCLE Duty Cycle for PWM4
0x5000340E TRIPLE_PWM_FREQUENCY Frequency for PWM 2,3 and 4
0x50003410 TRIPLE_PWM_CTRL_REG PWM 2 3 4 Control

DA14580
Table 27: BLE_RWBTLECNTL_REG (0x40000000)
Bit Mode Symbol Description Reset

31 R/W MASTER_SOFT_RS Reset the complete system except registers and timing gen- 0x0
T erator, when written with a 1. Resets at 0 when action is per-
formed. No action happens if it is written with 0.
30 R/W MASTER_TGSOFT_ Reset the timing generator, when written with a 1. Resets at 0x0
RST 0 when action is performed. No action happens if it is written
with 0.
29 R/W REG_SOFT_RST Reset the complete register block, when written with a 1. 0x0
Resets at 0 when action is performed. No action happens if it
is written with 0.
28:27 - - Reserved 0x0
26 R/W RFTEST_ABORT Abort the current RF Testing defined as per CS-FORMAT 0x0
when written with a 1. Resets at 0 when action is performed.
No action happens if it is written with 0.
Note that when RFTEST_ABORT is requested.
1) In case of infinite Tx, the Packet Controller FSM stops at
the end of the current byte in process, and processes
accordingly the packet CRC.
2) In case of Infinite Rx, the Packet Controller FSM either
stops as the end of the current Packet reception (if Access
address has been detected), or simply stop the processing
switching off the RF.
25 R/W ADVERT_ABORT Abort the current Advertising event when written with a 1. 0x0
Resets at 0 when action is performed. No action happens if it
is written with 0.
24 R/W SCAN_ABORT Abort the current scan window when written with a 1. Resets 0x0
at 0 when action is performed. No action happens if it is writ-
ten with 0.
23 - - Reserved 0x0
22 R/W MD_DSB 0: Normal operation of MD bits management 0x0
1: Allow a single Tx/Rx exchange whatever the MD bits are
21 R/W SN_DSB 0: Normal operation of Sequence number 0x0
1: Sequence Number Management disabled:
value forced by SW from Tx Descriptor
value ignored in Rx, meaning that no SN error reported.
20 R/W NESN_DSB 0: Normal operation of Sequence number 0x0
1: Sequence Number Management disabled:
value forced by SW from Tx Descriptor
value ignored in Rx, meaning that no SN error reported.
19 R/W CRYPT_DSB 0: Normal operation. Encryption / Decryption enabled. 0x0
1: Encryption / Decryption disabled.
Note that if CS-CRYPT_EN is set, then MIC is generated,
and only data encryption is disabled, meaning data sent are
plain data.
18 R/W WHIT_DSB 0: Normal operation. Whitening enabled. 0x0
1: Whitening disabled.
17 R/W CRC_DSB 0: Normal operation. CRC removed from data stream. 0x0
1: CRC stripping disabled on Rx packets, CRC replaced by
0x000 in Tx
16 R/W HOP_REMAP_DSB 0: Normal operation. Frequency Hopping Remapping algo- 0x0
rithm enabled.
1: Frequency Hopping Remapping algorithm disabled

DA14580
Table 27: BLE_RWBTLECNTL_REG (0x40000000)

12 R/W TXWINOFFSEL Applicable only if device is in Initiator mode 0x0
0: Window Offset field in CONNECT_REQ comes from Tx
Data Buffer
1: Window Offset field in CONNECT_REQ comes from
Event Controller processing and is replaced in real time by
Packet Controller
11 R/W RXDESCPTRSEL 0: Selects Rx Descriptor Pointer value from Control Structure 0x0
1: Selects Rx Descriptor Pointer value from CURRENTRX-
DESCPTR register
10 R/W ADVERRFILT_EN Advertising Channels Error Filtering Enable control 0x0
0: BLE Core reports all errors to BLE Software
1: BLE Core reports only correctly received packet, without
error to BLE Software
9 R/W WLSYNC_EN 0: WLAN synchronization pulse generation disabled 0x0
1: WLAN synchronization pulse generation enabled
8 R/W RWBLE_EN 0: Disable BLE Core Exchange Table pre-fetch mechanism. 0x0
1: Enable BLE Core Exchange table pre-fetch mechanism.
7:4 R/W RXWINSZDEF Default Rx Window size in us. Used when device 0x0
a) is master connected
b) performs its second receipt.
0 is not a valid value. Recommended value is 10.
3 - - Reserved 0x0
2:0 R/W SYNCERR Indicates the maximum number of errors allowed to recog- 0x0
nize the synchronization word.
Table 28: BLE_VERSION_REG (0x40000004)

31:24 R TYP BLE Core Type - 0x6 means BT4.0 (i.e correspond LL ver- 0x0
sion assigned number)
23:16 R REL BLE Core version - Major release number.(Correspond to FS 0x0
v1.11)
15:8 R UPG BLE Core upgrade - Upgrade number. (Correspond to FS 0x0
v1.11)
7:0 R BUILD BLE Core Build - Build number 0x0
Table 29: BLE_RWBTLECONF_REG (0x40000008)

29:24 R ADD_WIDTH Value of the BLE_ADDRESS_WIDTH parameter converted 0xE
into binary.
23 - - Reserved 0x0
22:16 R RFIF Supported radio interfaces. 0x8
0001000: on-chip radio
others: reserved
13:8 R CLK_SEL Operating Frequency (in MHz). 0x0
This field is a copy of the
BLE_CNTL2_REG[BLE_CLK_SEL] value.

DA14580
Table 29: BLE_RWBTLECONF_REG (0x40000008)

5 R DMMODE 0: BLE Core is used as a standalone BLE device 0x0
1: BLE Core is used in a Dual Mode device
4 R INTMODE 0: Interrupts are edge level generated, i.e pulse. 0x1
1: Interrupts are trigger level generated, i.e stays active at 1
till acknowledgement
3 R WLAN 0: WLAN Coexistence mechanism not present 0x0
1: WLAN Coexistence mechanism present
2 R USEDBG 0: Diagnostic port not instantiated 0x1
1: Diagnostic port instantiated
1 R USECRYPT 0: Encryption block not present 0x1
1: Encryption block present
0 R BUSWIDTH Processor bus width: 0x1
0: 16 bits
1: 32 bits
Table 30: BLE_INTCNTL_REG (0x4000000C)

31:16 R/W INTCSCNTL Selection of the CS counter that generates an interrupt. For 0xFF
example, if INTCNTL[3] is set, an interrupt is sent each time
CS counter equals 3.
15 R/W CSCNTDEVMSK CSCNT interrupt mask during event. This bit allows to 0x1
enable CSCNT interrupt generation during events (i.e adver-
tising, scanning, initiating, and connection)
0: CSCNT Interrupt not generated during events.
1: CSCNT Interrupt generated during events.
8 R/W RADIOCNTLINTMSK Radio Controller interrupt mask 0x0
0: Interrupt not generated
1: Interrupt generated
7 R/W FINETGTIMINTMSK Fine Target Timer Mask 0x0
6 R/W GROSSTGTIMINT- Gross Target Timer Mask 0x0
MSK 0: Interrupt not generated
5 R/W ERRORINTMSK Error Interrupt Mask 0x0
4 R/W CRYPTINTMSK Encryption / Decryption Interrupt Mask 0x1
3 R/W EVENTINTMSK End of event Interrupt Mask 0x1
2 R/W SLPINTMSK Sleep Mode Interrupt Mask 0x1
1 R/W RXINTMSK Rx Interrupt Mask 0x1

DA14580
Table 30: BLE_INTCNTL_REG (0x4000000C)

0 R/W CSCNTINTMSK 625usec Base Time Interrupt Mask 0x1
Table 31: BLE_INTSTAT_REG (0x40000010)

8 R RADIOCNTLINT- Radio Controller interrupt status 0x0
STAT 0: No Gross Target Timer interrupt.
1: A Gross Target Timer interrupt is pending.
7 R FINETGTIMINTSTAT Masked Fine Target Timer Error interrupt status 0x0
0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.
6 R GROSSTGTIMINT- Masked Gross Target Timer interrupt status 0x0
STAT 0: No Gross Target Timer interrupt.
5 R ERRORINTSTAT Masked Error interrupt status 0x0
0: No Error interrupt.
1: An Error interrupt is pending.
4 R CRYPTINTSTAT Masked Encryption/Decryption interrupt status 0x0
0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.
3 R EVENTINTSTAT Masked End of Event interrupt status 0x0
0: No End of Advertising / Scanning / Connection interrupt.
1: An End of Advertising / Scanning / Connection interrupt is
pending.
2 R SLPINTSTAT Masked Sleep interrupt status 0x0
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.
1 R RXINTSTAT Masked Packet Reception interrupt status 0x0
0: No Rx interrupt.
1: An Rx interrupt is pending.
0 R CSCNTINTSTAT Masked 625us base time reference interrupt status 0x0
0: No 625us Base Time interrupt.
1: A 625us Base Time interrupt is pending.
Table 32: BLE_INTRAWSTAT_REG (0x40000014)

8 R RADIOCNTLIN- Radio Controller interrupt raw status 0x0
TRAWSTAT 0: No Gross Target Timer interrupt.
7 R FINETGTIMINTRAW- Fine Target Timer Error interrupt raw status 0x0
STAT 0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.
6 R GROSSTGTIMIN- Gross Target Timer interrupt raw status 0x0
TRAWSTAT 0: No Gross Target Timer interrupt.

DA14580
Table 32: BLE_INTRAWSTAT_REG (0x40000014)

5 R ERRORINTRAW- Error interrupt raw status 0x0
STAT 0: No Error interrupt.
1: An Error interrupt is pending.
4 R CRYPTINTRAWSTAT Encryption/Decryption interrupt raw status 0x0
0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.
3 R EVENTINTRAWSTAT End of Event interrupt raw status 0x0
0: No End of Advertising / Scanning / Connection interrupt.
1: An End of Advertising / Scanning / Connection interrupt is
pending.
2 R SLPINTRAWSTAT Sleep interrupt raw status 0x0
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.
1 R RXINTRAWSTAT Packet Reception interrupt raw status 0x0
0: No Rx interrupt.
1: An Rx interrupt is pending.
0 R CSCNTINTRAW- 625us base time reference interrupt raw status 0x0
STAT 0: No 625us Base Time interrupt.
1: A 625us Base Time interrupt is pending.
Table 33: BLE_INTACK_REG (0x40000018)

8 W RADIOCNTLINTACK Radio Controller interrupt acknowledgement bit 0x0
Software writing 1 acknowledges the Error interrupt. This bit
resets RADIOCNTLINTSTAT and RADIOCNTLINTRAW-
STAT flags.
7 W FINETGTIMINTACK Fine Target Timer interrupt acknowledgement bit 0x0
resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT
flags.
6 W GROSSTGTIMIN- Gross Target Timer interrupt acknowledgement bit 0x0
TACK Software writing 1 acknowledges the Error interrupt. This bit
resets GROSSTGTIMINTSTAT and GROSSTGTIMIN-
TRAWSTAT flags.
5 W ERRORINTACK Error interrupt acknowledgement bit 0x0
resets ERRORINTSTAT and ERRORINTRAWSTAT flags.
4 W CRYPTINTACK Encryption/Decryption interrupt acknowledgement bit Soft- 0x0
ware writing 1 acknowledges the Encryption / Decryption
interrupt. This bit resets CRYPTINTSTAT and CRYPTIN-
TRAWSTAT flags.
3 W EVENTINTACK End of Event interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the End of Advertising /
Scanning / Connection interrupt. This bit resets SLPINT-
STAT and SLPINTRAWSTAT flags.
2 W SLPINTACK End of Deep Sleep interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the End of Sleep Mode
interrupt. This bit resets SLPINTSTAT and SLPINTRAW-
STAT flags.
1 W RXINTACK Packet Reception interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the Rx interrupt. This bit
resets RXINTSTAT and RXINTRAWSTAT flags.
DA14580
Table 33: BLE_INTACK_REG (0x40000018)

0 W CSCNTINTACK 625us base time reference interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the CLKN interrupt. This bit
resets CLKINTSTAT and CLKINTRAWSTAT flags.
Table 34: BLE_BASETIMECNT_REG (0x4000001C)

26:0 R BASETIMECNT Value of the 625us base time reference counter. Updated 0x0
each time BLE_SAMPLECLK_REG[SAMP] is written. Used
by the SW in order to synchronize with the HW.
Table 35: BLE_FINETIMECNT_REG (0x40000020)

9:0 R FINECNT Value of the current usec fine time reference counter. 0x0
Updated each usec. Used by the SW in order to synchronize
with the HW, and obtain a more precise sleep duration
Table 36: BLE_BDADDRL_REG (0x40000024)

31:0 R/W BDADDRL Bluetooth Low Energy Device Address. LSB part. 0x0
Table 37: BLE_BDADDRU_REG (0x40000028)

16 R/W PRIV_NPUB Bluetooth Low Energy Device Address privacy indicator 0x0
0: Public Bluetooth Device Address
1: Private Bluetooth Device Address
15:0 R/W BDADDRU Bluetooth Low Energy Device Address. MSB part. 0x0
Table 38: BLE_CURRENTRXDESCPTR_REG (0x4000002C)

13:0 R/W CURRENTRX- Rx Descriptor Pointer that determines the starting point of 0x0
DESCPTR the Receive Buffer Chained List.
Table 39: BLE_DEEPSLCNTL_REG (0x40000030)

31 R/W EXTWKUPDSB External Wake-Up disable 0x0
0: BLE Core can be woken by external wake-up
1: BLE Core cannot be woken up by external wake-up

DA14580
Table 39: BLE_DEEPSLCNTL_REG (0x40000030)

15 R DEEP_SLEEP_STAT Indicator of current Deep Sleep clock mux status: 0x0
0: BLE Core is not yet in Deep Sleep Mode
1: BLE Core is in Deep Sleep Mode (only Low Power Clock
is running)
4 R/W SOFT_WAKEUP_RE Wake Up Request from BLE Software. Applies when system 0x0
Q is in Deep Sleep Mode. It wakes up the BLE Core when writ-
ten with a 1. Always read as 0. No action happens if it is writ-
ten with 0.
3 R/W DEEP_SLEEP_COR 625us base time reference integer and fractional part correc- 0x0
R_EN tion. Applies when system has been woken-up from Deep
Sleep Mode. It enables Fine Counter and Base Time counter
when written with a 1. Always read as 0. No action happens
if it is written with 0.
2 R/W DEEP_SLEEP_ON 0: BLE Core in normal active mode 0x0
1: Request BLE Core to switch in deep sleep mode.
This bit is reset on DEEP_SLEEP_STAT falling edge.
1:0 R/W DEEP_SLEEP_IRQ_ Always set to "3" when DEEP_SLEEP_ON is set to "1". 0x0
EN It controls the generation of BLE_WAKEUP_LP_IRQ.
Table 40: BLE_DEEPSLWKUP_REG (0x40000034)

31:0 R/W DEEPSLTIME Determines the time in Low Power Clock cycles to spend in 0x0
Deep Sleep Mode before waking-up the device. This
ensures a maximum of 37 hours and 16mn sleep mode
capabilities at 32kHz. This ensures a maximum of 36 hours
and 16mn sleep mode capabilities at 32.768kHz. If DEEPSL-
TIME is set to zero, the Deep Sleep Time duration is consid-
ered as infinite, and only wake up requests can restore
active behavior
BLE Software must ensure DEEPSLTIME value to be
greater than 2 in order to cope with control resynchronization
requirements
Table 41: BLE_DEEPSLSTAT_REG (0x40000038)

31:0 R DEEPSLDUR Actual duration of the last deep sleep phase measured in 0x0
Low Power Clock cycles. DEEPSLDUR is set to zero at the
beginning of the deep sleep phase, and is incremented at
each Low Power Clock cycle until the end of the deep sleep
phase.
Table 42: BLE_ENBPRESET_REG (0x4000003C)

31:21 R/W TWEXT Minimum and recommended value is "TWIRQ_RESET + 1". 0x0
In the case of wake-up due to an external wake-up request,
TWEXT specifies the time delay in low power oscillator
cycles to deassert BLE_WAKEUP_LP_IRQ.
Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ].
Range is [0...64 ms] for 32kHz; [0...62.5 ms] for 32.768kHz

DA14580
Table 42: BLE_ENBPRESET_REG (0x4000003C)

20:10 R/W TWIRQ_SET Minimum value is "TWIRQ_RESET + 1". 0x0
Time in low power oscillator cycles to set
BLE_WAKEUP_LP_IRQ before the BLE sleep timer expira-
tion.
Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME].
Range is [0...64 ms] for 32kHz; [0...62.5 ms] for 32.768kHz
9:0 R/W TWIRQ_RESET Recommended value is 1. 0x0
Time in low power oscillator cycles to reset
BLE_WAKEUP_LP_IRQ before the BLE sleep timer expira-
tion.
Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME].
Range is [0...32 ms] for 32kHz; [0...31.25 ms] for 32.768kHz.
Table 43: BLE_FINECNTCORR_REG (0x40000040)

9:0 R/W FINECNTCORR Phase correction value for the 625usec reference counter 0x0
(i.e Fine Counter) in us.
Table 44: BLE_BASETIMECNTCORR_REG (0x40000044)

26:0 R/W BASETIMECNT- Base Time Counter correction value. 0x0
CORR
Table 45: BLE_DIAGCNTL_REG (0x40000050)

31 R/W DIAG3_EN 0: Disable diagnostic port 3 output. All outputs are set to 0. 0x0
1: Enable diagnostic port 3 output.
30 - - Reserved 0x0
29:24 R/W DIAG3 Only relevant when DIAG3_EN = 1. 0x0
Selection of the outputs that must be driven to the diagnostic
port 3.
22 - - Reserved 0x0
port 2.
14 - - Reserved 0x0
port 1.
6 - - Reserved 0x0

DA14580
Table 45: BLE_DIAGCNTL_REG (0x40000050)

port 0.
Table 46: BLE_DIAGSTAT_REG (0x40000054)

31:24 R DIAG3STAT Directly connected to ble_dbg3[7:0] output. Debug use only. 0x0
Table 47: BLE_DEBUGADDMAX_REG (0x40000058)

15:0 R/W ADDMAX Upper limit for the memory zone. 0x0
Table 48: BLE_DEBUGADDMIN_REG (0x4000005C)

15:0 R/W ADDMIN Lower limit for the memory zone. 0x0
Table 49: BLE_ERRORTYPESTAT_REG (0x40000060)

11 R CSFORMAT_ERRO Indicates whether CS-FORMAT has been programmed with 0x0
R an invalid value: this is a major software programming fail-
ure.
0: No error
1: Error occurred
10 R CSTXPTR_ERROR Indicates whether CS-TXPTR is null, this is a major software 0x0
programming failure.
0: No error
1: Error occurred
9 - - Reserved 0x0
8 R RADIO_EMACC_ER Radio Controller Exchange Memory access error, happens 0x0
ROR when Exchange Memory access are not served in time and
data are corrupted.
0: No error
1: Error occurred
7 R LLCHMAP_ERROR Link Layer Channel Map error, happens when actual number 0x0
of CS-LLCHMAP bit set to one is different from CS-NBCH-
GOOD at the beginning of Frequency Hopping process
0: No error
1: Error occurred

DA14580
Table 49: BLE_ERRORTYPESTAT_REG (0x40000060)

6 R IFS_UNDERRUN Inter Frame Space Under run, occurs if IFS time is not 0x0
enough to update and read Control Structure/Descriptors,
and/or White List parsing is not finished and/or Decryption
time is too long to be finished on time
0: No error
1: Error occurred
5 R RXCRYPT_ERROR Real Time Decryption Error, happens when decryption is not 0x0
finished before IFS time
0: No error
1: Error occurred
4 R WHITELIST_ERROR White List Timeout Error, occurs if White List parsing is not 0x0
finished on time
0: No error
1: Error occurred
3 R APFM_ERROR Anticipated Pre-Fetch Mechanism error, happens when 3 0x0
consecutive Exchange Table entry have been programmed,
0: no error
1: Error occured
2 R TXDESC_ERROR Tx Descriptor Error, happens when fetched Tx Descriptor 0x0
has TXDONE bit not set
0: No error
1: Error occurred
1 R PKTCNTL_EMACC_ Packet Controller Exchange Memory access error, happens 0x0
ERROR when Exchange Memory access are not served in time and
Tx/Rx data are corrupted
0: No error
1: Error occurred
0 R TXCRYPT_ERROR Real Time Encryption Error, happens when encryption is not 0x0
finished before Tx Payload has to be sent
0: No error
1: Error occurred
Table 50: BLE_SWPROFILING_REG (0x40000064)

31:0 R/W SWPROFVAL Software Profiling register: used by BLE Software for profil- 0x0
ing purpose: this value is copied on Diagnostic port
Table 51: BLE_RADIOCNTL0_REG (0x40000070)

22 R/W DPCORR_EN Enable the use of delayed DC compensated data path in 0x0
Radio Correlator block
1: Enable
0: Disable
Must be set to "0".
21:0 - - Reserved 0x2102


DA14580

20:16 R/W XRFSEL Extended radio selection field, Must be set to '00011'. 0x0
Table 53: BLE_RADIOPWRUPDN_REG (0x40000080)

31 - - Reserved 0x0
30:24 R/W RTRIP_DELAY Defines round trip delay value. This value correspond to the 0x0
addition of data latency in Tx and data latency in Rx. Value is
in us.
23:16 R/W RXPWRUP This register holds the length in us of the Rx power up phase 0xD2
for the current radio device. Default value is 210 us (reset
value). Operating range depends of the selected radio.
11:8 R/W TXPWRDN This register extends the length in us of the Tx power down 0x3
phase for the current radio device. Default value is 3us (reset
7:0 R/W TXPWRUP This register holds the length in us of the Tx power up phase 0xD2
for the current radio device. Default value is 210 us (reset
Table 54: BLE_ADVCHMAP_REG (0x40000090)

2:0 R/W ADVCHMAP Advertising Channel Map, defined as per the advertising 0x7
connection settings. Contains advertising channels index 37
to 39. If ADVCHMAP[i] equals:
0: Do not use data channel i+37.
1: Use data channel i+37.
Table 55: BLE_ADVTIM_REG (0x400000A0)

13:0 R/W ADVINT Advertising Packet Interval defines the time interval in 0x0
between two ADV_xxx packet sent.
Value is in usec.
Value to program depends of the used Advertising Packet
type and the device filtering policy. Please refer to Table 3-10
for details about ADVINT programming range.
Table 56: BLE_ACTSCANSTAT_REG (0x400000A4)

24:16 R/W BACKOFF Active scan mode back-off counter initialization value. 0x0
8:0 R/W UPPERLIMIT Active scan mode upper limit counter value. 0x0

DA14580
Table 57: BLE_WLPUBADDPTR_REG (0x400000B0)

15:0 R/W WLPUBADDPTR Start address pointer of the public devices white list. 0x0
Table 58: BLE_WLPRIVADDPTR_REG (0x400000B4)

15:0 R/W WLPRIVADDPTR Start address pointer of the private devices white list. 0x0
Table 59: BLE_WLNBDEV_REG (0x400000B8)

15:8 R/W NBPRIVDEV Number of private devices in the white list. 0x0
7:0 R/W NBPUBDEV Number of public devices in the white list. 0x0
Table 60: BLE_AESCNTL_REG (0x400000C0)

0 R/W AES_START Writing a 1 starts AES-128 ciphering process. 0x0
This bit is reset once the process is finished (i.e
BLE_CRYPT_IRQ interrupt occurs, even masked)
Table 61: BLE_AESKEY31_0_REG (0x400000C4)

31:0 R/W AESKEY31_0 AES encryption 128-bit key. Bit 31 down to 0 0x0
Table 62: BLE_AESKEY63_32_REG (0x400000C8)

Table 63: BLE_AESKEY95_64_REG (0x400000CC)

Table 64: BLE_AESKEY127_96_REG (0x400000D0)

Table 65: BLE_AESPTR_REG (0x400000D4)


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Table 65: BLE_AESPTR_REG (0x400000D4)

15:0 R/W AESPTR Pointer to the memory zone where the block to encrypt/ 0x0
decrypt is stored.
Table 66: BLE_TXMICVAL_REG (0x400000D8)

31:0 R TXMICVAL AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ 0x0
interrupt (even masked)
Table 67: BLE_RXMICVAL_REG (0x400000DC)

31:0 R RXMICVAL AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ 0x0
interrupt (even masked)
Table 68: BLE_RFTESTCNTL_REG (0x400000E0)

31 R/W INFINITERX Applicable for all frame format 0x0
0: Normal mode of operation
1: Infinite Rx window
15 R/W INFINITETX Applicable for all frame format 0x0
0: Normal mode of operation.
1: Infinite Tx packet / Normal start of a packet but endless
payload
In case of infinite Tx payload, and when PRBS source is not
selected, then RFTESTCNTL-TXLENGTH field provides the
length of the pattern to repeat in the payload.
14 R/W TXLENGTHSRC Applicable only in Tx/Rx RF Test mode 0x0
0: Normal mode of operation: TXDESC-TXADVLEN controls
the Tx packet payload size
1: Uses RFTESTCNTL-TXLENGTH packet length (can sup-
port up to 512 bytes transmit)
13 R/W PRBSTYPE Applicable only in Tx/Rx RF Test mode 0x0
0: Tx Packet Payload are PRBS9 type
1: Tx Packet Payload are PRBS15 type
PRBS9 is defined as p(x)=1+x5+x9. The LFSR used for the
PRBS9 generator must be initialized with 0x1FF value.
PRBS15 is defined as p(x)=1+x+x2+x12+x13+x14. The
LFSR used for the PRBS15 generator must be initialized
with 0x7FFF value.
12 R/W TXPLDSRC Applicable only in Tx/Rx RF Test mode 0x0
0: Tx Packet Payload source is the Control Structure
1: Tx Packet Payload are PRBS generator
8:0 R/W TXLENGTH Applicable only in Tx/Rx RF Test mode 0x0
Tx packet length in number of byte

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Table 69: BLE_TIMGENCNTL_REG (0x400000F0)

7:0 R/W PREFTECH_TIME Defines Exchange Table pre-fetch instant in us 0x0
Table 70: BLE_GROSSTIMTGT_REG (0x400000F4)

15:0 R/W GROSSTARGET Gross Timer Target value on which a 0x0
BLE_GROSSTGTIM_IRQ must be generated. This timer
has a precision of 10ms: interrupt is generated only when
GROSSTARGET[15:0] = BASETIMECNT[19:4] and BASE-
TIMECNT[3:0] = 0.
Table 71: BLE_FINETIMTGT_REG (0x400000F8)

26:0 R/W FINETARGET Fine Timer Target value on which a BLE_FINETGTIM_IRQ 0x0
must be generated. This timer has a precision of 625us:
interrupt is generated only when FINETARGET = BASE-
TIMECNT
Table 72: BLE_SAMPLECLK_REG (0x400000FC)

0 R/W SAMP Writing a 1 samples the Base Time Counter value in BASE- 0x0
TIMECNT register. Resets at 0 when action is performed.
Table 73: BLE_CNTL2_REG (0x40000200)

21 R/W BLE_RSSI_SEL 0: Select Peak-hold RSSI value (default). 0x0
1: Select current Average RSSI value.
20 R WAKEUPLPSTAT The status of the BLE_WAKEUP_LP_IRQ. The Interrupt 0x0
Service Routine of BLE_WAKEUP_LP_IRQ should return
only when the WAKEUPLPSTAT is cleared.
Note that BLE_WAKEUP_LP_IRQ is automatically acknowl-
edged after the power up of the Radio Subsystem, plus one
Low Power Clock period.
19 R/W SW_RPL_SPI Keep to 0. 0x0
18 R/W BB_ONLY Keep to 0. 0x0
17 R/W RADIO_ONLY Keep to 0. 0x0

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14:9 R/W BLE_CLK_SEL BLE Clock Select. 0x0
Specifies the BLE master clock absolute frequency in MHz.
Typical values are 16 and 8.
Value depends on the selected XTAL frequency and the
value of CLK_RADIO_REG[BLE_DIV] bitfield. For example,
if XTAL oscillates at 16MHz and
CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE
master clock frequency is 8MHz and BLE_CLK_SEL should
be set to value 8.
The selected BLE master clock frequency (affected by
BLE_DIV and BLE_CLK_SEL) must be modified and set
only during the initialization time, i.e. before setting
BLE_RWBTLECNTL_REG[RWBLE_EN] to 1.
Refer also to BLE_RWBTLECONF_REG[CLK_SEL].
8 R RADIO_PWRDN_AL This active high signal indicates when it is allowed for the 0x0
LOW BLE core (embedded in the Radio sub-System power
domain) to be powered down.
After the assertion of the
BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware
sequence based on the Low Power clock will cause the
assertion of RADIO_PWRDN_ALLOW. The
RADIO_PWRDN_ALLOW will be cleared to "0" when the
BLE core exits from the sleep state, i.e. when the
BLE_SLP_IRQ will be asserted.
7 R/W MON_LP_CLK The SW can only write a "0" to this bit. 0x0
Whenever a positive edge of the low power clock used by
the BLE Timers is detected, then the HW will automatically
set this bit to "1". This functionality will not work if BLE Timer
is in reset state (refer to
CLK_RADIO_REG[BLE_LP_RESET]).
This bit can be used for SW synchronization, to debug the
low power clock, etc.
6 R BLE_CLK_STAT 0: BLE uses low power clock 0x0
1: BLE uses master clock
5 R/W DIAGPORT_REVER BLE/RADIO Diagnostic Port Reverse order. 0
SE
When this bit is "1", the mapping of the diagnostic bus DIAG-
PORT[7:0] (controlled by DIAGPORT_SEL) to GPIOs (con-
trolled by Pxy_MODE_REG[PID]) is reversed. The mapping
is:
If "0" then DIAGPORT[7] is mapped to P0[7], etc.

DIAGPORT[4] is mapped to P0[4],
DIAGPORT[3] is mapped to P0[3] and P1[3], etc. and
DIAGPORT[0] is mapped to P0[0] and P1[0].
If "1" then DIAGPORT[7] is mapped to P0[0] and P1[0], etc.
DIAGPORT[4] is mapped to P0[3] and P1[3],
DIAGPORT[3] is mapped to P0[4], etc. and
DIAGPORT[0] is mapped to P0[7].

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4:3 R/W DIAGPORT_SEL BLE/RADIO Diagnostic Port Selection. 0x0
Controls the multiplexing of the internal diagnostic signals

towards the 8-bit diagnostic bus DIAGPORT[7:0]. The DIAG-
PORT[7:0] bit order may or may not be reversed by using
the DIAGPORT_REVERSE bitfield and then it will be
directed to the GPIOs P0[7:0] and P1[3:0]. (Note that the
P1[3:0] diagnostic signals are the same with P0[3:0] signals.)
The DIAGPORT[7:0] value, depending on the

DIAGPORT_SEL value, is:
00: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2:0]}
01: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2]
, wakeup_lp_irq, deep_sleep_stat_32k}
10: RADIO_DIAG0[7:0]
11: RADIO_DIAG1[7:0]
2 R/W EMACCERRMSK Exchange Memory Access Error Mask: 0x1
When cleared to "0" the EM_ACC_ERR will not cause an
BLE_ERROR_IRQ interrupt.
When set to "1" an BLE_ERROR_IRQ will be generated as
long as EM_ACC_ERR is "1".
1 W EMACCERRACK Exchange Memory Access Error Acknowledge. 0x0
When the SW writes a "1" to this bit then the EMAC-
CERRSTAT bit will be cleared.
When the SW writes "0" it will have no affect.
The read value is always "0".
0 R EMACCERRSTAT Exchange Memory Access Error Status: 0x0
The bit is read-only and can be cleared only by writing a "1"
at EMACCERRACK bitfield.
This bit will be set to "1" by the hardware when the controller
will access an EM page that is not mapped according to the
EM_MAPPING value.
When this bit is "1" then the BLE_ERROR_IRQ will be
asserted as long as EMACCERRMSK is "1".
Table 74: BLE_RF_DIAGIRQ_REG (0x40000204)

31 R DIAGIRQ_STAT_3 Same as DIAGIRQ_STAT_0. 0
30 R/W DIAGIRQ_EDGE_3 Same as DIAGIRQ_EDGE_0. 0
29:27 R/W DIAGIRQ_BSEL_3 Same as DIAGIRQ_BSEL_0. 0
26:25 R/W DIAGIRQ_WSEL_3 Same as DIAGIRQ_WSEL_0. 0
24 R/W DIAGIRQ_MASK_3 Same as DIAGIRQ_MASK_0. 0

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Table 74: BLE_RF_DIAGIRQ_REG (0x40000204)

7 R DIAGIRQ_STAT_0 Diagnostic IRQ Status 0 0
This bit is read only. It is automatically cleared to "0" on each

read of the BLE_RF_DIAGIRQ_REG register. It is automati-
cally asserted to "1" on each detection of the selected edge,
of the selected bit, of the selected word.
6 R/W DIAGIRQ_EDGE_0 Diagnostic IRQ Edge 0 0
Selects the edge of the selected bit (refer to

DIAGIRQ_BSEL_0) that will trigger the assertion of
DIAGIRQ_STAT_0.
If '0' then the positive edge is selected, when "1" the nega-
tive edge is selected.
5:3 R/W DIAGIRQ_BSEL_0 Diagnostic IRQ Bit Select 0 0
Selects the bit of the 8-bit bus (as selected by the

DIAGIRQ_WSEL_0) that will be used for the IRQ generation.
2:1 R/W DIAGIRQ_WSEL_0 Diagnostic IRQ Word Select 0 0
Selects the 8-bit diagnostic bus that will be used for the IRQ
generation.
00: Selects the BLE_DIAG0

01: Selects the BLE_DIAG1
10: Selects the RADIO_DIAG0
11: Selects the RADIO_DIAG1
0 R/W DIAGIRQ_MASK_0 Diagnostic IRQ Mask 0 0
When set to "1" a BLE_RF_DIAG_IRQ will be generated on

each rise of the DIAGIRQ_STAT_0 bit.
When cleared to "0" no IRQ will be generated.
Table 75: OTPC_MODE_REG (0x40008000)

29:28 R/W OTPC_MODE_PRG_ Selects the source that is connected to the prg_port port of 0x0
PORT_MUX the controller.
00 - {16'd0, BANDGAP_REG[15:0]}
01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0,
RFIO_CTRL1_REG{7:0]}
10 - {3'd0, RF_LNA_CTRL3_REG[4:0],
RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]}
11 - {28'd0, RF_VCO_CTRL_REG[3:0]}
See OTPC_MODE_PRG_PORT_SEL about the use of the

prg_port
8 R/W OPTC_MODE_PRG_ Defines the timing that will be used for all the programming 0
FAST activities (APROG, MPROG and TWR)
0 - Selects the normal timing
1 - Selects the fast timing

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Table 75: OTPC_MODE_REG (0x40008000)

7 R/W OTPC_MODE_PRG_ Selects an alternative data source for the programming of 0x0
PORT_SEL the OTP macrocells, when the controller is configured in
APROG mode.
0 - The fifo will be used as the data source. The fifo will be
filled with a way defined by the register
OTPC_MODE_USE_DMA. The number of words that will be
programmed is defined by OTPC_NWORDS.
1 - Only one word will programmed. The value of the word is
contained in the prg_port port of the controller. The values of
the registers OTPC_MODE_USE_DMA, OTPC_NWORDS
and the contents of the FIFO will not be used.
6 R/W OTPC_MODE_TWO Defines the duration of each read from the OTP macrocells. 0x0
_CC_ACC 0 - Reads 16 bits of data every one clock cycle.
1 - Reads 16 bits of data every two clock cycles.
5 R/W OTPC_MODE_FIFO Writing 1, removes any content from the FIFO. This bit 0x0
_FLUSH returns automatically to 0.
4 R/W OTPC_MODE_USE_ Selects the use of the dma, when the controller is configured 0x0
DMA in one of the modes: AREAD or APROG.
0 - DMAis not used. The data should be transfered from/to
controller through OTPC_FFPRT_REG
1 - DMA is used. Data transfers from/to controller are per-
formed automatically. The AHB base address should be con-
figured in OTPC_AHBADR_REG before the selection of the
mode.
If programming of the OTPC_MODE_REG is performed
through the serial interface,the OTPC_MODE_USE_DMA
will be set to 0 automatically.
If the controller is in APROG mode and the
OTPC_MODE_PRG_PORT_SEL is enabled, the dma will
stay inactive.
3 - - Reserved 0x0
2:0 R/W OTPC_MODE_MOD Defines the mode of operation of the OTPC controller. The 0x0
E encoding of the modes is as follows:
000 - STBY mode
001 - MREAD mode
010 - MPROG mode
011 - AREAD mode
100 - APROG mode
101 - Test mode. Reserved
To manually move between modes, always return to STBY
mode first.
Table 76: OTPC_PCTRL_REG (0x40008004)

27 R/W OTPC_PCTRL_ENU Enables the programming in the upper bank of the OTP. 0x0
0 - Programming sequence is not applied in the upper bank.
1 - Programming sequence is applied in the upper bank.
26 R/W OTPC_PCTRL_BITU Defines the value of the selected bit in the upper bank, after 0x0
the programming sequence.

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Table 76: OTPC_PCTRL_REG (0x40008004)

25 R/W OTPC_PCTRL_ENL Enables the programming in the lower bank. 0x0
0 - The programming sequence is not applied in the lower
bank.
1 -The programming sequence is applied in the lower bank.
24 R/W OTPC_PCTRL_BITL Defines the value of the selected bit in the lower bank, after 0x0
the programming sequence.
23 R/W OTPC_PCTRL_BSE Selects between the U1 and U0 byte for the programming 0x0
LU sequence in the upper bank.
0 - Program the U0 byte
1 - Program the U1 byte
22:20 R/W OTPC_PCTRL_BAD Selects the bit inside the Ux (x=0,1) byte, which will be pro- 0x0
RU grammed in the upper bank.
19 R/W OTPC_PCTRL_BSE Selects between the L1 and L0 byte for the programming 0x0
LL sequence in the lower bank.
0 - Program the L0 byte
1 - Program the L1 byte
18:16 R/W OTPC_PCTRL_BAD Selects the bit inside the Lx (x=0,1) byte, which will be pro- 0x0
RL grammed in the lower bank.
12:0 R/W OTPC_PCTRL_WAD Defines the address of a 32 bits word {U1,L1,U0,L0} in the 0x0
DR macrocells, where one or two bits will be programmed.
There are two macrocell banks, with 8 bits each. Each bank
contribute with two memory positions for each 32 bits word.
The Ux, Lx represent the bytes of the upper and lower bank
respectively.
Table 77: OTPC_STAT_REG (0x40008008)

28:16 R OTPC_STAT_NWOR Contains the current value of the words to be processed. 0
DS
15 R OTPC_STAT_TERR_ Indicates the upper bank as the source of a test error. This 0x0
U value is valid when OTPC_STAT_TERROR is valid.
0 - There is no test error in the upper bank
1 - A test error has occured in the upper bank
14 R OTPC_STAT_TERR_ Indicates the lower bank as the source of a test error. The 0x0
L value is valid when OTPC_STAT_TERROR is valid.
0 - There is no test error in the lower bank
1 - A test error has occured in the lower bank
13 R OTPC_STAT_PERR_ Indicates the upper bank as the source of a programming 0x0
U error. The value is valid when OTPC_STAT_PERROR is
valid.
0 - There is no programming error in the upper bank
1 - A programming error has occured in the upper bank
12 R OTPC_STAT_PERR_ Indicates the lower bank as the source of a programming 0x0
L error. The value is valid when OTPC_STAT_PERROR is
valid.
0 - There is no programming error in the lower bank
1 - A programming error has occured in the lower bank
11:8 R OTPC_STAT_FWOR Indicates the number of words which contained in the fifo of 0x0
DS the controller.

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Table 77: OTPC_STAT_REG (0x40008008)

4 R OTPC_STAT_ARDY Monitors the progress of read or programming operations 0x1
while in the AREAD or APROG modes.
0 - The controller is busy while reading or programming
(AREAD or APROG modes).
1 - The controller is not busy in AREAD or APROG mode.
3 R OTPC_STAT_TERR Indicates the result of a test sequence. Should be checked 0x0
OR after the end of a TBLANK, TDEC and TWR mode
(OTPC_STAT_TRDY= 1).
0 - The test sequence ends with no error.
1 - The test sequence has failed.
2 R OTPC_STAT_TRDY Indicates the state of a test mode. Should be used to monitor 0x1
the progress of the TBLANK, TDEC and TWR modes.
0 - The controller is busy. A test mode is in progress.
1 - There is no active test mode.
1 R OTPC_STAT_PERR Indicates that an error has occurred during the bit-program- 0x0
OR ming process.
0 - No error during the bit-programming process.
1 - The process of bit-programming failed.
When the controller is in MPROG mode, this bit should be
checked after the end of the programming process
(OTPC_STAT_PRDY= 1).
During APROG mode, the value of this field is normal to
change periodically. Upon finishing the operation in the
APROG mode (OTPC_STAT_ARDY= 1), this field indicates
if the programming has failed or ended succesfully.
0 R OTPC_STAT_PRDY Indicates the state of a bit-programming process. 0x1
0 - The controller is busy. A bit-programming is in progress
1 - The logic which performs bit-programming is idle.
When the controller is in MPROG mode, this bit should be
used to monitor the progress of a programming request.
During APROG mode, the value of this field it is normal to
changing periodically.
Table 78: OTPC_AHBADR_REG (0x4000800C)

31:2 R/W OTPC_AHBADR Tthe AHB address used by the AHB master interface of the 0x0
controller (
bits [31:2]).
Table 79: OTPC_CELADR_REG (0x40008010)

12:0 R/W OTPC_CELADR Defines a word address inside the macrocell. Used in modes 0x0
AREAD and APROG and is automatically updated.
Table 80: OTPC_NWORDS_REG (0x40008014)


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Table 80: OTPC_NWORDS_REG (0x40008014)

12:0 R/W OTPC_NWORDS The number of words (minus one) for reading/programming 0x0
during the AREAD/APROG mode.
If in APROG mode, and the
OTPC_MODE_PRG_PORT_SEL is enabled (=1), this regis-
ter will not be used and will stay unchanged.
During mirroring, this register reflects the current amount of
data that will be copied. It keeps its value until be written by
the software with a new value. The number of the words that
remaining to be processed by the controller is contained in
the field OTPC_STAT_NWORDS.
Table 81: OTPC_FFPRT_REG (0x40008018)

31:0 R/W OTPC_FFPRT Provides access to the fifo through an access port. Write this 0x0
register with the corresponding data, when the APROG
mode is selected and the DMA is disabled. Read from this
register the corresponding data, when the AREAD mode is
selected and the DMA is disabled.
Check OTPC_STAT_FWORDS register for data/space avail-
ability, before accessing the fifo.
Table 82: OTPC_FFRD_REG (0x4000801C)

31:0 R OTPC_FFRD Contains the value read from the fifo, after a read of the 0x0
OTPC_FFPRT_REG register.
Table 83: CLK_AMBA_REG (0x50000000)

7 R/W OTP_ENABLE Clock enable for OTP controller 0x0
6 - - Reserved 0x0
5:4 R/W PCLK_DIV APB interface clock (PCLK). Divider is cascaded with 0x2
HCLK_DIV. PCLK is HCLK divided by:
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
1:0 R/W HCLK_DIV AHB interface and microprocessor clock (HCLK). HCLK is 0x2
source clock divided by:
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
Table 84: CLK_FREQ_TRIM_REG (0x50000002)


DA14580
Table 84: CLK_FREQ_TRIM_REG (0x50000002)

10:8 R/W COARSE_ADJ Xtal frequency course trimming register. 0x0
0x0: lowest frequency
0x7: highest frequencyIncrement or decrement the binary
value with 1. Wait approximately 200 us to allow the adjust-
ment to settle.
7:0 R/W FINE_ADJ Xtal frequency fine trimming register. 0x0
0xFF: highest frequency
Table 85: CLK_PER_REG (0x50000004)

15 R/W QUAD_ENABLE Enable the Quadrature clock 0x0
11 R/W SPI_ENABLE Enable SPI clock 0x0
10 - - Reserved 0x0
9:8 R/W SPI_DIV Division factor for SPI 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
7 R/W UART1_ENABLE Enable UART1 clock 0x0
6 R/W UART2_ENABLE Enable UART2 clock 0x0
5 R/W I2C_ENABLE Enable I2C clock 0x0
4 R/W WAKEUPCT_ENABL Enable Wakeup CaptureTimer clock 0x0
E
3 R/W TMR_ENABLE Enable TIMER0 and TIMER2 clock 0x0
2 - - Reserved 0x0
1:0 R/W TMR_DIV Division factor for TIMER0 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
Table 86: CLK_RADIO_REG (0x50000008)

7 R/W BLE_ENABLE Enable the BLE core clocks 0x0
6 R/W BLE_LP_RESET Reset for the BLE LP timer 0x1
5:4 R/W BLE_DIV Division factor for BLE core blocks 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
The programmed frequency should not be lower than 8 MHz
and not faster than the programmed CPU clock frequency.
Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
3 R/W RFCU_ENABLE Enable the RF control Unit clock 0x0
2 - - Reserved 0x0

DA14580
Table 86: CLK_RADIO_REG (0x50000008)

1:0 R/W RFCU_DIV Division factor for RF Control Unit 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
The programmed frequency must be exactly 8 MHz.
Table 87: CLK_CTRL_REG (0x5000000A)

7 R RUNNING_AT_XTAL Indicates that the XTAL16M clock is used as clock, and may 0x1
16M not be switched off
6 R RUNNING_AT_RC16 Indicates that the RC16M clock is used as clock 0x0
M
5 R RUNNING_AT_32K Indicates that either the RC32k or XTAL32k is being used as 0x0
clock
4 - - Reserved 0x0
3 R/W XTAL16M_SPIKE_FL Disable spikefilter in digital clock 0x0
T_DISABLE
2 R/W XTAL16M_DISABLE Setting this bit instantaneously disables the 16 MHz crystal 0x0
oscillator. Also, after sleep/wakeup cycle, the oscillator will
not be enabled. This bit may not be set to '1'when
"RUNNING_AT_XTAL16M is '1' to prevent deadlock. After
resetting this bit, wait for XTAL16_SETTLED or
XTAL16_TRIM_READY to become '1' before switching to
XTAL16 clock source.
1:0 R/W SYS_CLK_SEL Selects the clock source. 0x0
0x0: XTAL16M (check the XTAL16_SETTLED and
XTAL16_TRIM_READY bits!!)
0x1: RC16M
0x2/0x3: either RC32k or XTAL32k is used
Table 88: PMU_CTRL_REG (0x50000010)

11:8 R/W RETENTION_MODE Select the retainability of the 4 retention RAM macros. 0x0
'1' is retainable, '0' is power gated.
(3) is RETRAM4
(2) is RETRAM3
(1) is RETRAM2
(0) is RETRAM1
7 R/W FORCE_BOOST Force the DCDC into boost mode at next wakeup. 0x0
Setting this bit reduces the deepsleep current.
FORCE_BOOST has highest priority.
When either FORCE_BOOST or FORCE_BUCK have been
written, these bits cannot be changed.
6 R/W FORCE_BUCK Force the DCDC into buck mode at next wakeup. 0x0
Setting this bit reduces the deepsleep current.
FORCE_BOOST has highest priority.
When either FORCE_BOOST or FORCE_BUCK have been
written, these bits cannot be changed.

DA14580
Table 88: PMU_CTRL_REG (0x50000010)

5:4 R/W OTP_COPY_DIV Sets the HCLK division during OTP mirroring 0x0
2 R/W RADIO_SLEEP Put the digital part of the radio in powerdown 0x1
1 R/W PERIPH_SLEEP Put all peripherals (I2C, UART, SPI, ADC) in powerdown 0x1
0 R/W RESET_ON_WAKEU Perform a Hardware Reset after waking up. Booter will be 0x0
P started.
Table 89: SYS_CTRL_REG (0x50000012)

15 W SW_RESET Writing a '1' to this bit will reset the device, except for: 0x0
SYS_CTRL_REG
CLK_FREQ_TRIM_REG
...
9 R/W TIMEOUT_DISABLE Disables timeout in Power statemachine. By default, the 0x0
statemachine continues if after 2 ms the blocks are not
started up. This can be read back from
ANA_STATUS_REG.
8 - - Reserved 0x0
7 R/W DEBUGGER_ENABL Enable the debugger. This bit is set by the booter according 0x0
E to the OTP header. If not set, the SWDIO and SW_CLK can
be used as gpio ports.
6 R/W OTPC_RESET_REQ Reset request for the OTP controller. 0x0
5 R/W PAD_LATCH_EN Latches the control signals of the pads for state retention in 0x1
powerdown mode.
0: Control signals are retained
1: Latch is transparant, pad can be recontrolled
4 R/W OTP_COPY Enables OTP to SysRAM copy action after waking up 0x0
PD_SYS
3 R/W CLK32_SOURCE Sets the clock source of the 32 kHz clock 0x0
0 = RC-oscillator
1 = 32 kHz crystal oscillator
2 R/W RET_SYSRAM Sets the development phase mode. 0x0
The PD_SYS is not actually power gated (SysRAM is
retained).
No copy action to SysRAM is done when the system wakes
up.
For emulating startup time, the OTP_COPY bit still needs to
be set.
1:0 R/W REMAP_ADR0 Controls which memory is located at address 0x0000 for 0x0
execution.
0x0: ROM
0x1: OTP
0x2: SysRAM
0x3: RetRAM
Table 90: SYS_STAT_REG (0x50000014)

7 R XTAL16_SETTLED Indicates that XTAL16 has had > 2 ms of settle time 0x0
6 R XTAL16_TRIM_REA Indicates that XTAL trimming mechanism is ready, i.e. the 0x1
DY trimming equals CLK_FREQ_TRIM_REG.

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Table 90: SYS_STAT_REG (0x50000014)

5 R DBG_IS_UP Indicates that PD_DBG is functional 0x0
4 R DBG_IS_DOWN Indicates that PD_DBG is in power down 0x1
3 R PER_IS_UP Indicates that PD_PER is functional 0x0
2 R PER_IS_DOWN Indicates that PD_PER is in power down 0x1
1 R RAD_IS_UP Indicates that PD_RAD is functional 0x0
0 R RAD_IS_DOWN Indicates that PD_RAD is in power down 0x1
Table 91: TRIM_CTRL_REG (0x50000016)

7:4 R/W TRIM_TIME Defines the delay between XTAL16M enable and applying 0xA
the CLK_FREQ_TRIM_REG in steps of 250 us.
0x0: apply directly
0x1: wait between 0 and 250 us
0x2: wait between 250 us and 500 us
etc.
(Note 17)
3:0 R/W SETTLE_TIME Defines the delay between applying 0x2
CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of
250 us.
0x0: XTAL16_SETTLED is set direcly
0x1: wait between 0 and 250 us
0x2: wait between 250 us and 500 us
etc.
Note 17: The period duration of 250 us is derived by dividing the RC16M clock signal by 4000. Consequently, the period duration may vary over tem-
perature.
Table 92: CLK_32K_REG (0x50000020)

12 R/W XTAL32K_DISABLE_ Setting this bit disables the amplitude regulation of the 0x0
AMPREG XTAL32kHz oscillator.
Set this bit to '1' for an external clock applied at XTAL32Kp.
Keep this bit '0' with a crystal between XTAL32Kp and
XTAL32Km.
11:8 R/W RC32K_TRIM Controls the frequency of the RC32K oscillator. 0x7
0x7: default
0xF: highest frequency
7 R/W RC32K_ENABLE Enables the 32 kHz RC oscillator 0x1
6:3 R/W XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0x3
0x0: minimum
0x3: default
0xF: maximum
For each application there is an optimal setting for which the
startup behavior is optimal.
2:1 R/W XTAL32K_RBIAS Setting for the bias resistor of the 32 kHz XTAL oscillator. 0x2
0x0: maximum
0x3: minimum
Prefered setting will be provided by Dialog.
0 R/W XTAL32K_ENABLE Enables the 32 kHz XTAL oscillator 0x0

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Table 93: CLK_16M_REG (0x50000022)

9 R/W XTAL16_NOISE_FIL Enables noise flter in 16 MHz crystal oscillator 0x0
T_ENABLE
8 R/W XTAL16_BIAS_SH_E Enables Ibias sample/hold function in 16 MHz crystal oscilla- 0x0
NABLE tor. This bit should be set when the system wake up and
reset before entering deep or extended sleep mode.
7:5 R/W XTAL16_CUR_SET Bias current for the 16 MHz XTAL oscillator. 0x5
0x0: minimum
0x7: maximum
4:1 R/W RC16M_TRIM Controls the frequency of the RC16M oscillator. 0x0
0 R/W RC16M_ENABLE Enables the 16 MHz RC oscillator 0x0
Table 94: CLK_RCX20K_REG (0x50000024)

12 R/W RCX20K_SELECT Selects RCX oscillator. 0
0 : RC32K oscillator
1: RCX oscillator
11 R/W RCX20K_ENABLE Enable the RCX oscillator 0
10 R/W RCX20K_LOWF Extra low frequency 0
9:8 R/W RCX20K_BIAS Bias control 1
7:4 R/W RCX20K_NTC Temperature control 7
3:0 R/W RCX20K_TRIM Controls the frequency of the RCX oscillator. 8
0x7: default
Table 95: BANDGAP_REG (0x50000028)

15 - - Reserved 0x0
14 R/W BGR_LOWPOWER Test-mode, do not use. 0x0
It disables the bandgap core (voltages will continue for some
time, but will slowely drift away)
13:10 R/W LDO_RET_TRIM (Note 18) 0x0
9:5 R/W BGR_ITRIM Current trimming for bias 0x0
4:0 R/W BGR_TRIM Trim register for bandgap 0x0
Note 18: 0xF is the lowest voltage, but is too low for reliable startup at high temperature in combination with extended sleep. 0xA is 100 mV higher
and considered to be the lowest value which is safe to use. 0x0 or 0x1 is again 100 mV higher and 0x0 is the reset value. 0x4 is the maxi-
mum voltage.
Table 96: ANA_STATUS_REG (0x5000002A)

9 R BOOST_SELECTED Indicates that DCDC is in boost mode 0x0
8 - - Reserved 0x0

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Table 96: ANA_STATUS_REG (0x5000002A)

7 R BANDGAP_OK Indicates that BANDGAP is OK 0x1
6 R BOOST_VBAT_OK Indicates that VBAT is above threshold while in BOOST con- 0x0
verter mode.
5 R LDO_ANA_OK Indicates that LDO_ANA is in regulation. This LDO is used 0x0
for the general-purpose ADC only
4 R LDO_VDD_OK Indicates that LDO_VDD is in regulation 0x1
3 R LDO_OTP_OK Indicates that LDO_OTP is in regulation 0x0
2 R VDCDC_OK Indicates that VDCDC is above threshold. 0x0
1 R VBAT1V_OK Indicates that VBAT1V is above threshold. 0x0
0 R VBAT1V_AVAILABLE Indicates that VBAT1V is available. 0x0
Table 97: WKUP_CTRL_REG (0x50000100)

7 R/W WKUP_ENABLE_IR 0: no interrupt will be enabled 0x0
Q 1: if the event counter reaches the value set by
WKUP_COMPARE_REG an IRQ will be generated
6 R/W WKUP_SFT_KEYHIT 0: no effect 0x0
1: emulate key hit. The event counter will increment by 1
(after debouncing if enabled). First make this bit 0 before any
new key hit can be sensed.
5:0 R/W WKUP_DEB_VALUE Keyboard debounce time (N*1 ms with N = 1 to 63). 0x0
0x0: no debouncing
0x1 to 0x3F: 1 ms to 63 ms debounce time
Table 98: WKUP_COMPARE_REG (0x50000102)

7:0 R/W COMPARE The number of events that have to be counted before the 0x0
wakeup interrupt will be given
Table 99: WKUP_RESET_IRQ_REG (0x50000104)

15:0 W WKUP_IRQ_RST writing any value to this register will reset the interrupt. read- 0x0
ing always returns 0.
Table 100: WKUP_COUNTER_REG (0x50000106)

7:0 R EVENT_VALUE This value represents the number of events that have been 0x0
counted so far. It will be reset by resetting the interrupt.
Table 101: WKUP_RESET_CNTR_REG (0x50000108)

15:0 W WKUP_CNTR_RST writing any value to this register will reset the event counter 0x0
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Table 102: WKUP_SELECT_P0_REG (0x5000010A)

7:0 R/W WKUP_SELECT_P0 0: input P0x is not enabled for wakeup event counter 0x0
1: input P0x is enabled for wakeup event counter
Table 103: WKUP_SELECT_P1_REG (0x5000010C)

Table 104: WKUP_SELECT_P2_REG (0x5000010E)

Table 105: WKUP_SELECT_P3_REG (0x50000110)

Table 106: WKUP_POL_P0_REG (0x50000112)

7:0 R/W WKUP_POL_P0 0: enabled input P0x will increment the event counter if that 0x0
input goes high
1: enabled input P0x will increment the event counter if that
input goes low

input goes high
input goes low

input goes high
input goes low

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input goes high
input goes low
Table 110: QDEC_CTRL_REG (0x50000200)

9:3 R/W QD_IRQ_THRES The number of events on either counter (X or Y) that need to 0x2
be reached before an interrupt is generated. If 0 is written,
then threshold is considered to be 1.
2 R QD_IRQ_STATUS Interrupt Status. If 1 an interrupt has occured. 0x0
1 R/W QD_IRQ_CLR Writing 1 to this bit clears the interrupt. This bit is auto- 0x0
cleared
0 R/W QD_IRQ_MASK 0: interrupt is masked 0x0
1: interrupt is enabled
Table 111: QDEC_XCNT_REG (0x50000202)

15:0 R X_COUNTER Contains a signed value of the events. Zero when channel is 0x0
disabled
Table 112: QDEC_YCNT_REG (0x50000204)

15:0 R Y_COUNTER Contains a signed value of the events. Zero when channel is 0x0
disabled
Table 113: QDEC_CLOCKDIV_REG (0x50000206)

9:0 R/W CLOCK_DIVIDER Contains the number of the input clock cycles minus one, 0x0
that are required to generate one logic clock cycle.
Table 114: QDEC_CTRL2_REG (0x50000208)

15:12 - - Reserved 0

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Table 114: QDEC_CTRL2_REG (0x50000208)

11:8 R/W CHZ_PORT_SEL Defines which GPIOs are mapped on Channel Z 0
0: none
1: P0[0] -> CHZ_A, P0[1] -> CHZ_B
2: P0[2] -> CHZ_A, P0[3] -> CHZ_B
3: P0[4] -> CHZ_A, P0[5] -> CHZ_B
4: P0[6] -> CHZ_A, P0[7] -> CHZ_B
5: P1[0] -> CHZ_A, P1[1] -> CHZ_B
6: P1[2] -> CHZ_A, P1[3] -> CHZ_B
7: P2[3] -> CHZ_A, P2[4] -> CHZ_B
8: P2[5] -> CHZ_A, P2[6] -> CHZ_B
9: P2[7] -> CHZ_A, P2[8] -> CHZ_B
10: P2[9] -> CHZ_A, P2[0] -> CHZ_B
11..15: None
7:4 R/W CHY_PORT_SEL Defines which GPIOs are mapped on Channel Y 0
0: none
1: P0[0] -> CHY_A, P0[1] -> CHY_B
2: P0[2] -> CHY_A, P0[3] -> CHY_B
3: P0[4] -> CHY_A, P0[5] -> CHY_B
4: P0[6] -> CHY_A, P0[7] -> CHY_B
5: P1[0] -> CHY_A, P1[1] -> CHY_B
6: P1[2] -> CHY_A, P1[3] -> CHY_B
7: P2[3] -> CHY_A, P2[4] -> CHY_B
8: P2[5] -> CHY_A, P2[6] -> CHY_B
9: P2[7] -> CHY_A, P2[8] -> CHY_B
10: P2[9] -> CHY_A, P2[0] -> CHY_B
11..15: None
3:0 R/W CHX_PORT_SEL Defines which GPIOs are mapped on Channel X 0
0: none
1: P0[0] -> CHX_A, P0[1] -> CHX_B
2: P0[2] -> CHX_A, P0[3] -> CHX_B
3: P0[4] -> CHX_A, P0[5] -> CHX_B
4: P0[6] -> CHX_A, P0[7] -> CHX_B
5: P1[0] -> CHX_A, P1[1] -> CHX_B
6: P1[2] -> CHX_A, P1[3] -> CHX_B
7: P2[3] -> CHX_A, P2[4] -> CHX_B
8: P2[5] -> CHX_A, P2[6] -> CHX_B
9: P2[7] -> CHX_A, P2[8] -> CHX_B
10: P2[9] -> CHX_A, P2[0] -> CHX_B
11..15: None
Table 115: QDEC_ZCNT_REG (0x5000020A)

15:0 R Z_COUNTER Contains a signed value of the events. Zero when channel is 0
disabled
Table 116: UART_RBR_THR_DLL_REG (0x50001000)


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Table 116: UART_RBR_THR_DLL_REG (0x50001000)

7:0 R/W RBR_THR_DLL Receive Buffer Register: This register contains the data byte 0x0
received on the serial input port (sin) in UART mode or the
serial infrared input (sir_in) in infrared mode. The data in this
register is valid only if the Data Ready (DR) bit in the Line
status Register (LSR) is set. If FIFOs are disabled (FCR[0]
set to zero), the data in the RBR must be read before the
next data arrives, otherwise it will be overwritten, resulting in
an overrun error. If FIFOs are enabled (FCR[0] set to one),
this register accesses the head of the receive FIFO. If the
receive FIFO is full and this register is not read before the
next data character arrives, then the data already in the
FIFO will be preserved but any incoming data will be lost. An
overrun error will also occur. Transmit Holding Register: This
register contains data to be transmitted on the serial output
port (sout) in UART mode or the serial infrared output
(sir_out_n) in infrared mode. Data should only be written to
the THR when the THR Empty (THRE) bit (LSR[5]) is set. If
FIFO's are disabled (FCR[0] set to zero) and THRE is set,
writing a single character to the THR clears the THRE. Any
additional writes to the THR before the THRE is set again
causes the THR data to be overwritten. If FIFO's are enabled
(FCR[0] set to one) and THRE is set, x number of characters
of data may be written to the THR before the FIFO is full.
The number x (default=16) is determined by the value of
FIFO Depth that you set during configuration. Any attempt to
write data when the FIFO is full results in the write data being
lost. Divisor Latch (Low): This register makes up the lower 8-
bits of a 16-bit, read/write, Divisor Latch register that con-
tains the baud rate divisor for the UART. This register may
only be accessed when the DLAB bit (LCR[7]) is set. The
output baud rate is equal to the serial clock (sclk) frequency
divided by sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq) / (16 * divisor) Note
that with the Divisor Latch Registers (DLL and DLH) set to
zero, the baud clock is disabled and no serial communica-
tions will occur. Also, once the DLL is set, at least 8 clock
cycles of the slowest DW_apb_uart clock should be allowed
to pass before transmitting or receiving data.
Table 117: UART_IER_DLH_REG (0x50001004)

7 R/W PTIME_DLH7 Interrupt Enable Register: PTIME, Programmable THRE 0x0
Interrupt Mode Enable. This is used to enable/disable the
generation of THRE Interrupt. 0 = disabled 1 = enabled Divi-
sor Latch (High): Bit[7] of the 8 bit DLH register.
3 R/W EDSSI_DLH3 Interrupt Enable Register: EDSSI, Enable Modem Status 0x0
Interrupt. This is used to enable/disable the generation of
Modem Status Interrupt. This is the fourth highest priority
interrupt. 0 = disabled 1 = enabled Divisor Latch (High):
Bit[3] of the 8 bit DLH register

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Table 117: UART_IER_DLH_REG (0x50001004)

2 R/W ELSI_DHL2 Interrupt Enable Register: ELSI, Enable Receiver Line Sta- 0x0
tus Interrupt. This is used to enable/disable the generation of
Receiver Line Status Interrupt. This is the highest priority
Bit[2] of the 8 bit DLH register.
1 R/W ETBEI_DLH1 Interrupt Enable Register: ETBEI, Enable Transmit Holding 0x0
Register Empty Interrupt. This is used to enable/disable the
generation of Transmitter Holding Register Empty Interrupt.
This is the third highest priority interrupt. 0 = disabled 1 =
enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.
0 R/W ERBFI_DLH0 Interrupt Enable Register: ERBFI, Enable Received Data 0x0
Available Interrupt. This is used to enable/disable the gener-
ation of Received Data Available Interrupt and the Character
Timeout Interrupt (if in FIFO mode and FIFO's enabled).
These are the second highest priority interrupts. 0 = disabled
1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH reg-
ister.

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Table 118: UART_IIR_FCR_REG (0x50001008)

15:0 R/W IIR_FCR Interrupt Identification Register, reading this register; FIFO 0x0
Control Register, writing to this register. Interrupt Identifica-
tion Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is
used to indicate whether the FIFO's are enabled or disabled.
00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID):
This indicates the highest priority pending interrupt which
can be one of the following types: 0000 = modem status.
0001 = no interrupt pending. 0010 = THR empty. 0100 =
received data available. 0110 = receiver line status. 0111 =
busy detect. 1100 = character timeout. Bits[7:6], RCVR Trig-
ger (or RT):. This is used to select the trigger level in the
receiver FIFO at which the Received Data Available Interrupt
will be generated. In auto flow control mode it is used to
determine when the rts_n signal will be de-asserted. It also
determines when the dma_rx_req_n signal will be asserted
when in certain modes of operation. The following trigger
levels are supported: 00 = 1 character in the FIFO 01 = FIFO
1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4],
TX Empty Trigger (or TET): This is used to select the empty
threshold level at which the THRE Interrupts will be gener-
ated when the mode is active. It also determines when the
dma_tx_req_n signal will be asserted when in certain modes
of operation. The following trigger levels are supported: 00 =
FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full
11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This deter-
mines the DMA signalling mode used for the dma_tx_req_n
and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1
Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control
portion of the transmit FIFO and treats the FIFO as empty.
Note that this bit is 'self-clearing' and it is not necessary to
clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This
resets the control portion of the receive FIFO and treats the
FIFO as empty. Note that this bit is 'self-clearing' and it is not
necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE):
This enables/disables the transmit (XMIT) and receive
(RCVR) FIFO's. Whenever the value of this bit is changed
both the XMIT and RCVR controller portion of FIFO's will be
reset.
Table 119: UART_LCR_REG (0x5000100C)

7 R/W UART_DLAB Divisor Latch Access Bit. 0x0
This bit is used to enable reading and writing of the Divisor
Latch register (DLL and DLH) to set the baud rate of the
UART.
This bit must be cleared after initial baud rate setup in order
to access other registers.

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Table 119: UART_LCR_REG (0x5000100C)

6 R/W UART_BC Break Control Bit. 0x0
This is used to cause a break condition to be transmitted to
the receiving device. If set to one the serial output is forced
to the spacing (logic 0) state. When not in Loopback Mode,
as determined by MCR[4], the sout line is forced low until the
Break bit is cleared. If active (MCR[6] set to one) the
sir_out_n line is continuously pulsed. When in Loopback
Mode, the break condition is internally looped back to the
receiver and the sir_out_n line is forced low.
5 - - Reserved 0x0
4 R/W UART_EPS Even Parity Select. 0x0
This is used to select between even and odd parity, when
parity is enabled (PEN set to one). If set to one, an even
number of logic 1s is transmitted or checked. If set to zero,
an odd number of logic 1s is transmitted or checked.
3 R/W UART_PEN Parity Enable. 0x0
This bit is used to enable and disable parity generation and
detection in transmitted and received serial character
respectively.
0 = parity disabled
1 = parity enabled
2 R/W UART_STOP Number of stop bits. 0x0
This is used to select the number of stop bits per character
that the peripheral transmits and receives. If set to zero, one
stop bit is transmitted in the serial data.
If set to one and the data bits are set to 5 (LCR[1:0] set to
zero) one and a half stop bits is transmitted. Otherwise, two
stop bits are transmitted. Note that regardless of the number
of stop bits selected, the receiver checks only the first stop
bit.
0 = 1 stop bit
1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
1:0 R/W UART_DLS Data Length Select. 0x0
This is used to select the number of data bits per character
that the peripheral transmits and receives. The number of bit
that may be selected areas follows:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Table 120: UART_MCR_REG (0x50001010)

6 R/W UART_SIRE SIR Mode Enable. 0x0
This is used to enable/disable the IrDA SIR Mode features
as described in "IrDA 1.0 SIR Protocol" on page 53.
0 = IrDA SIR Mode disabled
1 = IrDA SIR Mode enabled
5 R/W UART_AFCE Auto Flow Control Enable. 0x0
When FIFOs are enabled and the Auto Flow Control Enable
(AFCE) bit is set, hardware Auto Flow Control is enabled via
CTS and RTS.
0 = Auto Flow Control Mode disabled
1 = Auto Flow Control Mode enabled
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Table 120: UART_MCR_REG (0x50001010)

4 R/W UART_LB LoopBack Bit. 0x0
This is used to put the UART into a diagnostic mode for test
purposes.
If operating in UART mode (SIR_MODE not active, MCR[6]
set to zero), data on the sout line is held high, while serial
data output is looped back to the sin line, internally. In this
mode all the interrupts are fully functional. Also, in loopback
mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n)
are disconnected and the modem control outputs (dtr_n,
rts_n, out1_n, out2_n) are looped back to the inputs, inter-
nally.
If operating in infrared mode (SIR_MODE active, MCR[6] set
to one), data on the sir_out_n line is held low, while serial
data output is inverted and looped back to the sir_in line.
3 R/W UART_OUT2 OUT2. 0x0
This is used to directly control the user-designated Output2
(out2_n) output. The value written to this location is inverted
and driven out on out2_n, that is:
0 = out2_n de-asserted (logic 1)
1 = out2_n asserted (logic 0)
Note that in Loopback mode (MCR[4] set to one), the out2_n
output is held inactive high while the value of this location is
internally looped back to an input.
1 R/W UART_RTS Request to Send. 0x0
This is used to directly control the Request to Send (rts_n)
output. The Request To Send (rts_n) output is used to inform
the modem or data set that the UART is ready to exchange
data.
When Auto Flow Control is disabled (MCR[5] set to zero),
the rts_n signal is set low by programming MCR[1] (RTS) to
a high. When Auto Flow Control is enabled (MCR[5] set to
one) and FIFOs are enabled (FCR[0] set to one), the rts_n
output is controlled in the same way, but is also gated with
the receiver FIFO threshold trigger (rts_n is inactive high
when above the threshold). The rts_n signal is de-asserted
when MCR[1] is set low.
Note that in Loopback mode (MCR[4] set to one), the rts_n
output is held inactive (high) while the value of this location is
0 - - Reserved 0x0
Table 121: UART_LSR_REG (0x50001014)


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7 R UART_RFE Receiver FIFO Error bit. 0x0
This bit is only relevant when FIFOs are enabled (FCR[0] set
to one). This is used to indicate if there is at least one parity
error, framing error, or break indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the LSR is read and the character
with the error is at the top of the receiver FIFO and there are
no subsequent errors in the FIFO.
6 R UART_TEMT Transmitter Empty bit. 0x1
If FIFOs enabled (FCR[0] set to one), this bit is set whenever
the Transmitter Shift Register and the FIFO are both empty.
If FIFOs are disabled, this bit is set whenever the Transmitter
Holding Register and the Transmitter Shift Register are both
empty.
5 R UART_THRE Transmit Holding Register Empty bit. 0x1
If THRE mode is disabled (IER[7] set to zero) and regardless
of FIFO's being implemented/enabled or not, this bit indi-
cates that the THR or TX FIFO is empty.
This bit is set whenever data is transferred from the THR or
TX FIFO to the transmitter shift register and no new data has
been written to the THR or TX FIFO. This also causes a
THRE Interrupt to occur, if the THRE Interrupt is enabled. If
both modes are active (IER[7] set to one and FCR[0] set to
one respectively), the functionality is switched to indicate the
transmitter FIFO is full, and no longer controls THRE inter-
rupts, which are then controlled by the FCR[5:4] threshold
setting.
4 R UART_B1 Break Interrupt bit. 0x0
This is used to indicate the detection of a break sequence on
the serial input data.
If in UART mode (SIR_MODE == Disabled), it is set when-
ever the serial input, sin, is held in a logic '0' state for longer
than the sum of start time + data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set when-
ever the serial input, sir_in, is continuously pulsed to logic '0'
for longer than the sum of start time + data bits + parity +
stop bits. A break condition on serial input causes one and
only one character, consisting of all zeros, to be received by
the UART.
In the FIFO mode, the character associated with the break
condition is carried through the FIFO and is revealed when
the character is at the top of the FIFO.
Reading the LSR clears the BI bit. In the non-FIFO mode,
the BI indication occurs immediately and persists until the
LSR is read.

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3 R UART_FE Framing Error bit. 0x0
This is used to indicate the occurrence of a framing error in
the receiver. A framing error occurs when the receiver does
not detect a valid STOP bit in the received data.
In the FIFO mode, since the framing error is associated with
a character received, it is revealed when the character with
the framing error is at the top of the FIFO.
When a framing error occurs, the UART tries to resynchro-
nize. It does this by assuming that the error was due to the
start bit of the next character and then continues receiving
the other bit i.e. data, and/or parity and stop. It should be
noted that the Framing Error (FE) bit (LSR[3]) is set if a
break interrupt has occurred, as indicated by Break Interrupt
(BI) bit (LSR[4]).
0 = no framing error
1 = framing error
Reading the LSR clears the FE bit.
2 R UART_PE Parity Error bit. 0x0
This is used to indicate the occurrence of a parity error in the
receiver if the Parity Enable (PEN) bit (LCR[3]) is set.
In the FIFO mode, since the parity error is associated with a
character received, it is revealed when the character with the
parity error arrives at the top of the FIFO.
It should be noted that the Parity Error (PE) bit (LSR[2]) is
set if a break interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
Reading the LSR clears the PE bit.
1 R UART_OE Overrun error bit. 0x0
This is used to indicate the occurrence of an overrun error.
This occurs if a new data character was received before the
previous data was read.
In the non-FIFO mode, the OE bit is set when a new charac-
ter arrives in the receiver before the previous character was
read from the RBR. When this happens, the data in the RBR
is overwritten. In the FIFO mode, an overrun error occurs
when the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the data in the
receive shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.
0 R UART_DR Data Ready bit. 0x0
This is used to indicate that the receiver contains at least
one character in the RBR or the receiver FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-FIFO mode,
or when the receiver FIFO is empty, in FIFO mode.
Table 122: UART_MSR_REG (0x50001018)


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7 R UART_DCD Data Carrier Detect. 0x0
This is used to indicate the current state of the modem con-
trol line dcd_n. This bit is the complement of dcd_n. When
the Data Carrier Detect input (dcd_n) is asserted it is an indi-
cation that the carrier has been detected by the modem or
data set.
0 = dcd_n input is de-asserted (logic 1)
1 = dcd_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DCD is the same as
MCR[3] (Out2).
6 R UART_R1 Ring Indicator. 0x0
trol line ri_n. This bit is the complement of ri_n. When the
Ring Indicator input (ri_n) is asserted it is an indication that a
telephone ringing signal has been received by the modem or
data set.
0 = ri_n input is de-asserted (logic 1)
1 = ri_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), RI is the same as
MCR[2] (Out1).
5 - - Reserved 0x0
4 R UART_CTS Clear to Send. 0x0
trol line cts_n. This bit is the complement of cts_n. When the
Clear to Send input (cts_n) is asserted it is an indication that
the modem or data set is ready to exchange data with the
UART Ctrl.
0 = cts_n input is de-asserted (logic 1)
1 = cts_n input is asserted (logic 0)
In Loopback Mode (MCR[4] = 1), CTS is the same as
MCR[1] (RTS).
3 R UART_DDCD Delta Data Carrier Detect. 0x0
This is used to indicate that the modem control line dcd_n
has changed since the last time the MSR was read.
0 = no change on dcd_n since last read of MSR
1 = change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit. In Loopback Mode
(MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2).
Note, if the DDCD bit is not set and the dcd_n signal is
asserted (low) and a reset occurs (software or otherwise),
then the DDCD bit is set when the reset is removed if the
dcd_n signal remains asserted.
2 R UART_TERI Trailing Edge of Ring Indicator. 0x0
This is used to indicate that a change on the input ri_n (from
an active-low to an inactive-high state) has occurred since
the last time the MSR was read.
0 = no change on ri_n since last read of MSR
1 = change on ri_n since last read of MSR
Reading the MSR clears the TERI bit. In Loopback Mode
(MCR[4] = 1), TERI reflects when MCR[2] (Out1) has
changed state from a high to a low.
1 - - Reserved 0x0

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0 R UART_DCTS Delta Clear to Send. 0x0
This is used to indicate that the modem control line cts_n
0 = no change on cts_n since last read of MSR
1 = change on cts_n since last read of MSR
Reading the MSR clears the DCTS bit. In Loopback Mode
(MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).
Note, if the DCTS bit is not set and the cts_n signal is
then the DCTS bit is set when the reset is removed if the
cts_n signal remains asserted.
Table 123: UART_SCR_REG (0x5000101C)

7:0 R/W UART_SCRATCH_P This register is for programmers to use as a temporary stor- 0x0
AD age space. It has no defined purpose in the UART Ctrl.
Table 124: UART_LPDLL_REG (0x50001020)

7:0 R/W UART_LPDLL This register makes up the lower 8-bits of a 16-bit, read/ 0x0
write, Low Power Divisor Latch register that contains the
baud rate divisor for the UART, which must give a baud rate
of 115.2K. This is required for SIR Low Power (minimum
pulse width) detection at the receiver. This register may be
accessed only when the DLAB bit (LCR[7]) is set.
The output low-power baud rate is equal to the serial clock
(sclk) frequency divided by sixteen times the value of the
baud rate divisor, as follows:
Low power baud rate = (serial clock frequency)/(16* divisor)
Therefore, a divisor must be selected to give a baud rate of
115.2K.
NOTE: When the Low Power Divisor Latch registers (LPDLL
and LPDLH) are set to 0, the low-power baud clock is dis-
abled and no low-power pulse detection (or any pulse detec-
tion) occurs at the receiver. Also, once the LPDLL is set, at
least eight clock cycles of the slowest UART Ctrl clock
should be allowed to pass before transmitting or receiving
data.
Table 125: UART_LPDLH_REG (0x50001024)


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Table 125: UART_LPDLH_REG (0x50001024)

7:0 R/W UART_LPDLH This register makes up the upper 8-bits of a 16-bit, read/ 0x0
115.2K.
tion) occurs at the receiver. Also, once the LPDLH is set, at
data.
Table 126: UART_SRBR_STHR0_REG (0x50001030)

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0
for the RBR and has been allocated sixteen 32-bit locations
so as to accommodate burst accesses from the master. This
register contains the data byte received on the serial input
port (sin) in UART mode or the serial infrared input (sir_in) in
infrared mode. The data in this register is valid only if the
Data Ready (DR) bit in the Line status Register (LSR) is set.
If FIFOs are disabled (FCR[0] set to zero), the data in the
RBR must be read before the next data arrives, otherwise it
will be overwritten, resulting in an overrun error. If FIFOs are
enabled (FCR[0] set to one), this register accesses the head
of the receive FIFO. If the receive FIFO is full and this regis-
ter is not read before the next data character arrives, then
the data already in the FIFO will be preserved but any
incoming data will be lost. An overrun error will also occur.
Shadow Transmit Holding Register 0: This is a shadow reg-
ister for the THR and has been allocated sixteen 32-bit loca-
tions so as to accommodate burst accesses from the master.
This register contains data to be transmitted on the serial
output port (sout) in UART mode or the serial infrared output
lost.

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lost.


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lost.
Table 129: UART_SRBR_STHR3_REG (0x5000103C)


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


DA14580

lost.


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lost.


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lost.


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lost.


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lost.
Table 142: UART_USR_REG (0x5000107C)

4 R UART_RFF Receive FIFO Full. 0x0
This is used to indicate that the receive FIFO is completely
full.
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.
3 R UART_RFNE Receive FIFO Not Empty. 0x0
This is used to indicate that the receive FIFO contains one or
more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
2 R UART_TFE Transmit FIFO Empty. 0x1
This is used to indicate that the transmit FIFO is completely
empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.

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Table 142: UART_USR_REG (0x5000107C)

1 R UART_TFNF Transmit FIFO Not Full. 0x1
This is used to indicate that the transmit FIFO in not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0 - - Reserved 0x0
Table 143: UART_TFL_REG (0x50001080)

15:0 R UART_TRANSMIT_F Transmit FIFO Level. 0x0
IFO_LEVEL This is indicates the number of data entries in the transmit
FIFO.
Table 144: UART_RFL_REG (0x50001084)

15:0 R UART_RECEIVE_FI Receive FIFO Level. 0x0
FO_LEVEL This is indicates the number of data entries in the receive
FIFO.
Table 145: UART_SRR_REG (0x50001088)

2 W UART_XFR XMIT FIFO Reset. 0x0
This is a shadow register for the XMIT FIFO Reset bit
(FCR[2]). This can be used to remove the burden on soft-
ware having to store previously written FCR values (which
are pretty static) just to reset the transmit FIFO. This resets
the control portion of the transmit FIFO and treats the FIFO
as empty. Note that this bit is 'self-clearing'. It is not neces-
sary to clear this bit.
1 W UART_RFR RCVR FIFO Reset. 0x0
This is a shadow register for the RCVR FIFO Reset bit
are pretty static) just to reset the receive FIFO This resets
the control portion of the receive FIFO and treats the FIFO
as empty.
Note that this bit is 'self-clearing'. It is not necessary to clear
this bit.
0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and 0x0
synchronously removes the reset assertion. For a two clock
implementation both pclk and sclk domains are reset.
Table 146: UART_SRTS_REG (0x5000108C)


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Table 146: UART_SRTS_REG (0x5000108C)

0 R/W UART_SHADOW_R Shadow Request to Send. 0x0
EQUEST_TO_SEND This is a shadow register for the RTS bit (MCR[1]), this can
be used to remove the burden of having to perform a read-
modify-write on the MCR. This is used to directly control the
Request to Send (rts_n) output. The Request To Send
(rts_n) output is used to inform the modem or data set that
the UART Ctrl is ready to exchange data.
When Auto Flow Control is disabled (MCR[5] = 0), the rts_n
signal is set low by programming MCR[1] (RTS) to a high.
When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs
are enabled (FCR[0] = 1), the rts_n output is controlled in the
same way, but is also gated with the receiver FIFO threshold
trigger (rts_n is inactive high when above the threshold).
Note that in Loopback mode (MCR[4] = 1), the rts_n output is
held inactive-high while the value of this location is internally
looped back to an input.
Table 147: UART_SBCR_REG (0x50001090)

0 R/W UART_SHADOW_B Shadow Break Control Bit. 0x0
REAK_CONTROL This is a shadow register for the Break bit (LCR[6]), this can
be used to remove the burden of having to performing a read
modify write on the LCR. This is used to cause a break con-
dition to be transmitted to the receiving device.
If set to one the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined by
MCR[4], the sout line is forced low until the Break bit is
cleared.
If SIR_MODE active (MCR[6] = 1) the sir_out_n line is con-
tinuously pulsed. When in Loopback Mode, the break condi-
tion is internally looped back to the receiver.
Table 148: UART_SDMAM_REG (0x50001094)

0 R/W UART_SHADOW_D Shadow DMA Mode. 0x0
MA_MODE This is a shadow register for the DMA mode bit (FCR[3]).
This can be used to remove the burden of having to store the
previously written value to the FCR in memory and having to
mask this value so that only the DMA Mode bit gets updated.
This determines the DMA signalling mode used for the
dma_tx_req_n and dma_rx_req_n output signals.
0 = mode 0
1 = mode 1
Table 149: UART_SFE_REG (0x50001098)


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Table 149: UART_SFE_REG (0x50001098)

0 R/W UART_SHADOW_FI Shadow FIFO Enable. 0x0
FO_ENABLE This is a shadow register for the FIFO enable bit (FCR[0]).
mask this value so that only the FIFO enable bit gets
updated.This enables/disables the transmit (XMIT) and
receive (RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR controller
portion of FIFOs are reset.
Table 150: UART_SRT_REG (0x5000109C)

1:0 R/W UART_SHADOW_R Shadow RCVR Trigger. 0x0
CVR_TRIGGER This is a shadow register for the RCVR trigger bits
(FCR[7:6]). This can be used to remove the burden of having
to store the previously written value to the FCR in memory
and having to mask this value so that only the RCVR trigger
bit gets updated.
This is used to select the trigger level in the receiver FIFO at
which the Received Data Available Interrupt is generated. It
also determines when the dma_rx_req_n signal is asserted
when DMA Mode (FCR[3]) = 1. The following trigger levels
are supported:
00 = 1 character in the FIFO
01 = FIFO Â¼ full
10 = FIFO Â½ full
11 = FIFO 2 less than full
Table 151: UART_STET_REG (0x500010A0)

1:0 R/W UART_SHADOW_TX Shadow TX Empty Trigger. 0x0
_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits
and having to mask this value so that only the TX empty trig-
ger bit gets updated.
This is used to select the empty threshold level at which the
THRE Interrupts are generated when the mode is active.
The following trigger levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO Â¼ full
11 = FIFO Â½ full
Table 152: UART_HTX_REG (0x500010A4)


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Table 152: UART_HTX_REG (0x500010A4)

0 R/W UART_HALT_TX This register is use to halt transmissions for testing, so that 0x0
the transmit FIFO can be filled by the master when FIFOs
are implemented and enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled, the setting
of the halt TX register has no effect on operation.
Table 153: UART_CPR_REG (0x500010F4)

15:0 R CPR Component Parameter Register 0x0
Table 154: UART_UCV_REG (0x500010F8)

15:0 R UCV Component Version 0x33303
82A
Table 155: UART_CTR_REG (0x500010FC)

15:0 R CTR Component Type Register 0x44570
110
Table 156: UART2_RBR_THR_DLL_REG (0x50001100)


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Table 156: UART2_RBR_THR_DLL_REG (0x50001100)

7:0 R/W RBR_THR_DLL Receive Buffer Register: This register contains the data byte 0x0
received on the serial input port (sin) in UART mode or the
serial infrared input (sir_in) in infrared mode. The data in this
register is valid only if the Data Ready (DR) bit in the Line
status Register (LSR) is set. If FIFOs are disabled (FCR[0]
set to zero), the data in the RBR must be read before the
next data arrives, otherwise it will be overwritten, resulting in
an overrun error. If FIFOs are enabled (FCR[0] set to one),
this register accesses the head of the receive FIFO. If the
receive FIFO is full and this register is not read before the
next data character arrives, then the data already in the
FIFO will be preserved but any incoming data will be lost. An
overrun error will also occur. Transmit Holding Register: This
register contains data to be transmitted on the serial output
port (sout) in UART mode or the serial infrared output
lost. Divisor Latch (Low): This register makes up the lower 8-
bits of a 16-bit, read/write, Divisor Latch register that con-
tains the baud rate divisor for the UART. This register may
only be accessed when the DLAB bit (LCR[7]) is set. The
output baud rate is equal to the serial clock (sclk) frequency
divided by sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq) / (16 * divisor) Note
that with the Divisor Latch Registers (DLL and DLH) set to
zero, the baud clock is disabled and no serial communica-
tions will occur. Also, once the DLL is set, at least 8 clock
cycles of the slowest DW_apb_uart clock should be allowed
to pass before transmitting or receiving data.
Table 157: UART2_IER_DLH_REG (0x50001104)

7 R/W PTIME_DLH7 Interrupt Enable Register: PTIME, Programmable THRE 0x0
Interrupt Mode Enable. This is used to enable/disable the
generation of THRE Interrupt. 0 = disabled 1 = enabled Divi-
sor Latch (High): Bit[7] of the 8 bit DLH register.
3 R/W EDSSI_DLH3 Interrupt Enable Register: EDSSI, Enable Modem Status 0x0
Interrupt. This is used to enable/disable the generation of
Modem Status Interrupt. This is the fourth highest priority
Bit[3] of the 8 bit DLH register

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Table 157: UART2_IER_DLH_REG (0x50001104)

2 R/W ELSI_DHL2 Interrupt Enable Register: ELSI, Enable Receiver Line Sta- 0x0
tus Interrupt. This is used to enable/disable the generation of
Receiver Line Status Interrupt. This is the highest priority
Bit[2] of the 8 bit DLH register.
1 R/W ETBEI_DLH1 Interrupt Enable Register: ETBEI, Enable Transmit Holding 0x0
Register Empty Interrupt. This is used to enable/disable the
generation of Transmitter Holding Register Empty Interrupt.
This is the third highest priority interrupt. 0 = disabled 1 =
enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.
0 R/W ERBFI_DLH0 Interrupt Enable Register: ERBFI, Enable Received Data 0x0
Available Interrupt. This is used to enable/disable the gener-
ation of Received Data Available Interrupt and the Character
Timeout Interrupt (if in FIFO mode and FIFO's enabled).
These are the second highest priority interrupts. 0 = disabled
1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH reg-
ister.

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Table 158: UART2_IIR_FCR_REG (0x50001108)

15:0 R/W IIR_FCR Interrupt Identification Register, reading this register; FIFO 0x0
Control Register, writing to this register. Interrupt Identifica-
tion Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is
used to indicate whether the FIFO's are enabled or disabled.
00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID):
This indicates the highest priority pending interrupt which
can be one of the following types: 0000 = modem status.
0001 = no interrupt pending. 0010 = THR empty. 0100 =
received data available. 0110 = receiver line status. 0111 =
busy detect. 1100 = character timeout. Bits[7:6], RCVR Trig-
ger (or RT):. This is used to select the trigger level in the
receiver FIFO at which the Received Data Available Interrupt
will be generated. In auto flow control mode it is used to
determine when the rts_n signal will be de-asserted. It also
determines when the dma_rx_req_n signal will be asserted
when in certain modes of operation. The following trigger
levels are supported: 00 = 1 character in the FIFO 01 = FIFO
1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4],
TX Empty Trigger (or TET): This is used to select the empty
threshold level at which the THRE Interrupts will be gener-
ated when the mode is active. It also determines when the
dma_tx_req_n signal will be asserted when in certain modes
of operation. The following trigger levels are supported: 00 =
FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full
11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This deter-
mines the DMA signalling mode used for the dma_tx_req_n
and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1
Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control
portion of the transmit FIFO and treats the FIFO as empty.
Note that this bit is 'self-clearing' and it is not necessary to
clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This
resets the control portion of the receive FIFO and treats the
FIFO as empty. Note that this bit is 'self-clearing' and it is not
necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE):
This enables/disables the transmit (XMIT) and receive
(RCVR) FIFO's. Whenever the value of this bit is changed
both the XMIT and RCVR controller portion of FIFO's will be
reset.
Table 159: UART2_LCR_REG (0x5000110C)

7 R/W UART_DLAB Divisor Latch Access Bit. 0x0
This bit is used to enable reading and writing of the Divisor
Latch register (DLL and DLH) to set the baud rate of the
UART.
This bit must be cleared after initial baud rate setup in order
to access other registers.

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Table 159: UART2_LCR_REG (0x5000110C)

6 R/W UART_BC Break Control Bit. 0x0
This is used to cause a break condition to be transmitted to
the receiving device. If set to one the serial output is forced
to the spacing (logic 0) state. When not in Loopback Mode,
as determined by MCR[4], the sout line is forced low until the
Break bit is cleared. If active (MCR[6] set to one) the
sir_out_n line is continuously pulsed. When in Loopback
Mode, the break condition is internally looped back to the
receiver and the sir_out_n line is forced low.
5 - - Reserved 0x0
4 R/W UART_EPS Even Parity Select. 0x0
This is used to select between even and odd parity, when
parity is enabled (PEN set to one). If set to one, an even
number of logic 1s is transmitted or checked. If set to zero,
an odd number of logic 1s is transmitted or checked.
3 R/W UART_PEN Parity Enable. 0x0
This bit is used to enable and disable parity generation and
detection in transmitted and received serial character
respectively.
0 = parity disabled
1 = parity enabled
2 R/W UART_STOP Number of stop bits. 0x0
This is used to select the number of stop bits per character
that the peripheral transmits and receives. If set to zero, one
stop bit is transmitted in the serial data.
If set to one and the data bits are set to 5 (LCR[1:0] set to
zero) one and a half stop bits is transmitted. Otherwise, two
stop bits are transmitted. Note that regardless of the number
of stop bits selected, the receiver checks only the first stop
bit.
0 = 1 stop bit
1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
1:0 R/W UART_DLS Data Length Select. 0x0
This is used to select the number of data bits per character
that the peripheral transmits and receives. The number of bit
that may be selected areas follows:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Table 160: UART2_MCR_REG (0x50001110)

6 R/W UART_SIRE SIR Mode Enable. 0x0
This is used to enable/disable the IrDA SIR Mode features
as described in "IrDA 1.0 SIR Protocol" on page 53.
0 = IrDA SIR Mode disabled
1 = IrDA SIR Mode enabled
5 R/W UART_AFCE Auto Flow Control Enable. 0x0
When FIFOs are enabled and the Auto Flow Control Enable
(AFCE) bit is set, hardware Auto Flow Control is enabled via
CTS and RTS.
0 = Auto Flow Control Mode disabled
1 = Auto Flow Control Mode enabled
DA14580
Table 160: UART2_MCR_REG (0x50001110)

4 R/W UART_LB LoopBack Bit. 0x0
This is used to put the UART into a diagnostic mode for test
purposes.
If operating in UART mode (SIR_MODE not active, MCR[6]
set to zero), data on the sout line is held high, while serial
data output is looped back to the sin line, internally. In this
mode all the interrupts are fully functional. Also, in loopback
mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n)
are disconnected and the modem control outputs (dtr_n,
rts_n, out1_n, out2_n) are looped back to the inputs, inter-
nally.
If operating in infrared mode (SIR_MODE active, MCR[6] set
to one), data on the sir_out_n line is held low, while serial
data output is inverted and looped back to the sir_in line.
1 R/W UART_RTS Request to Send. 0x0
This is used to directly control the Request to Send (rts_n)
output. The Request To Send (rts_n) output is used to inform
the modem or data set that the UART is ready to exchange
data.
When Auto Flow Control is disabled (MCR[5] set to zero),
the rts_n signal is set low by programming MCR[1] (RTS) to
a high. When Auto Flow Control is enabled (MCR[5] set to
one) and FIFOs are enabled (FCR[0] set to one), the rts_n
output is controlled in the same way, but is also gated with
the receiver FIFO threshold trigger (rts_n is inactive high
when above the threshold). The rts_n signal is de-asserted
when MCR[1] is set low.
Note that in Loopback mode (MCR[4] set to one), the rts_n
output is held inactive (high) while the value of this location is
0 - - Reserved 0x0
Table 161: UART2_LSR_REG (0x50001114)


DA14580

7 R UART_RFE Receiver FIFO Error bit. 0x0
This bit is only relevant when FIFOs are enabled (FCR[0] set
to one). This is used to indicate if there is at least one parity
error, framing error, or break indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the LSR is read and the character
with the error is at the top of the receiver FIFO and there are
no subsequent errors in the FIFO.
6 R UART_TEMT Transmitter Empty bit. 0x1
If FIFOs enabled (FCR[0] set to one), this bit is set whenever
the Transmitter Shift Register and the FIFO are both empty.
If FIFOs are disabled, this bit is set whenever the Transmitter
Holding Register and the Transmitter Shift Register are both
empty.
5 R UART_THRE Transmit Holding Register Empty bit. 0x1
If THRE mode is disabled (IER[7] set to zero) and regardless
of FIFO's being implemented/enabled or not, this bit indi-
cates that the THR or TX FIFO is empty.
This bit is set whenever data is transferred from the THR or
TX FIFO to the transmitter shift register and no new data has
been written to the THR or TX FIFO. This also causes a
THRE Interrupt to occur, if the THRE Interrupt is enabled. If
both modes are active (IER[7] set to one and FCR[0] set to
one respectively), the functionality is switched to indicate the
transmitter FIFO is full, and no longer controls THRE inter-
rupts, which are then controlled by the FCR[5:4] threshold
setting.
4 R UART_B1 Break Interrupt bit. 0x0
This is used to indicate the detection of a break sequence on
the serial input data.
If in UART mode (SIR_MODE == Disabled), it is set when-
ever the serial input, sin, is held in a logic '0' state for longer
than the sum of start time + data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set when-
ever the serial input, sir_in, is continuously pulsed to logic '0'
for longer than the sum of start time + data bits + parity +
stop bits. A break condition on serial input causes one and
only one character, consisting of all zeros, to be received by
the UART.
In the FIFO mode, the character associated with the break
condition is carried through the FIFO and is revealed when
the character is at the top of the FIFO.
Reading the LSR clears the BI bit. In the non-FIFO mode,
the BI indication occurs immediately and persists until the
LSR is read.

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3 R UART_FE Framing Error bit. 0x0
This is used to indicate the occurrence of a framing error in
the receiver. A framing error occurs when the receiver does
not detect a valid STOP bit in the received data.
In the FIFO mode, since the framing error is associated with
a character received, it is revealed when the character with
the framing error is at the top of the FIFO.
When a framing error occurs, the UART tries to resynchro-
nize. It does this by assuming that the error was due to the
start bit of the next character and then continues receiving
the other bit i.e. data, and/or parity and stop. It should be
noted that the Framing Error (FE) bit (LSR[3]) is set if a
break interrupt has occurred, as indicated by Break Interrupt
(BI) bit (LSR[4]).
0 = no framing error
1 = framing error
Reading the LSR clears the FE bit.
2 R UART_PE Parity Error bit. 0x0
This is used to indicate the occurrence of a parity error in the
receiver if the Parity Enable (PEN) bit (LCR[3]) is set.
In the FIFO mode, since the parity error is associated with a
character received, it is revealed when the character with the
parity error arrives at the top of the FIFO.
It should be noted that the Parity Error (PE) bit (LSR[2]) is
set if a break interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
Reading the LSR clears the PE bit.
1 R UART_OE Overrun error bit. 0x0
This is used to indicate the occurrence of an overrun error.
This occurs if a new data character was received before the
previous data was read.
In the non-FIFO mode, the OE bit is set when a new charac-
ter arrives in the receiver before the previous character was
read from the RBR. When this happens, the data in the RBR
is overwritten. In the FIFO mode, an overrun error occurs
when the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the data in the
receive shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.
0 R UART_DR Data Ready bit. 0x0
This is used to indicate that the receiver contains at least
one character in the RBR or the receiver FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-FIFO mode,
or when the receiver FIFO is empty, in FIFO mode.
Table 162: UART2_MSR_REG (0x50001118)


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7 R UART_DCD Data Carrier Detect. 0x0
trol line dcd_n. This bit is the complement of dcd_n. When
the Data Carrier Detect input (dcd_n) is asserted it is an indi-
cation that the carrier has been detected by the modem or
data set.
0 = dcd_n input is de-asserted (logic 1)
1 = dcd_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DCD is the same as
MCR[3] (Out2).
6 R UART_R1 Ring Indicator. 0x0
trol line ri_n. This bit is the complement of ri_n. When the
Ring Indicator input (ri_n) is asserted it is an indication that a
telephone ringing signal has been received by the modem or
data set.
0 = ri_n input is de-asserted (logic 1)
1 = ri_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), RI is the same as
MCR[2] (Out1).
5 - - Reserved 0x0
4 R UART_CTS Clear to Send. 0x0
trol line cts_n. This bit is the complement of cts_n. When the
Clear to Send input (cts_n) is asserted it is an indication that
the modem or data set is ready to exchange data with the
UART Ctrl.
0 = cts_n input is de-asserted (logic 1)
1 = cts_n input is asserted (logic 0)
In Loopback Mode (MCR[4] = 1), CTS is the same as
MCR[1] (RTS).
3 R UART_DDCD Delta Data Carrier Detect. 0x0
This is used to indicate that the modem control line dcd_n
0 = no change on dcd_n since last read of MSR
1 = change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit. In Loopback Mode
(MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2).
Note, if the DDCD bit is not set and the dcd_n signal is
then the DDCD bit is set when the reset is removed if the
dcd_n signal remains asserted.
2 R UART_TERI Trailing Edge of Ring Indicator. 0x0
This is used to indicate that a change on the input ri_n (from
an active-low to an inactive-high state) has occurred since
the last time the MSR was read.
0 = no change on ri_n since last read of MSR
1 = change on ri_n since last read of MSR
Reading the MSR clears the TERI bit. In Loopback Mode
(MCR[4] = 1), TERI reflects when MCR[2] (Out1) has
changed state from a high to a low.
1 - - Reserved 0x0

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0 R UART_DCTS Delta Clear to Send. 0x0
This is used to indicate that the modem control line cts_n
0 = no change on cts_n since last read of MSR
1 = change on cts_n since last read of MSR
Reading the MSR clears the DCTS bit. In Loopback Mode
(MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).
Note, if the DCTS bit is not set and the cts_n signal is
then the DCTS bit is set when the reset is removed if the
cts_n signal remains asserted.
Table 163: UART2_SCR_REG (0x5000111C)

7:0 R/W UART_SCRATCH_P This register is for programmers to use as a temporary stor- 0x0
AD age space. It has no defined purpose in the UART Ctrl.
Table 164: UART2_LPDLL_REG (0x50001120)

7:0 R/W UART_LPDLL This register makes up the lower 8-bits of a 16-bit, read/ 0x0
115.2K.
tion) occurs at the receiver. Also, once the LPDLL is set, at
data.
Table 165: UART2_LPDLH_REG (0x50001124)


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Table 165: UART2_LPDLH_REG (0x50001124)

7:0 R/W UART_LPDLH This register makes up the upper 8-bits of a 16-bit, read/ 0x0
115.2K.
tion) occurs at the receiver. Also, once the LPDLH is set, at
data.
Table 166: UART2_SRBR_STHR0_REG (0x50001130)

lost.

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lost.


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lost.
Table 169: UART2_SRBR_STHR3_REG (0x5000113C)


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.


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lost.
Table 182: UART2_USR_REG (0x5000117C)

4 R UART_RFF Receive FIFO Full. 0x0
This is used to indicate that the receive FIFO is completely
full.
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.
3 R UART_RFNE Receive FIFO Not Empty. 0x0
This is used to indicate that the receive FIFO contains one or
more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
2 R UART_TFE Transmit FIFO Empty. 0x1
This is used to indicate that the transmit FIFO is completely
empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.

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Table 182: UART2_USR_REG (0x5000117C)

1 R UART_TFNF Transmit FIFO Not Full. 0x1
This is used to indicate that the transmit FIFO in not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0 - - Reserved 0x0
Table 183: UART2_TFL_REG (0x50001180)

15:0 R UART_TRANSMIT_F Transmit FIFO Level. 0x0
IFO_LEVEL This is indicates the number of data entries in the transmit
FIFO.
Table 184: UART2_RFL_REG (0x50001184)

15:0 R UART_RECEIVE_FI Receive FIFO Level. 0x0
FO_LEVEL This is indicates the number of data entries in the receive
FIFO.
Table 185: UART2_SRR_REG (0x50001188)

2 W UART_XFR XMIT FIFO Reset. 0x0
This is a shadow register for the XMIT FIFO Reset bit
are pretty static) just to reset the transmit FIFO. This resets
the control portion of the transmit FIFO and treats the FIFO
as empty. Note that this bit is 'self-clearing'. It is not neces-
sary to clear this bit.
1 W UART_RFR RCVR FIFO Reset. 0x0
This is a shadow register for the RCVR FIFO Reset bit
are pretty static) just to reset the receive FIFO This resets
the control portion of the receive FIFO and treats the FIFO
as empty.
Note that this bit is 'self-clearing'. It is not necessary to clear
this bit.
0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and 0x0
synchronously removes the reset assertion. For a two clock
implementation both pclk and sclk domains are reset.
Table 186: UART2_SRTS_REG (0x5000118C)


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Table 186: UART2_SRTS_REG (0x5000118C)

0 R/W UART_SHADOW_R Shadow Request to Send. 0x0
EQUEST_TO_SEND This is a shadow register for the RTS bit (MCR[1]), this can
be used to remove the burden of having to perform a read-
modify-write on the MCR. This is used to directly control the
Request to Send (rts_n) output. The Request To Send
(rts_n) output is used to inform the modem or data set that
the UART Ctrl is ready to exchange data.
When Auto Flow Control is disabled (MCR[5] = 0), the rts_n
signal is set low by programming MCR[1] (RTS) to a high.
When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs
are enabled (FCR[0] = 1), the rts_n output is controlled in the
same way, but is also gated with the receiver FIFO threshold
trigger (rts_n is inactive high when above the threshold).
Note that in Loopback mode (MCR[4] = 1), the rts_n output is
held inactive-high while the value of this location is internally
looped back to an input.
Table 187: UART2_SBCR_REG (0x50001190)

0 R/W UART_SHADOW_B Shadow Break Control Bit. 0x0
REAK_CONTROL This is a shadow register for the Break bit (LCR[6]), this can
be used to remove the burden of having to performing a read
modify write on the LCR. This is used to cause a break con-
dition to be transmitted to the receiving device.
If set to one the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined by
MCR[4], the sout line is forced low until the Break bit is
cleared.
If SIR_MODE active (MCR[6] = 1) the sir_out_n line is con-
tinuously pulsed. When in Loopback Mode, the break condi-
tion is internally looped back to the receiver.
Table 188: UART2_SDMAM_REG (0x50001194)

0 R/W UART_SHADOW_D Shadow DMA Mode. 0x0
MA_MODE This is a shadow register for the DMA mode bit (FCR[3]).
mask this value so that only the DMA Mode bit gets updated.
This determines the DMA signalling mode used for the
dma_tx_req_n and dma_rx_req_n output signals.
0 = mode 0
1 = mode 1
Table 189: UART2_SFE_REG (0x50001198)


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Table 189: UART2_SFE_REG (0x50001198)

0 R/W UART_SHADOW_FI Shadow FIFO Enable. 0x0
FO_ENABLE This is a shadow register for the FIFO enable bit (FCR[0]).
mask this value so that only the FIFO enable bit gets
updated.This enables/disables the transmit (XMIT) and
receive (RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR controller
portion of FIFOs are reset.
Table 190: UART2_SRT_REG (0x5000119C)

1:0 R/W UART_SHADOW_R Shadow RCVR Trigger. 0x0
CVR_TRIGGER This is a shadow register for the RCVR trigger bits
and having to mask this value so that only the RCVR trigger
bit gets updated.
This is used to select the trigger level in the receiver FIFO at
which the Received Data Available Interrupt is generated. It
also determines when the dma_rx_req_n signal is asserted
when DMA Mode (FCR[3]) = 1. The following trigger levels
are supported:
00 = 1 character in the FIFO
01 = FIFO Â¼ full
10 = FIFO Â½ full
11 = FIFO 2 less than full
Table 191: UART2_STET_REG (0x500011A0)

1:0 R/W UART_SHADOW_TX Shadow TX Empty Trigger. 0x0
_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits
and having to mask this value so that only the TX empty trig-
ger bit gets updated.
This is used to select the empty threshold level at which the
THRE Interrupts are generated when the mode is active.
The following trigger levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO Â¼ full
11 = FIFO Â½ full
Table 192: UART2_HTX_REG (0x500011A4)


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Table 192: UART2_HTX_REG (0x500011A4)

0 R/W UART_HALT_TX This register is use to halt transmissions for testing, so that 0x0
the transmit FIFO can be filled by the master when FIFOs
are implemented and enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled, the setting
of the halt TX register has no effect on operation.
Table 193: UART2_CPR_REG (0x500011F4)

15:0 R CPR Component Parameter Register 0x0
Table 194: UART2_UCV_REG (0x500011F8)

15:0 R UCV Component Version 0x33303
82A
Table 195: UART2_CTR_REG (0x500011FC)

15:0 R CTR Component Type Register 0x44570
110
Table 196: SPI_CTRL_REG (0x50001200)

15 R/W SPI_EN_CTRL 0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't 0x0
care.
1 = SPI_EN pin enabled in slave mode.
14 R/W SPI_MINT 0 = Disable SPI_INT_BIT to the Interrupt Controller 0x0
1 = Enable SPI_INT_BIT to the Interrupt Controller
13 R SPI_INT_BIT 0 = RX Register or FIFO is empty. 0x0
1 = SPI interrupt. Data has been transmitted and received-
Must be reset by SW by writing to SPI_CLEAR_INT_REG.
12 R SPI_DI Returns the actual value of pin SPI_DIN (delayed with two 0x0
internal SPI clock cycles)
11 R SPI_TXH 0 = TX-FIFO is not full, data can be written. 0x0
1 = TX-FIFO is full, data can not be written.
10 R/W SPI_FORCE_DO 0 = normal operation 0x0
1 = Force SPIDO output level to value of SPI_DO.
9 R/W SPI_RST 0 = normal operation 0x0
1 = Reset SPI. Same function as SPI_ON except that inter-
nal clock remain active.
8:7 R/W SPI_WORD 00 = 8 bits mode, only SPI_RX_TX_REG0 used 0x0
01 = 16 bit mode, only SPI_RX_TX_REG0 used
10 = 32 bits mode, SPI_RX_TX_REG0 &
SPI_RX_TX_REG1 used
11 = 9 bits mode. Only valid in master mode.

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Table 196: SPI_CTRL_REG (0x50001200)

6 R/W SPI_SMN Master/slave mode 0x0
0 = Master,
1 = Slave(SPI1 only)
5 R/W SPI_DO Pin SPI_DO output level when SPI is idle or when 0x0
SPI_FORCE_DO=1
4:3 R/W SPI_CLK Select SPI_CLK clock frequency in master mode:00 = 0x0
(XTAL) / (CLK_PER_REG *8)
01 = (XTAL) / (CLK_PER_REG *4)
2 R/W SPI_POL Select SPI_CLK polarity. 0x0
0 = SPI_CLK is initially low.
1 = SPI_CLK is initially high.
1 R/W SPI_PHA Select SPI_CLK phase. See functional timing diagrams in 0x0
SPI chapter
0 R/W SPI_ON 0 = SPI Module switched off (power saving). Everything is 0x0
reset except SPI_CTRL_REG0 and SPI_CTRL_REG1.
When this bit is cleared the SPI will remain active in master
mode until the shift register and holding register are both
empty.
1 = SPI Module switched on. Should only be set after all con-
trol bits have their desired values. So two writes are needed!
Table 197: SPI_RX_TX_REG0 (0x50001202)

15:0 R0/W SPI_DATA0 Write: SPI_TX_REG0 output register 0 (TX-FIFO) 0x0
Read: SPI_RX_REG0 input register 0 (RX-FIFO)
In 8 or 9 bits mode bits 15 to 8 are not used, they contain old
data.
Table 198: SPI_RX_TX_REG1 (0x50001204)

15:0 R0/W SPI_DATA1 Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) 0x0
Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO)
In 8 or 9 or 16 bits mode bits this register is not used.
Table 199: SPI_CLEAR_INT_REG (0x50001206)

15:0 R0/W SPI_CLEAR_INT Writing any value to this register will clear the 0x0
SPI_CTRL_REG[SPI_INT_BIT]
Reading returns 0.
Table 200: SPI_CTRL_REG1 (0x50001208)

4 R/W SPI_9BIT_VAL Determines the value of the first bit in 9 bits SPI mode. 0x0

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Table 200: SPI_CTRL_REG1 (0x50001208)

3 R SPI_BUSY 0 = The SPI is not busy with a transfer. This means that 0x0
either no TX-data is available or that the transfers have been
suspended due to a full RX-FIFO. The
SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish
between these situations.
1 = The SPI is busy with a transfer.
2 R/W SPI_PRIORITY 0 = The SPI has low priority, the DMA request signals are 0x0
reset after the corresponding acknowledge.
1 = The SPI has high priority, DMA request signals remain
active until the FIFOS are filled/emptied, so the DMA holds
the AHB bus.
1:0 R/W SPI_FIFO_MODE 0: TX-FIFO and RX-FIFO used (Bidirectional mode). 0x3
1: RX-FIFO used (Read Only Mode) TX-FIFO single depth,
no flow control
2: TX-FIFO used (Write Only Mode), RX-FIFO single depth,
no flow control
3: No FIFOs used (backwards compatible mode)
Table 201: I2C_CON_REG (0x50001300)

6 R/W I2C_SLAVE_DISABL Slave enabled or disabled after reset is applied, which 0x1
E means software does not have to configure the slave.
0=slave is enabled
1=slave is disabled
Software should ensure that if this bit is written with '0', then
bit 0 should also be written with a '0'.
5 R/W I2C_RESTART_EN Determines whether RESTART conditions may be sent 0x1
when acting as a master
0= disable
1=enable
4 R/W I2C_10BITADDR_MA Controls whether the controller starts its transfers in 7- or 10- 0x1
STER bit addressing mode when acting as a master.
0= 7-bit addressing
1= 10-bit addressing
3 R/W I2C_10BITADDR_SL When acting as a slave, this bit controls whether the control- 0x1
AVE ler responds to 7- or 10-bit addresses.
0= 7-bit addressing
1= 10-bit addressing
2:1 R/W I2C_SPEED These bits control at which speed the controller operates. 0x2
1= standard mode (100 kbit/s)
2= fast mode (400 kbit/s)
0 R/W I2C_MASTER_MOD This bit controls whether the controller master is enabled. 0x1
E 0= master disabled
1= master enabled
Software should ensure that if this bit is written with '1' then
bit 6 should also be written with a '1'.
Table 202: I2C_TAR_REG (0x50001304)


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Table 202: I2C_TAR_REG (0x50001304)

11 R/W SPECIAL This bit indicates whether software performs a General Call 0x0
or
START BYTE command.
0: ignore bit 10 GC_OR_START and use IC_TAR normally
1: perform special I2C command as specified in
GC_OR_START
bit
10 R/W GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether 0x0
a General Call or START byte command is to be performed
by the controller.
0: General Call Address - after issuing a General Call, only
writes may be performed. Attempting to issue a read com-
mand results in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register. The controller remains in
General Call mode until the SPECIAL bit value (bit 11) is
cleared.
1: START BYTE
9:0 R/W IC_TAR This is the target address for any master transaction. When 0x55
transmitting a General Call, these bits are ignored. To gener-
ate a START BYTE, the CPU needs to write only once into
these bits.
Note: If the IC_TAR and IC_SAR are the same, loopback
exists but the FIFOs are shared between master and slave,
so full loopback is not feasible. Only one direction loopback
mode is supported (simplex), not duplex. A master cannot
transmit to itself; it can transmit to only a slave
Table 203: I2C_SAR_REG (0x50001308)

9:0 R/W IC_SAR The IC_SAR holds the slave address when the I2C is operat- 0x55
ing as a slave. For 7-bit addressing, only IC_SAR[6:0] is
used. This register can be written only when the I2C inter-
face is disabled, which corresponds to the IC_ENABLE reg-
ister being set to 0. Writes at other times have no effect.
Table 204: I2C_DATA_CMD_REG (0x50001310)


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Table 204: I2C_DATA_CMD_REG (0x50001310)

8 R/W CMD This bit controls whether a read or a write is performed. This 0x0
bit does not control the direction when the I2C Ctrl acts as a
slave. It controls only the direction when it acts as a master.
1 = Read
0 = Write
When a command is entered in the TX FIFO, this bit distin-
guishes the write and read commands. In slave-receiver
mode, this bit is a "don't care" because writes to this register
are not required. In slave-transmitter mode, a "0" indicates
that CPU data is to be transmitted and as DAT or
IC_DATA_CMD[7:0]. When programming this bit, you should
remember the following: attempting to perform a read opera-
tion after a General Call command has been sent results in a
TX_ABRT interrupt (bit 6 of the
I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in
the I2C_TAR register has been cleared.
If a "1" is written to this bit after receiving a RD_REQ inter-
rupt, then a TX_ABRT interrupt occurs.
NOTE: It is possible that while attempting a master I2C read
transfer on the controller, a RD_REQ interrupt may have
occurred simultaneously due to a remote I2C master
addressing the controller. In this type of scenario, it ignores
the I2C_DATA_CMD write, generates a TX_ABRT interrupt,
and waits to service the RD_REQ interrupt
7:0 R/W DAT This register contains the data to be transmitted or received 0x0
on the I2C bus. If you are writing to this register and want to
perform a read, bits 7:0 (DAT) are ignored by the controller.
However, when you read this register, these bits return the
value of data received on the controller's interface.
Table 205: I2C_SS_SCL_HCNT_REG (0x50001314)

15:0 R/W IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can 0x48
take place to ensure proper I/O timing. This register sets the
SCL clock high-period count for standard speed. This regis-
ter can be written only when the I2C interface is disabled
which corresponds to the IC_ENABLE register being set to
0. Writes at other
times have no effect.
The minimum valid value is 6; hardware prevents values less
than this being written, and if attempted results in 6 being
set.
NOTE: This register must not be programmed to a value
higher than 65525, because the controller uses a 16-bit
counter to flag an I2C bus idle condition when this counter
reaches a value of IC_SS_SCL_HCNT + 10.

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Table 206: I2C_SS_SCL_LCNT_REG (0x50001318)

15:0 R/W IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can 0x4F
SCL clock low period count for standard speed.
This register can be written only when the I2C interface is
disabled which corresponds to the I2C_ENABLE register
being set to 0. Writes at other times have no effect.
than this being written, and if attempted, results in 8 being
set.
Table 207: I2C_FS_SCL_HCNT_REG (0x5000131C)

15:0 R/W IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can 0x8
SCL clock high-period count for fast speed. It is used in high-
speed mode to send the Master Code and START BYTE or
General CALL. This register can be written only when the
I2C interface is disabled, which corresponds to the
I2C_ENABLE register being set to 0. Writes at other times
have no effect.
set.
Table 208: I2C_FS_SCL_LCNT_REG (0x50001320)

15:0 R/W IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can 0x17
SCL clock low-period count for fast speed. It is used in high-
speed mode to send the Master Code and START BYTE or
General CALL. This register can be written only when the
I2C interface is disabled, which corresponds to the
I2C_ENABLE register being set to 0. Writes at other times
have no effect.
set. For designs with APB_DATA_WIDTH = 8 the order of
programming is important to ensure the correct operation of
the controller. The lower byte must be programmed first.
Then the upper byte is programmed.
Table 209: I2C_INTR_STAT_REG (0x5000132C)

11 R R_GEN_CALL Set only when a General Call address is received and it is 0x0
acknowledged. It stays set until it is cleared either by dis-
abling controller or when the CPU reads bit 0 of the
I2C_CLR_GEN_CALL register. The controller stores the
received data in the Rx buffer.

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10 R R_START_DET Indicates whether a START or RESTART condition has 0x0
occurred on the I2C interface regardless of whether control-
ler is operating in slave or master mode.
9 R R_STOP_DET Indicates whether a STOP condition has occurred on the I2C 0x0
interface regardless of whether controller is operating in
slave or master mode.
8 R R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is 0x0
cleared. There are four ways to clear it:
=> Disabling the I2C Ctrl
=> Reading the IC_CLR_ACTIVITY register
=> Reading the IC_CLR_INTR register
=> System reset
Once this bit is set, it stays set unless one of the four meth-
ods is used to clear it. Even if the controller module is idle,
this bit remains set until cleared, indicating that there was
activity on the bus.
7 R R_RX_DONE When the controller is acting as a slave-transmitter, this bit is 0x0
set to 1 if the master does not acknowledge a transmitted
byte. This occurs on the last byte of the transmission, indi-
cating that the transmission is done.
6 R R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is 0x0
unable to complete the intended actions on the contents of
the transmit FIFO. This situation can occur both as an I2C
master or an I2C slave, and is referred to as a "transmit
abort".
When this bit is set to 1, the I2C_TX_ABRT_SOURCE regis-
ter indicates the reason why the transmit abort takes places.
NOTE: The controller flushes/resets/empties the TX FIFO
whenever this bit is set. The TX FIFO remains in this flushed
state until the register I2C_CLR_TX_ABRT is read. Once
this read is performed, the TX FIFO is then ready to accept
more data bytes from the APB interface.
5 R R_RD_REQ This bit is set to 1 when the controller is acting as a slave 0x0
and another I2C master is attempting to read data from the
controller. The controller holds the I2C bus in a wait state
(SCL=0) until this interrupt is serviced, which means that the
slave has been addressed by a remote master that is asking
for data to be transferred. The processor must respond to
this interrupt and then write the requested data to the
I2C_DATA_CMD register. This bit is set to 0 just after the
processor reads the I2C_CLR_RD_REQ register
4 R R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the 0x0
threshold value set in the I2C_TX_TL register. It is automati-
cally cleared by hardware when the buffer level goes above
the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO
is flushed and held in reset. There the TX FIFO looks like it
has no data within it, so this bit is set to 1, provided there is
activity in the master or slave state machines. When there is
no longer activity, then with ic_en=0, this bit is set to 0.
3 R R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the 0x0
processor attempts to issue another I2C command by writing
to the IC_DATA_CMD register. When the module is disabled,
this bit keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0, this inter-
rupt is cleared

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2 R R_RX_FULL Set when the receive buffer reaches or goes above the 0x0
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
1 R R_RX_OVER Set if the receive buffer is completely filled to 32 and an addi- 0x0
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master
or slave state machines go into idle, and when ic_en goes to
0, this interrupt is cleared.
0 R R_RX_UNDER Set if the processor attempts to read the receive buffer when 0x0
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
Table 210: I2C_INTR_MASK_REG (0x50001330)

11 R/W M_GEN_CALL These bits mask their corresponding interrupt status bits in 0x1
the I2C_INTR_STAT register.
10 R/W M_START_DET These bits mask their corresponding interrupt status bits in 0x0
9 R/W M_STOP_DET These bits mask their corresponding interrupt status bits in 0x0
8 R/W M_ACTIVITY These bits mask their corresponding interrupt status bits in 0x0
7 R/W M_RX_DONE These bits mask their corresponding interrupt status bits in 0x1
6 R/W M_TX_ABRT These bits mask their corresponding interrupt status bits in 0x1
5 R/W M_RD_REQ These bits mask their corresponding interrupt status bits in 0x1
4 R/W M_TX_EMPTY These bits mask their corresponding interrupt status bits in 0x1
3 R/W M_TX_OVER These bits mask their corresponding interrupt status bits in 0x1
2 R/W M_RX_FULL These bits mask their corresponding interrupt status bits in 0x1
1 R/W M_RX_OVER These bits mask their corresponding interrupt status bits in 0x1
0 R/W M_RX_UNDER These bits mask their corresponding interrupt status bits in 0x1

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Table 211: I2C_RAW_INTR_STAT_REG (0x50001334)

11 R GEN_CALL Set only when a General Call address is received and it is 0x0
acknowledged. It stays set until it is cleared either by dis-
abling controller or when the CPU reads bit 0 of the
I2C_CLR_GEN_CALL register. I2C Ctrl stores the received
data in the Rx buffer.
10 R START_DET Indicates whether a START or RESTART condition has 0x0
occurred on the I2C interface regardless of whether control-
ler is operating in slave or master mode.
9 R STOP_DET Indicates whether a STOP condition has occurred on the I2C 0x0
interface regardless of whether controller is operating in
slave or master mode.
8 R ACTIVITY This bit captures I2C Ctrl activity and stays set until it is 0x0
cleared. There are four ways to clear it:
=> Disabling the I2C Ctrl
=> Reading the IC_CLR_ACTIVITY register
=> Reading the IC_CLR_INTR register
=> System reset
Once this bit is set, it stays set unless one of the four meth-
ods is used to clear it. Even if the controller module is idle,
this bit remains set until cleared, indicating that there was
activity on the bus.
7 R RX_DONE When the controller is acting as a slave-transmitter, this bit is 0x0
set to 1 if the master does not acknowledge a transmitted
byte. This occurs on the last byte of the transmission, indi-
cating that the transmission is done.
6 R TX_ABRT This bit indicates if the controller, as an I2C transmitter, is 0x0
unable to complete the intended actions on the contents of
the transmit FIFO. This situation can occur both as an I2C
master or an I2C slave, and is referred to as a "transmit
abort".
When this bit is set to 1, the I2C_TX_ABRT_SOURCE regis-
ter indicates the reason why the transmit abort takes places.
NOTE: The controller flushes/resets/empties the TX FIFO
whenever this bit is set. The TX FIFO remains in this flushed
state until the register I2C_CLR_TX_ABRT is read. Once
this read is performed, the TX FIFO is then ready to accept
more data bytes from the APB interface.
5 R RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and 0x0
another I2C master is attempting to read data from the con-
troller. The controller holds the I2C bus in a wait state
(SCL=0) until this interrupt is serviced, which means that the
slave has been addressed by a remote master that is asking
for data to be transferred. The processor must respond to
this interrupt and then write the requested data to the
I2C_DATA_CMD register. This bit is set to 0 just after the
processor reads the I2C_CLR_RD_REQ register
4 R TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the 0x0
threshold value set in the I2C_TX_TL register. It is automati-
cally cleared by hardware when the buffer level goes above
the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO
is flushed and held in reset. There the TX FIFO looks like it
has no data within it, so this bit is set to 1, provided there is
activity in the master or slave state machines. When there is
no longer activity, then with ic_en=0, this bit is set to 0.

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Table 211: I2C_RAW_INTR_STAT_REG (0x50001334)

3 R TX_OVER Set during transmit if the transmit buffer is filled to 32 and the 0x0
processor attempts to issue another I2C command by writing
to the IC_DATA_CMD register. When the module is disabled,
this bit keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0, this inter-
rupt is cleared
2 R RX_FULL Set when the receive buffer reaches or goes above the 0x0
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
1 R RX_OVER Set if the receive buffer is completely filled to 32 and an addi- 0x0
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master
or slave state machines go into idle, and when ic_en goes to
0, this interrupt is cleared.
0 R RX_UNDER Set if the processor attempts to read the receive buffer when 0x0
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
Table 212: I2C_RX_TL_REG (0x50001338)

4:0 R/W RX_TL Receive FIFO Threshold Level Controls the level of entries 0x0
(or above) that triggers the RX_FULL interrupt (bit 2 in
I2C_RAW_INTR_STAT register). The valid range is 0-31,
with the additional restriction that hardware does not allow
this value to be set to a value larger than the depth of the
buffer. If an attempt is made to do that, the actual value set
will be the maximum depth of the buffer. A value of 0 sets the
threshold for 1 entry, and a value of 31 sets the threshold for
32 entries.
Table 213: I2C_TX_TL_REG (0x5000133C)

4:0 R/W RX_TL Transmit FIFO Threshold Level Controls the level of entries 0x0
(or below) that trigger the TX_EMPTY interrupt (bit 4 in
I2C_RAW_INTR_STAT register). The valid range is 0-31,
with the additional restriction that it may not be set to value
larger than the depth of the buffer. If an attempt is made to
do that, the actual value set will be the maximum depth of
the buffer. A value of 0 sets the threshold for 0 entries, and a
value of 31 sets the threshold for 32 entries..

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Table 214: I2C_CLR_INTR_REG (0x50001340)

0 R CLR_INTR Read this register to clear the combined interrupt, all individ- 0x0
ual interrupts, and the I2C_TX_ABRT_SOURCE register.
This bit does not clear hardware clearable interrupts but soft-
ware clearable interrupts. Refer to Bit 9 of the
I2C_TX_ABRT_SOURCE register for an exception to clear-
ing I2C_TX_ABRT_SOURCE
Table 215: I2C_CLR_RX_UNDER_REG (0x50001344)

0 R CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of 0x0
the
Table 216: I2C_CLR_RX_OVER_REG (0x50001348)

0 R CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of 0x0
the
Table 217: I2C_CLR_TX_OVER_REG (0x5000134C)

0 R CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of 0x0
the I2C_RAW_INTR_STAT register.
Table 218: I2C_CLR_RD_REQ_REG (0x50001350)

0 R CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of 0x0
the I2C_RAW_INTR_STAT register.
Table 219: I2C_CLR_TX_ABRT_REG (0x50001354)

0 R CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of 0x0
the
IC_RAW_INTR_STAT register, and the
I2C_TX_ABRT_SOURCE register. This also releases the TX
FIFO from the flushed/reset state, allowing more writes to
the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE
register for an exception to clearing
IC_TX_ABRT_SOURCE.

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Table 220: I2C_CLR_RX_DONE_REG (0x50001358)

0 R CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of 0x0
the
Table 221: I2C_CLR_ACTIVITY_REG (0x5000135C)

0 R CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C 0x0
is not active anymore. If the I2C module is still active on the
bus, the ACTIVITY interrupt bit continues to be set. It is auto-
matically cleared by hardware if the module is disabled and if
there is no further activity on the bus. The value read from
this register to get status of the ACTIVITY interrupt (bit 8) of
the IC_RAW_INTR_STAT register
Table 222: I2C_CLR_STOP_DET_REG (0x50001360)

0 R CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C 0x0
is not active anymore. If the I2C module is still active on the
bus, the ACTIVITY interrupt bit continues to be set. It is auto-
matically cleared by hardware if the module is disabled and if
there is no further activity on the bus. The value read from
this register to get status of the ACTIVITY interrupt (bit 8) of
the IC_RAW_INTR_STAT register.
Table 223: I2C_CLR_START_DET_REG (0x50001364)

0 R CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) 0x0
of the IC_RAW_INTR_STAT register.
Table 224: I2C_CLR_GEN_CALL_REG (0x50001368)

0 R CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of 0x0
Table 225: I2C_ENABLE_REG (0x5000136C)


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Table 225: I2C_ENABLE_REG (0x5000136C)

0 R/W CTRL_ENABLE Controls whether the controller is enabled. 0x0
0: Disables the controller (TX and RX FIFOs are held in an
erased state)
1: Enables the controller
Software can disable the controller while it is active. How-
ever, it is important that care be taken to ensure that the con-
troller is disabled properly. When the controller is disabled,
the following occurs:
* The TX FIFO and RX FIFO get flushed.
* Status bits in the IC_INTR_STAT register are still active
until the controller goes into IDLE state.
If the module is transmitting, it stops as well as deletes the
contents of the transmit buffer after the current transfer is
complete. If the module is receiving, the controller stops the
current transfer at the end of the current byte and does not
acknowledge the transfer.
There is a two ic_clk delay when enabling or disabling the
controller
Table 226: I2C_STATUS_REG (0x50001370)

6 R SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State 0x0
Machine (FSM) is not in the IDLE state, this bit is set.
0: Slave FSM is in IDLE state so the Slave part of the con-
troller is not Active
1: Slave FSM is not in IDLE state so the Slave part of the
controller is Active
5 R MST_ACTIVITY Master FSM Activity Status. When the Master Finite State 0x0
Machine (FSM) is not in the IDLE state, this bit is set.
0: Master FSM is in IDLE state so the Master part of the con-
troller is not Active
1: Master FSM is not in IDLE state so the Master part of the
controller is Active
4 R RFF Receive FIFO Completely Full. When the receive FIFO is 0x0
completely full, this bit is set. When the receive FIFO con-
tains one or more empty location, this bit is cleared.
0: Receive FIFO is not full
1: Receive FIFO is full
3 R RFNE Receive FIFO Not Empty. This bit is set when the receive 0x0
FIFO contains one or more entries; it is cleared when the
receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty
2 R TFE Transmit FIFO Completely Empty. When the transmit FIFO is 0x1
completely empty, this bit is set. When it contains one or
more valid entries, this bit is cleared. This bit field does not
request an interrupt.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
1 R TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains 0x1
one or more empty locations, and is cleared when the FIFO
is full.
0: Transmit FIFO is full
1: Transmit FIFO is not full

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Table 226: I2C_STATUS_REG (0x50001370)

0 R I2C_ACTIVITY I2C Activity Status. 0x0
Table 227: I2C_TXFLR_REG (0x50001374)

5:0 R TXFLR Transmit FIFO Level. Contains the number of valid data 0x0
entries in the transmit FIFO. Size is constrained by the
TXFLR value
Table 228: I2C_RXFLR_REG (0x50001378)

5:0 R RXFLR Receive FIFO Level. Contains the number of valid data 0x0
entries in the receive FIFO. Size is constrained by the
RXFLR value
Table 229: I2C_SDA_HOLD_REG (0x5000137C)

15:0 R/W IC_SDA_HOLD SDA Hold time 0x1
Table 230: I2C_TX_ABRT_SOURCE_REG (0x50001380)

15 R ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode 0x0
request for data to be transmitted to a remote master and
user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register
14 R ABRT_SLV_ARBLOS 1: Slave lost the bus while transmitting data to a remote 0x0
T master.
I2C_TX_ABRT_SOURCE[12] is set at the same time. Note:
Even though the slave never "owns" the bus, something
could go wrong on the bus. This is a fail safe check. For
instance, during a data transmission at the low-to-high tran-
sition of SCL, if what is on the data bus is not what is sup-
posed to be transmitted, then the controller no longer own
the bus.
13 R ABRT_SLVFLUSH_T 1: Slave has received a read command and some data 0x0
XFIFO exists in the TX FIFO so the slave issues a TX_ABRT inter-
rupt to flush old data in TX FIFO.
12 R ARB_LOST 1: Master has lost arbitration, or if 0x0
I2C_TX_ABRT_SOURCE[14] is also set, then the slave
transmitter has lost arbitration. Note: I2C can be both master
and slave at the same time.
11 R ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master 0x0
mode disabled.
10 R ABRT_10B_RD_NO 1: The restart is disabled (IC_RESTART_EN bit 0x0
RSTRT (I2C_CON[5]) = 0) and the master sends a read command in
10-bit addressing mode.

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Table 230: I2C_TX_ABRT_SOURCE_REG (0x50001380)

9 R ABRT_SBYTE_NOR To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT 0x0
STRT must be fixed first; restart must be enabled (I2C_CON[5]=1),
the SPECIAL bit must be cleared (I2C_TAR[11]), or the
GC_OR_START bit must be cleared (I2C_TAR[10]). Once
the source of the ABRT_SBYTE_NORSTRT is fixed, then
this bit can be cleared in the same manner as other bits in
this register. If the source of the ABRT_SBYTE_NORSTRT
is not fixed before attempting to clear this bit, bit 9 clears for
one cycle and then gets re-asserted. 1: The restart is dis-
abled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user
is trying to send a START Byte.
8 R ABRT_HS_NORSTR 1: The restart is disabled (IC_RESTART_EN bit 0x0
T (I2C_CON[5]) = 0) and the user is trying to use the master to
transfer data in High Speed mode
7 R ABRT_SBYTE_ACK 1: Master has sent a START Byte and the START Byte was 0x0
DET acknowledged (wrong behavior).
6 R ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master 0x0
code was acknowledged (wrong behavior).
5 R ABRT_GCALL_REA 1: the controller in master mode sent a General Call but the 0x0
D user programmed the byte following the General Call to be a
read from the bus (IC_DATA_CMD[9] is set to 1).
4 R ABRT_GCALL_NOA 1: the controller in master mode sent a General Call and no 0x0
CK slave on the bus acknowledged the General Call.
3 R ABRT_TXDATA_NO 1: This is a master-mode only bit. Master has received an 0x0
ACK acknowledgement for the address, but when it sent data
byte(s) following the address, it did not receive an acknowl-
edge from the remote slave(s).
2 R ABRT_10ADDR2_N 1: Master is in 10-bit address mode and the second address 0x0
OACK byte of the 10-bit address was not acknowledged by any
slave.
1 R ABRT_10ADDR1_N 1: Master is in 10-bit address mode and the first 10-bit 0x0
OACK address byte was not acknowledged by any slave.
0 R ABRT_7B_ADDR_N 1: Master is in 7-bit addressing mode and the address sent 0x0
OACK was not acknowledged by any slave.
Table 231: I2C_SDA_SETUP_REG (0x50001394)

7:0 R/W SDA_SETUP SDA Setup. 0x64
This register controls the amount of time delay (number of
I2C clock periods) between the rising edge of SCL and SDA
changing by holding SCL low when I2C block services a
read request while operating as a slave-transmitter. The rele-
vant I2C requirement is tSU:DAT (note 4) as detailed in the
I2C Bus Specification. This register must be programmed
with a value equal to or greater than 2.
It is recommended that if the required delay is 1000ns, then
for an I2C frequency of 10 MHz, IC_SDA_SETUP should be
programmed to a value of 11.Writes to this register succeed
only when IC_ENABLE[0] = 0.

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Table 232: I2C_ACK_GENERAL_CALL_REG (0x50001398)

0 R/W ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl responds with a 0x0
ACK (by asserting ic_data_oe) when it receives a General
Call. When set to 0, the controller does not generate General
Call interrupts.
Table 233: I2C_ENABLE_STATUS_REG (0x5000139C)

2 R SLV_RX_DATA_LOS Slave Received Data Lost. This bit indicates if a Slave- 0x0
T Receiver
operation has been aborted with at least one data byte
received from an I2C transfer due to the setting of
IC_ENABLE from 1 to 0. When read as 1, the controller is
deemed to have been actively engaged in an aborted I2C
transfer (with matching address) and the data phase of the
I2C transfer has been entered, even though a data byte has
been responded with a NACK. NOTE: If the remote I2C mas-
ter terminates the transfer with a STOP condition before the
controller has a chance to NACK a transfer, and IC_ENABLE
has been set to 0, then this bit is also set to 1.
When read as 0, the controller is deemed to have been dis-
abled without being actively involved in the data phase of a
Slave-Receiver transfer.
NOTE: The CPU can safely read this bit when IC_EN (bit 0)
is read as 0.
1 R SLV_DISABLED_WH Slave Disabled While Busy (Transmit, Receive). This bit indi- 0x0
ILE_BUSY cates if a potential or active Slave operation has been
aborted due to the setting of the IC_ENABLE register from 1
to 0. This bit is set when the CPU writes a 0 to the
IC_ENABLE register while:
(a) I2C Ctrl is receiving the address byte of the Slave-Trans-
mitter operation from a remote master; OR,
(b) address and data bytes of the Slave-Receiver operation
from a remote master. When read as 1, the controller is
deemed to have forced a NACK during any part of an I2C
transfer, irrespective of whether the I2C address matches
the slave address set in I2C Ctrl (IC_SAR register) OR if the
transfer is completed before IC_ENABLE is set to 0 but has
not taken effect.
NOTE: If the remote I2C master terminates the transfer with
a STOP condition before the the controller has a chance to
NACK a transfer, and IC_ENABLE has been set to 0, then
this bit will also be set to 1.
When read as 0, the controller is deemed to have been dis-
abled when there is master activity, or when the I2C bus is
idle.
NOTE: The CPU can safely read this bit when IC_EN (bit 0)
is read as 0.

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Table 233: I2C_ENABLE_STATUS_REG (0x5000139C)

0 R IC_EN ic_en Status. This bit always reflects the value driven on the 0x0
output port ic_en. When read as 1, the controller is deemed
to be in an enabled state.
When read as 0, the controller is deemed completely inac-
tive.
NOTE: The CPU can safely read this bit anytime. When this
bit is read as 0, the CPU can safely read
SLV_RX_DATA_LOST (bit 2) and
SLV_DISABLED_WHILE_BUSY (bit 1).
Table 234: I2C_IC_FS_SPKLEN_REG (0x500013A0)

7:0 R/W IC_FS_SPKLEN This register must be set before any I2C bus transaction can 0x1
take place to ensure stable operation. This register sets the
duration, measured in ic_clk cycles, of the longest spike in
the SCL or SDA lines that will be filtered out by the spike
suppression logic. This register can be written only when the
I2C interface is disabled which corresponds to the
IC_ENABLE register being set to 0. Writes at other times
have no effect. The minimum valid value is 2; hardware pre-
vents values less than this being written, and if attempted
results in 2 being set.
Table 235: GPIO_IRQ0_IN_SEL_REG (0x50001400)


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5:0 R/W KBRD_IRQ0_SEL input selection that can generate a GPIO interrupt 0x0
0: no input selected
1: P0[0] is selected
all others: no input selected

5:0 R/W KBRD_IRQ1_SEL see KBRD_IRQ0_SEL 0x0



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Table 240: GPIO_DEBOUNCE_REG (0x5000140C)

13 R/W DEB_ENABLE_KBR enables the debounce counter for the KBRD interface 0x0
D
12 R/W DEB_ENABLE4 enables the debounce counter for GPIO IRQ4 0x0
5:0 R/W DEB_VALUE Keyboard debounce time if enabled. Generate KEYB_INT 0x0
after specified time.
Debounce time: N*1 ms. N =0..63
Table 241: GPIO_RESET_IRQ_REG (0x5000140E)

5 R0/W RESET_KBRD_IRQ writing a 1 to this bit will reset the KBRD IRQ. 0x0
Reading returns 0.
4 R0/W RESET_GPIO4_IRQ writing a 1 to this bit will reset the GPIO4 IRQ. 0x0
Reading returns 0.
Reading returns 0.
Reading returns 0.
Reading returns 0.
Reading returns 0.
Table 242: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

12 R/W EDGE_LEVELN4 see EDGE_LEVELn0, but for GPIO IRQ4 0x0
8 R/W EDGE_LEVELN0 0: do not wait for key release after interrupt was reset for 0x0
GPIO IRQ0, so a new interrupt can be initiated immediately
1: wait for key release after interrupt was reset for IRQ0

DA14580
Table 242: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

4 R/W INPUT_LEVEL4 see INPUT_LEVEL0, but for GPIO IRQ4 0x0
0 R/W INPUT_LEVEL0 0 = selected input will generate GPIO IRQ0 if that input is 0x0
high.
1 = selected input will generate GPIO IRQ0 if that input is
low.
Table 243: KBRD_IRQ_IN_SEL0_REG (0x50001412)

15 R/W KBRD_REL 0 = No interrupt on key release 0x0
1 = Interrupt also on key release (also debouncing if
enabled)
14 R/W KBRD_LEVEL 0 = enabled input will generate KBRD IRQ if that input is 0x0
high.
1 = enabled input will generate KBRD IRQ if that input is low.
13:8 R/W KEY_REPEAT While key is pressed, automatically generate repeating 0x0
KEYB_INT after specified time unequal to 0.
Repeat time: N*1 ms. N =1..63, N=0 disables the timer.
7 R/W KBRD_P07_EN enable P0[7] for the keyboard interrupt 0x0


DA14580


Table 246: GP_ADC_CTRL_REG (0x50001500)

15 R/W GP_ADC_LDO_ZER Forces LDO-output to 0V. 0x0
O
14 R/W GP_ADC_LDO_EN Turns on LDO. 0x0
13 R/W GP_ADC_CHOP Takes two samples with opposite GP_ADC_SIGN to cancel 0x0
the internal offset voltage of the ADC; Highly recommended
for DC-measurements.
12 R/W GP_ADC_MUTE Takes sample at mid-scale (to dertermine the internal offset 0x0
and/or noise of the ADC with regards to VDD_REF which is
also sampled by the ADC).
11 R/W GP_ADC_SE 0 = Differential mode 0x0
1 = Single ended mode
10 R/W GP_ADC_SIGN 0 = Default 0x0
1 = Conversion with opposite sign at input and output to can-
cel out the internal offset of the ADC and low-frequency
9:6 R/W GP_ADC_SEL ADC input selection which must be set before the 0x0
GP_ADC_START bit is enabled.
If GP_ADC_SE = 1 (single ended mode):
0000 = P0[0]
0001 = P0[1]
0010 = P0[2]
0011 = P0[3]
0100 = AVS
0101 = VDD_REF
0110 = VDD_RTT
0111 = VBAT3V
1000 = VDCDC
1001 = VBAT1V
All other combinations are reserved.
If GP_ADC_SE = 0 (differential mode):
0000 = P0[0] vs P0[1]
All other combinations are P0[2] vs P0[3].
5 R/W GP_ADC_MINT 0 = Disable (mask) GP_ADC_INT. 0x0
1 = Enable GP_ADC_INT to ICU.

DA14580
Table 246: GP_ADC_CTRL_REG (0x50001500)

4 R GP_ADC_INT 1 = AD conversion ready and has generated an interrupt. 0x0
Must be cleared by writing any value to
GP_ADC_CLEAR_INT_REG.
3 R/W GP_ADC_CLK_SEL 0 = Internal high-speed ADC clock used. 0x0
1 = Digital clock used.
2 - GP_ADC_TEST Reserved, keep 0. 0x0
1 R/W GP_ADC_START 0 = ADC conversion ready. 0x0
1 = If a 1 is written, the ADC starts a conversion. After the
conversion this bit will be set to 0 and the GP_ADC_INT bit
will be set.
0 R/W GP_ADC_EN 0 = ADC is disabled and in reset. 0x0
1 = ADC is enabled and sampling of input is started.
Table 247: GP_ADC_CTRL2_REG (0x50001502)

3 R/W GP_ADC_I20U Adds 20uA constant load current at the ADC LDO to mini- 0x0
mize ripple on the reference voltage of the ADC.
2 R/W GP_ADC_IDYN Enables dynamic load current at the ADC LDO to minimize 0x0
ripple on the reference voltage of the ADC.
1 R/W GP_ADC_ATTN3X 0 = Input voltages up to 1.2V allowed. 0x0
1 = Input voltages up to 3.6V allowed by enabling 3x attenu-
ator.
0 R/W GP_ADC_DELAY_E Enables delay function for several signals. This is not auto- 0x0
N cleared. Toggle this bit before every sampling to enable suc-
cesive conversions.
Table 248: GP_ADC_OFFP_REG (0x50001504)

9:0 R/W GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network (effective if 0x200
"GP_ADC_SE=0", or "GP_ADC_SE=1 AND
GP_ADC_SIGN=0")
Table 249: GP_ADC_OFFN_REG (0x50001506)

9:0 R/W GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network (effective if 0x200
"GP_ADC_SE=0", or "GP_ADC_SE=1 AND
GP_ADC_SIGN=1")
Table 250: GP_ADC_CLEAR_INT_REG (0x50001508)

15:0 R0/W GP_ADC_CLR_INT Writing any value to this register will clear the ADC_INT 0x0
interrupt. Reading returns 0.

DA14580
Table 251: GP_ADC_RESULT_REG (0x5000150A)

9:0 R GP_ADC_VAL Returns the 10 bits linear value of the last AD conversion. 0x0
Table 252: GP_ADC_DELAY_REG (0x5000150C)

7:0 R/W DEL_LDO_EN Defines the delay before the LDO enable 0x0
(GP_ADC_LDO_EN). Reset value is 0 µs since the LDO
enable should be the first thing to be programmed in the
sequence of bringing the GP ADC up.
Table 253: GP_ADC_DELAY2_REG (0x5000150E)

15:8 R/W DEL_ADC_START Defines the delay for the GP_ADC_START bit. Reset value 0x88
is 17 µs which is the recommended value to wait before
starting the GP ADC. This is the third and last step of bring-
ing up the GP ADC
7:0 R/W DEL_ADC_EN Defines the delay for the GP_ADC_EN bit. Reset value is 16 0x80
µs which is the recommended value to wait after enabling
the LDO. This is the second step in bringing up the GP ADC.
Table 254: CLK_REF_SEL_REG (0x50001600)

2 R/W REF_CAL_START Writing a '1' starts a calibration. This bit is cleared when cali- 0x0
bration is finished, and CLK_REF_VAL is ready.
1:0 R/W REF_CLK_SEL Select clock input for calibration: 0x0
0x0 : RC32KHz oscillator
0x1 : RC16MHz oscillator
0x2 : XTAL32KHz oscillator
0x3 : RCX32KHz oscillator
Table 255: CLK_REF_CNT_REG (0x50001602)

15:0 R/W REF_CNT_VAL Indicates the calibration time, with a decrement counter to 1. 0x0
Table 256: CLK_REF_VAL_L_REG (0x50001604)

15:0 R XTAL_CNT_VAL Returns the lower 16 bits of XTAL16 clock cycles during the 0x0
calibration time, defined with REF_CNT_VAL

DA14580
Table 257: CLK_REF_VAL_H_REG (0x50001606)

15:0 R XTAL_CNT_VAL Returns the upper 16 bits of XTAL16 clock cycles during the 0x0
calibration time, defined with REF_CNT_VAL
Table 258: P0_DATA_REG (0x50003000)

7:0 R/W P0_DATA Set P0 output register when written; Returns the value of P0 0x0
port when read
Table 259: P0_SET_DATA_REG (0x50003002)

7:0 R/W P0_SET Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded; 0x0
Reading returns 0
Table 260: P0_RESET_DATA_REG (0x50003004)

7:0 R/W P0_RESET Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded; 0x0
Reading returns 0
Table 261: P00_MODE_REG (0x50003006)

9:8 R/W PUPD 00 = Input, no resistors selected 0x2
01 = Input, pull-up selected
11 = Output, no resistors selected
In ADC mode, these bits are don't care

DA14580
Table 261: P00_MODE_REG (0x50003006)

4:0 R/W PID Function of port 0x0
0 = Port function, PUPD as set above
1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
15 = ADC (only for P0[3:0])
16 = PWM0
17 = PWM1
18 = BLE_DIAG (only for P0[7:0])
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Note: when a certain input function (like SPI_DI) is selected
on more than 1 port pin, the port with the lowest index has
the highest priority and P0 has higher priority than P1.
Table 262: P01_MODE_REG (0x50003008)


DA14580
Table 262: P01_MODE_REG (0x50003008)

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 263: P02_MODE_REG (0x5000300A)


DA14580

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 264: P03_MODE_REG (0x5000300C)


DA14580

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 265: P04_MODE_REG (0x5000300E)


DA14580

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 266: P05_MODE_REG (0x50003010)


DA14580
Table 266: P05_MODE_REG (0x50003010)

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 267: P06_MODE_REG (0x50003012)


DA14580
Table 267: P06_MODE_REG (0x50003012)

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4
Table 268: P07_MODE_REG (0x50003014)


DA14580
Table 268: P07_MODE_REG (0x50003014)

1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SPI_DI
6 = SPI_DO
7 = SPI_CLK
8 = SPI_EN
9 = I2C_SCL
10 = I2C_SDA
11 = UART1_IRDA_RX
12 = UART1_IRDA_TX
13 = UART2_IRDA_RX
14 = UART2_IRDA_TX
16 = PWM0
17 = PWM1
19 = UART1_CTSN
20 = UART1_RTSN
21 = UART2_CTSN
22 = UART2_RTSN
23 = PWM2
24 = PWM3
25 = PWM4

port when read

Reading returns 0

Reading returns 0

DA14580
Table 272: P10_MODE_REG (0x50003026)

In analog mode, these bits are don't care
P14_MODE_REG and P15_MODE_REG reset value is 1
(i.e. pulled up)
4:0 R/W PID See P0x_MODE_REG[PID] 0x0
Table 273: P11_MODE_REG (0x50003028)

(i.e. pulled up)

(i.e. pulled up)

(i.e. pulled up)

DA14580


(i.e. pulled up)
Table 277: P15_MODE_REG (0x50003030)

(i.e. pulled up)

port when read

Reading returns 0

Reading returns 0

DA14580
Table 281: P20_MODE_REG (0x50003046)

Table 282: P21_MODE_REG (0x50003048)





DA14580

Table 286: P25_MODE_REG (0x50003050)

Table 287: P26_MODE_REG (0x50003052)

Table 288: P27_MODE_REG (0x50003054)

Table 289: P28_MODE_REG (0x50003056)


DA14580
Table 289: P28_MODE_REG (0x50003056)

Table 290: P29_MODE_REG (0x50003058)

Table 291: P01_PADPWR_CTRL_REG (0x50003070)

13:8 R/W P1_OUT_CTRL 1 = P1_x port output is powered by the 1 V rail 0x0
0 = P1_x port output is powered by the 3 V rail
bit 8 controls the power of P1[0],
bit 13 controls the power of P1[5]
(Note 19)
bit 7 controls the power of P0[7]
(Note 20)
Note 19: In Buck mode the output must be powered by the 3 V rail. In Boost mode the outputs can be powered by the 1 V rail or by the 3 V rail. In
Boost mode the 3 V rail can only supply a limited current, e.g. for switching a high-impedance input of an external device. See table 'Digital
input/output characteristics'.

(Note 21)

DA14580

15:8 - - Reserved 0
7:0 R/W P3_OUT_CTRL 1 = P3_x port output is powered by the 1 V rail 0
(Note 22)

15:8 - - Reserved 0
7:0 R/W P3_DATA Set P3 output register when written; Returns the value of P3 0
port when read

15:8 - - Reserved 0
7:0 R0/W P3_SET Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded; 0
Reading returns 0

15:8 - - Reserved 0
7:0 R0/W P3_RESET Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded; 0
Reading returns 0
Table 297: P30_MODE_REG (0x50003086)

9:8 R/W PUPD 00 = Input, no resistors selected 2
7:5 - - Reserved 0
4:0 R/W PID See P0x_MODE_REG[PID] 0
Table 298: P31_MODE_REG (0x50003088)


DA14580
Table 298: P31_MODE_REG (0x50003088)

7:5 - - Reserved 0

7:5 - - Reserved 0

7:5 - - Reserved 0

7:5 - - Reserved 0
Table 302: P35_MODE_REG (0x50003090)


DA14580
Table 302: P35_MODE_REG (0x50003090)

7:5 - - Reserved 0
Table 303: P36_MODE_REG (0x50003092)

7:5 - - Reserved 0
Table 304: P37_MODE_REG (0x50003094)

7:5 - - Reserved 0
Table 305: WATCHDOG_REG (0x50003100)

15:9 R0/W WDOG_WEN 0000.000 = Write enable for Watchdog timer 0x0
else Write disable. This filter prevents unintentional preset-
ting the watchdog with a SW run-away.
8 R/W WDOG_VAL_NEG 0 = Watchdog timer value is positive. 0x0
1 = Watchdog timer value is negative.
7:0 R/W WDOG_VAL Write: Watchdog timer reload value. Note that all bits 15-9 0xFF
must be 0 to reload this register.
Read: Actual Watchdog timer value. Decremented by 1
every 10.24 msec. Bit 8 indicates a negative counter value.
2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is
generated under the following conditions:
If WATCHDOG_CTRL_REG[NMI_RST] = 0 then
If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt)
if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16
If WATCHDOG_CTRL_REG[NMI_RST] = 1 then
if WDOG_VAL <= 0 -> WDOG reset -> reload FF16

DA14580
Table 306: WATCHDOG_CTRL_REG (0x50003102)

1 - - Reserved 0x0
0 R/W NMI_RST 0 = Watchdog timer generates NMI at value 0, and WDOG 0x0
(SYS) reset at <=-16. Timer can be frozen /resumed using
SET_FREEZE_REG[FRZ_WDOG]/
RESET_FREEZE_REG[FRZ_WDOG].
1 = Watchdog timer generates a WDOG (SYS) reset at value

0 and can not be frozen by Software.
Note that this bit can only be set to 1 by SW and only be
reset with a WDOG (SYS) reset or SW reset.
The watchdog is always frozen when the Cortex-M0 is halted

in DEBUG State.
Table 307: CHIP_ID1_REG (0x50003200)

7:0 R CHIP_ID1 First character of device type "580" in ASCII. 0x35

7:0 R CHIP_ID2 Second character of device type "580" in ASCII. 0x38

7:0 R CHIP_ID3 Third character of device type "580" in ASCII. 0x30
Table 310: CHIP_SWC_REG (0x50003203)

3:0 R CHIP_SWC SoftWare Compatibility code. 0x0
Integer (default = 0) which is incremented if a silicon change
has impact on the CPU Firmware.
Can be used by software developers to write silicon revision
dependent code.
Table 311: CHIP_REVISION_REG (0x50003204)

7:0 R REVISION_ID Chip version, corresponds with type number in ASCII. 0x41
0x41 = 'A', 0x42 = 'B'
Table 312: SET_FREEZE_REG (0x50003300)


DA14580
Table 312: SET_FREEZE_REG (0x50003300)

3 R/W FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. 0x0
WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow
the freeze function.
2 R/W FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is discarded. 0x0
1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) is frozen, '0' is discarded. 0x0
0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0x0
Table 313: RESET_FREEZE_REG (0x50003302)

3 R/W FRZ_WDOG If '1', the watchdog timer continues, '0' is discarded. 0x0
2 R/W FRZ_BLETIM If '1', the the BLE master clock continues, '0' is discarded. 0x0
1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) continues, '0' is discarded. 0x0
0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is discarded. 0x0
Table 314: DEBUG_REG (0x50003304)

0 R/W DEBUGS_FREEZE_ Default '1', freezing of the on-chip timers is enabled when the 0x1
EN Cortex-M0 is halted in DEBUG State.
If '0', freezing of the on-chip timers is depending on
FREEZE_REG when the Cortex-M0 is halted in DEBUG
State except the watchdog timer. The watchdog timer is
always frozen when the Cortex-M0 is halted in DEBUG
State.
Table 315: GP_STATUS_REG (0x50003306)

0 R/W CAL_PHASE If '1', it designates that the chip is in Calibration Phase i.e. 0x0
the OTP has been initially programmed but no Calibration
has occured.
Table 316: GP_CONTROL_REG (0x50003308)

15:6 - - Reserved 0

DA14580
Table 316: GP_CONTROL_REG (0x50003308)

5:1 R/W EM_MAP Select the mapping of the Exchange memory pages. 0x1
0: EM size 0 kB, SysRAM size 42 kB
8: Reserved
16: Reserved
other: Reserved.
0 R/W BLE_WAKEUP_REQ If '1', the BLE wakes up. Must be kept high at least for 1 low 0x0
power clock period.
If the BLE is in deep sleep state, then by setting this bit it will
cause the wakeup LP IRQ to be asserted with a delay of 3 to
4 low power cycles.
Table 317: TIMER0_CTRL_REG (0x50003400)

3 R/W PWM_MODE 0 = PWM signals are '1' during high time. 0x0
1 = PWM signals send out the (fast) clock divided by 2 dur-
ing high time. So it will be in the range of 1 to 8 MHz.
2 R/W TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0x0
0 = Timer0 uses selected clock frequency divided by 10.
Note that this applies only to the ON-counter.
1 R/W TIM0_CLK_SEL 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0x0
0 = Timer0 uses 32 kHz (slow) clock frequency.
0 R/W TIM0_CTRL 0 = Timer0 is off and in reset state. 0x0
1 = Timer0 is running.
Table 318: TIMER0_ON_REG (0x50003402)

15:0 R0/W TIM0_ON Timer0 On reload value: 0x0
If read the actual counter value ON_CNTer is returned

DA14580
Table 319: TIMER0_RELOAD_M_REG (0x50003404)

15:0 R0/W TIM0_M Timer0 'high' reload valueIf read the actual counter value 0x0
T0_CNTer is returned
Table 320: TIMER0_RELOAD_N_REG (0x50003406)

15:0 R0/W TIM0_N Timer0 'low' reload value: 0x0
If read the actual counter value T0_CNTer is returned
Table 321: PWM2_DUTY_CYCLE (0x50003408)

13:0 R/W DUTY_CYCLE duty cycle for PWM 0x0
Table 322: PWM3_DUTY_CYCLE (0x5000340A)

Table 323: PWM4_DUTY_CYCLE (0x5000340C)

Table 324: TRIPLE_PWM_FREQUENCY (0x5000340E)

13:0 R/W FREQ Freq for PWM 2 3 4 0x0
Table 325: TRIPLE_PWM_CTRL_REG (0x50003410)

2 R/W HW_PAUSE_EN '1' = HW can pause PWM 2,3,4 0x1
1 R/W SW_PAUSE_EN '1' = PWM 2 3 4 is paused 0x0
0 R/W TRIPLE_PWM_ENA '1' = PWM 2 3 4 is enabled 0x0
BLE

DA14580
27 Specifications
All MIN/MAX specification limits are guaranteed by design, production testing and/or statistical characterization. Typ-
ical values are based on characterization results at default measurement conditions and are informative only.
Default measurement conditions (unless otherwise specified): VBAT(VBAT3V) = 3.0 V (buck mode), VBAT(VBAT1V)
= 1.2 V (boost mode), TA = 25 C. All radio measurements are performed with standard RF measurement equipment
providing a source/load impedance of 50 .
The specifications in the following tables are valid for the reference circuits shown in Figure 68 (Boost mode) and
Figure 69 (Buck mode).
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Figure 68: Alkaline Battery Cell Powered System Diagram (Boost Mode)

DA14580
9%$7 73 9%$7

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Figure 69: Lithium Coin Cell Powered System Diagram (Buck Mode)

DA14580
Table 326: Absolute Maximum Ratings
Parameter Description Conditions Min Typ Max Unit

VPIN(LIM)(defaul limiting voltage on a pin Voltage between pin and -0.1 min{3.6, V
t) GND VBAT_RF
(Note 23) +0.2}
TSTG storage temperature -50 150 °C
tR(SUP) supply rise time Power supply rise time 100 ms
VBAT(LIM)(VBAT limiting battery supply Supply voltage on -0.1 3.6 V
1V) voltage VBAT1V in a boost con-
verter application
(VBAT3V is second out-
put of boost-converter in
this case)
(Note 23)
VBAT(LIM)(VBAT limiting battery supply Supply voltage on -0.1 3.6 V
3V) voltage VBAT3V and VBAT_RF
in a buck-converter
application, pin VBAT1V
is connected to ground
(Note 23)
VPIN(LIM)(1V2) limiting voltage on a pin XTAL32Km, XTAL16Mp, -0.2 min(1.2,V V
XTAL16Mm BAT_RF+
(Note 23) 0.2)
VPIN(LIM)(VDC limiting voltage on the Supply voltage on -0.2 min(3.3,V V
DC_RF) VDCDC_RF pin VDCDC_RF BAT_RF+
(Note 23) 0.2)
VPIN(LIM)(XTAL limiting voltage on a pin XTAL32Kp -0.2 min(1.5,V V
32Kp) BAT_RF+
0.2)
VESD(HBM)(WL electrostatic discharge 2000 V
CSP34) voltage (Human Body
Model)
VESD(HBM)(QF electrostatic discharge 4000 V
N40) voltage (Human Body
Model)
VESD(HBM)(QF electrostatic discharge 4000 V
N48) voltage (Human Body
Model)
VESD(MM)(WLC electrostatic discharge 200 V
SP34) voltage (Machine Model)
VESD(MM)(QFN electrostatic discharge 200 V
40) voltage (Machine Model)
VESD(MM)(QFN electrostatic discharge 200 V
48) voltage (Machine Model)
VESD(CDM)(WL electrostatic discharge 500 V
CSP34) voltage (Charged Device
Model)
VESD(CDM)(QF electrostatic discharge 1000 V
N40) voltage (Charged Device
Model)
VESD(CDM)(QF electrostatic discharge 1000 V
N48) voltage (Charged Device
Model)

DA14580
Note 23: The device should not be exposed for prolonged periods of time to voltages between the Recommended Operating Conditions and the
Absolute Maximum Ratings range.
Table 327: Recommended Operating Conditions

VPP programming voltage Supply voltage on pin 6.6 6.7 6.8 V
VPP during OTP pro-
gramming; TJ  50 C
VBAT(VBAT1V) battery supply voltage Supply voltage on 0.9 3.3 V
VBAT1V in a boost con-
verter application
(VBAT3V is second out-
put of boost-converter in
this case)
VBAT(VBAT3V) battery supply voltage Supply voltage on 2.35 3.3 V
VBAT3V and VBAT_RF (Note 24)
in a buck-converter
application, pin VBAT1V
is connected to ground
VPIN(default) voltage on a pin Voltage between pin and 0 min(3.3,V V
GND BAT_RF+
0.2)
VPIN(1V2) voltage on a pin XTAL32Km, XTAL16Mp, 0 1.2 V
XTAL16Mm
VPIN(VDCDC_ voltage on a pin Supply voltage on 0 3.3 V
RF) VDCDC_RF
TA ambient temperature -40 85 °C
Note 24: Cold boot should not be performed if voltage is less than 2.5 V because of possible corruption during OTP data mirroring. Trim values pro-
grammed in the OTP as well as the application image, should be copied into RAM while VBAT3V >= 2.5 V.
Table 328: DC Characteristics

IBAT(DP_SLP)_ battery supply current Boost configuration in 0.48 A
BOOST_1kB deep-sleep with 1 kB
retention RAM active,
running from RC32K
oscillator at lowest fre-
quency
IBAT(DP_SLP)_ battery supply current Boost configuration in 0.55 A
BOOST_2kB deep-sleep with 2 kB
running from XTAL32K
oscillator
IBAT(DP_SLP)_ battery supply current Typical boost-applica- 0.7 2 A
BOOST_8kB tion in deep-sleep with 8
kB retention RAM active,
oscillator
IBAT(EXT_SLP) battery supply current Typical boost-applica- 1.37 A
_BOOST_43K tion in extended-sleep
B mode with 42 kB (Sys-
RAM) and 1 kB
(RetRAM) retained

DA14580
Table 328: DC Characteristics

IBAT(EXT_SLP) battery supply current Typical boost-applica- 1.5 3 A
_BOOST_50kB tion in extended-sleep
mode with 42 kB (Sys-
RAM) and 8 kB
(RetRAM) retained
IBAT(DP_SLP)_ battery supply current Buck configuration in 0.4 A
BUCK_1kB deep-sleep with 1 kB
running from RC32K
oscillator at lowest fre-
quency
IBAT(DP_SLP)_ battery supply current Buck configuration in 0.45 A
BUCK_2kB deep-sleep with 2 kB
oscillator
IBAT(DP_SLP)_ battery supply current Typical buck-application 0.6 2 A
BUCK_8kB in deep-sleep with 8 kB
oscillator
IBAT(EXT_SLP) battery supply current Typical buck-application 1.2 A
_BUCK_43KB in extended-sleep mode
with 42 kB (SysRAM)
and 1 kB (RetRAM)
retained
IBAT(EXT_SLP) battery supply current Typical buck-application 1.4 3 A
_BUCK_50kB in extended-sleep mode
with 42 kB (SysRAM)
and 8 kB (RetRAM)
retained
IBAT(ACT_RX)_ battery supply current Typical application with 13.4 16 mA
BOOST boost converter and
receiver active
IBAT(ACT_TX)_ battery supply current Typical application with 12.4 15 mA
BOOST boost converter and
transmitter active
IBAT(ACT_RX)_ battery supply current Typical application with 5.1 6 mA
BUCK buck converter and
receiver active
IBAT(ACT_TX)_ battery supply current Typical application with 4.8 6 mA
BUCK buck converter and
transmitter active
Table 329: Timing Characteristics

tSTA(BOOST) startup time Boost-mode; time from 1.2 ms
deep-sleep to software (Note 25)
start.
Typical application, run-
ning from retention RAM
on 16 MHz RC oscillator

DA14580
Table 329: Timing Characteristics

tSTA(BUCK) startup time Buck-mode; time from 1 ms
deep-sleep to software (Note 25)
start.
Typical application, run-
ning from retention RAM
on 16 MHz RC oscillator
Note 25: Worst-case value under Normal Operating Conditions.
Table 330: 16 MHz Crystal Oscillator: Recommended Operating Conditions

fXTAL(16M) crystal oscillator fre- 16 MHz
quency
ESR(16M) equivalent series resis- 100 
tance
CL(16M) load capacitance No external capacitors 10 12 pF
are required
C0(16M) shunt capacitance 5 pF
fXTAL(16M) crystal frequency toler- After optional trimming; -20 20 ppm
ance including aging and tem-
perature drift
(Note 26)
fX- crystal frequency toler- Untrimmed; including -40 40 ppm
TAL(16M)UNT
ance aging and temperature
drift
(Note 27)
PDRV(MAX)(16M maximum drive power (Note 28) 100 W
)
VCLK(EXT)(16M) external clock voltage Only in case of an exter- 1 1.2 V
nal reference clock on
XTAL16Mp (XTAL16Mm
floating or connected to
mid-level 0.6 V)
N(EXTER- phase noise fC = 50 kHz -130 dBc/
NAL)16M in case of an external Hz
reference clock
Note 26: Using the internal varicaps a wide range of crystals can be trimmed to the required tolerance.
Note 27: Maximum allowed frequency tolerance for compensation by the internal varicap trimming mechanism.
Note 28: Select a crystal which can handle a drive-level equal or more than this specification
Table 331: 16 MHz Crystal Oscillator: Timing Characteristics

tSTA(XTAL)(16M) crystal oscillator startup 0.5 2 3 ms
time

DA14580
Table 332: 32 kHz Crystal Oscillator: Recommended Operating Conditions

VCLK(EXT)(32K) external clock voltage peak-peak voltage of 0.1 0.2 1.5 V
external clock at
XTAL32Kp, pin
XTAL32Km floating.
note: XTAL32Kp is inter-
nally AC coupled
fXTAL(32k) crystal oscillator fre- frequency range for an 10 32.768 100 kHz
quency external clock
(for a crystal, use either
32.000 kHz or 32.768
kHz)
ESR(32k) equivalent series resis- 100 k
tance
CL(32k) load capacitance no external capacitors 6 7 9 pF
are required for a 6 pF or
7 pF crystal
C0(32k) shunt capacitance 1 2 pF
fXTAL(32k) crystal frequency toler- Timing accuracy is domi- -250 250 ppm
ance (including aging) nated by crystal accu-
racy. A much smaller
value is preferred
PDRV(MAX)(32k) maximum drive power (Note 29) 0.1 W
Note 29: Select a crystal that can handle a drive-level of at least this specification.
Table 333: 32 kHz Crystal Oscillator: Timing Characteristics

tSTA(XTAL)(32k) crystal oscillator startup Typical application, time 0.4 s
time until 1000 clocks are
detected
(Note 30)
Note 30: This parameter is very much dependent on crystal parameters
Table 334: DC-DC Converter: Recommended Operating Conditions

L effective inductance 1.5 2.2 3 H
COUT(VDCDC) effective load capaci- VDCDC and VDDCRF 0.5 1 10 F
tance combined
(Note 31)
COUT(VBAT3V) effective load capaci- VBATRF and VBAT3V 0.5 1 10 F
tance combined are the sec-
ond output of the boost-
converter
(Note 31)
Note 31: A low value will result in lowest power consumption, keep this value at 1 uF or 2 uF.
Table 335: DC-DC Converter: DC Characteristics

VO(BUCK) output voltage default settings 1.41 V

DA14580
Table 335: DC-DC Converter: DC Characteristics

VO(BOOST) output voltage default settings, VDCDC 1.41 V
CONV_MAX(BU maximum conversion 86 %
CK) efficiency
CONV_MAX(BO maximum conversion 80 %
OST) efficiency
VO/ line regulation 2.35 V  VBAT3V  3.3 V -2 0.7 2 %/V
VI(BUCK)
VO/ line regulation 0.9 V  VBAT1V  1.2 V -2 1 4 %/V
VI(BOOST) (Note 32)
VO/IL(BUCK) load regulation VBAT3V = 2.5 V -0.2 -0.02 0.2 %/mA
VO/ load regulation VBAT1V = 1.2 V -0.2 -0.07 0.2 %/mA
IL(BOOST)
VRPL(BUCK) ripple voltage buck mode; RMS ripple 5 mV
voltage
VRPL(BOOST) ripple voltage VBAT1V  1.2 V, boost 8 mV
mode; RMS ripple volt-
age
(Note 32)
Note 32: When VBAT1V > VDCDC_nominal, VDCDC will follow VBAT1V.
Table 336: Digital Input/Output: DC Characteristics

VIH HIGH level input voltage 0.84 V
VIL LOW level input voltage 0.36 V
VIH(RST) HIGH level input voltage RST pin 0.84 V
VIL(RST) LOW level input voltage RST pin 0.36 V
VOH(VBAT1V) HIGH level output volt- Iout = -250 A, VBAT3V 0.72 V
age = 2.35 V, VBAT1V = 0.9
V
VOH(VBAT3V) HIGH level output volt- Iout = -4.8 mA, VBAT3V 1.88 V
age = 2.35 V, VBAT1V = 0 V
(Note 33)
VOL(VBAT1V) LOW level output voltage Iout = 250 A, VBAT3V = 0.18 V
2.35 V, VBAT1V = 0.9 V
VOL(VBAT3V) LOW level output voltage Iout = 4.8 mA, VBAT3V = 0.47 V
2.35 V, VBAT1V = 0 V
(Note 34)
IIH HIGH level input current Vin = VBAT3V = 2.5 V -1 1 A
IIL LOW level input current Vin = VSS = 0 V -1 1 A
IIH(PD) HIGH level input current Vin = VBAT3V = 2.5 V 50 150 A
IIL(PU) LOW level input current Vin = VSS = 0 V -150 -50 A
IIH(RST) HIGH level input current RST pin, V(RST) = 1.2 V 25 75 A
Note 33: In Boost mode the output source current is limited to Iout = -250 uA.
Note 34: In Boost mode the output sink current is limited to Iout = 250 uA.

DA14580
Table 337: General Purpose ADC: Recommended Operating Conditions

NBIT(ADC) number of bits (resolu- 10 bit
tion)
Table 338: General Purpose ADC: DC Characteristics

VI(ZS) zero-scale input voltage single-ended, calibrated -2.5 0 2.5 mV
at zero input
VI(FS) full-scale input voltage single-ended, calibrated 1150 1180 1250 mV
at zero input
VI(FSN) negative full-scale input differential, calibrated at -1180 mV
voltage zero input
VI(FSP) positive full-scale input differential, calibrated at 1180 mV
voltage zero input
INL integral non-linearity -2 2 LSB
DNL differential non-linearity -2 2 LSB
Table 339: General Purpose ADC: Timing Characteristics

tCONV(ADC) conversion time Excluding initial settling 0.25 0.4 s
time of the LDO and the
3x-attenuation (if used):
LDO settling time is 20

s (max), 3x-attenuation
settling time = 1 s (max)
Using internal ADC-clock
(~200 MHz)
Table 340: Radio: DC Characteristics

IBAT(RF)RX battery supply current receive mode; radio 3.7 4.3 mA
receiver and synthesizer
active; DCDC converter
assumed ideal; TA = 25
°C
(Note 35)
IBAT(RF)TX battery supply current transmit mode; radio 3.4 4 mA
transmitter and synthe-
sizer active; DCDC con-
verter assumed ideal; TA
= 25 °C
(Note 35)
Note 35: The DCDC-converter efficiency is assumed to be 100 % to enable benchmarking of the radio currents at battery supply domain (VBAT3V =
3 V).

DA14580
Table 341: Radio: AC Characteristics

PSENS(CLEAN) sensitivity level DC-DC converter -93 dBm
enabled; Dirty Transmit-
ter disabled; TA = 25 °C;
PER = 30.8 %
(Note 36)
PSENS sensitivity level Normal Operating Condi- -92.5 dBm
tions; DC-DC converter
enabled; TA = 25 °C;
PER = 30.8 %
(Note 36)
PSENS(EOC) sensitivity level Extreme Operating Con- -87 dBm
ditions; DC-DC converter
enabled; PER = 30.8 %;
-40 °C  TA  +85 °C
(Note 37)
PI(max) input power level DC-DC converter dis- 10 dBm
abled; TA = 25 C; PER 
30.8 %
(Note 36)
PINT(IMD) intermodulation distor- worst case interferer -35 -31 dBm
tion interferer power level @ f1, f2 with 2f1-f2 =
level f0, |f1-f2| = n MHz and n =
3,4,5; PWANTED = -64
dBm @ f0; PER = 30.8
%; TA = 25 °C
(Note 38)
CIR(0) carrier to interferer ratio n = 0; interferer @ f1 = f0 7 21 dB
+ n*1 MHz; TA = 25 °C
(Note 39)
CIR(1) carrier to interferer ratio n = ±1; interferer @ f1 = -3 15 dB
f0 + n*1 MHz; TA = 25 °C
(Note 39)
CIR(P2) carrier to interferer ratio n = +2 (image fre- -20 -9 dB
quency); interferer @ f1
= f0 + n*1 MHz; TA = 25
C
(Note 39)
CIR(M2) carrier to interferer ratio n = -2; interferer @ f1 = -30 -17 dB
f0 + n*1 MHz; TA = 25 C
(Note 39)
CIR(P3) carrier to interferer ratio n = +3 (image frequency -30 -15 dB
+ 1 MHz); interferer @ f1
= f0 + n*1 MHz; TA = 25
C
(Note 39)
CIR(M3) carrier to interferer ratio n = -3; interferer @ f1 = -35 -27 dB
f0 + n*1 MHz; TA = 25 C
(Note 39)

DA14580

CIR(4) carrier to interferer ratio |n| >= 4 (any other BLE -37 -27 dB
channel); interferer @ f1
= f0 + n*1 MHz; TA = 25
°C
(Note 39)
PBL(I) blocker power level 30 MHz  fBL  2000 -5 dBm
MHz; PWANTED = -67
dBm; TA = 25 °C
(Note 40)
PBL(II) blocker power level 2003 MHz  fBL  2399 -15 dBm
MHz; PWANTED = -67
dBm; TA = 25 °C
(Note 40)
PBL(III) blocker power level 2484 MHz  fBL  2997 -15 dBm
MHz; PWANTED = -67
dBm; TA = 25 C
(Note 40)
PBL(IV) blocker power level 3000 MHz  fBL  12.75 -5 dBm
GHz; PWANTED = -67
dBm; TA = 25 C
(Note 40)
PRSSI(min) RSSI power level absolute power level for -115 -112 -109 dBm
RXRSSI[7:0] = 0; TA =
25 °C
(Note 41)
PRSSI(max) RSSI power level upper limit of monoto- -26 -19 dBm
nous range; TA = 25 °C
LACC(RSSI)BO level accuracy tolerance of 5 % to 95 % 0 3 dB
OST confidence interval of
PRF: when RXRSSI[7:0]
= X, 50 < X < 175; burst
mode 1500 packets; TA
= 25 °C; DC-DC con-
verter in BOOST mode
LACC(RSSI)BU level accuracy tolerance of 5 % to 95 % 0 2 dB
CK confidence interval of
PRF: when RXRSSI[7:0]
= X, 50 < X < 175; burst
= 25 °C; DC-DC con-
verter in BUCK mode
LRES(RSSI) level resolution gradient of monotonous 0.46 0.474 0.485 dB/
range for RXRSSI[7:0] = LSB
X, 50 < X < 175; burst
= 25C
ACP(2M) adjacent channel power fOFFSET = 2 MHz; TA = -53 -50 dBm
level 25C
(Note 42)

DA14580

ACP(2M)(EOC) adjacent channel power fOFFSET = 2 MHz; -40C -53 -47 dBm
level  TA  +85C
(Note 42)
ACP(3M) adjacent channel power fOFFSET  3 MHz; TA = -57 -55 dBm
level 25C
(Note 42)
ACP(3M)(EOC) adjacent channel power fOFFSET  3 MHz; -40C -57 -47 dBm
level  TA  +85C
(Note 42)
PO output power level VDD = 3 V; maximum -2 -1 0 dBm
gain; TA = 25 °C
PO(HD2) output power level (sec- VDD = 3 V; maximum -54 -40 dBm
ond harmonic) gain; TA = 25 C
PO(HD3) output power level (third VDD = 3 V; maximum -56 -40 dBm
harmonic) gain; TA = 25 C
PO(HD4) output power level VDD = 3 V; maximum -70 -40 dBm
(fourth harmonic) gain; TA = 25 C
PO(HD5) output power level (fifth VDD = 3 V; maximum -70 -40 dBm
harmonic) gain; TA = 25 C
PO(NFM) output power level in VDD = 3 V; maximum -25 -20 -15 dBm
'Near Field Mode' gain; TA = 25 °C
(Note 43)
Note 36: Measured according to Bluetooth® Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.4.1.
Note 38: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.4. Published value is for n =
IXIT = 4 . IXIT = 5 gives the same results, IXIT = 3 gives results that are 5 dB lower.
Note 39: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.2.
Note 40: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.3. Due to limitations of the
measurement equipment, levels of -5 dBm should be interpreted as > -5 dBm.
Note 41: PRF = PRSSI(min) + LRES(RSSI) x RXRSSI[7:0] ± LACC(RSSI). Thanks to constant gain biasing of RF part in the receiver, the RSSI can
be used to estimate absolute power levels, rather than mere level changes. Even across the full temperature range the variation is limited.
Note 43: To activate the "Near Field Mode", program address 0x50002418 with the value 0x0030.
Table 342: Stable Low Frequency RCX Oscillator: Timing Characteristics

fRC(RCX) RCX oscillator frequency default setting, buck 5 10 40 kHz
mode only
fRC(RCX) RCX oscillator fre- buck mode only -500 500 ppm
quency drift (Note 44)
TA/ ambient temperature buck mode only; connec- 0.66 °C/s
t(RCX)100ms gradient tion interval 100 ms
TA/t(RCX)4s ambient temperature buck mode only; connec- 0.33 °C/s
gradient tion interval 4 s
Note 44: Maximum recommended connection interval (including slave latency) for the RCX usage is 2 s.

DA14580
28 Package Information
28.1 MOISTURE SENSITIVITY LEVEL (MSL)
The MSL is an indicator for the maximum allowable
time period (floor life time) in which a moisture sensi-
tive plastic device, once removed from the dry bag, can
be exposed to an environment with a maximum tem-
perature of 30 °C and a maximum relative humidity of
60 % RH. before the solder reflow process.
WLCSP packages are qualified for MSL 1.
QFN packages are qualified for MSL 3.
MSL Level Floor Life Time

MSL 4 72 hours
MSL 3 168 hours
MSL 2A 4 weeks
MSL 2 1 year
MSL 1 Unlimited at 30 °C / 85 % RH
28.2 WLCSP HANDLING

Manual handling of WLCSP packages should be
reduced to the absolute minimum. In cases where it is
still necessary, a vacuum pick-up tool should be used.
In extreme cases plastic tweezers could be used, but
metal tweezers are not acceptable, since contact may
easily damage the silicon chip.
Removal will cause damage to the solder balls and
therefore a removed sample cannot be reused.
WLCSP is sensitive to visible and infrared light. Pre-
cautions should be taken to properly shield the chip in
the final product.
28.3 SOLDERING INFORMATION

Refer to the JEDEC standard J-STD-020 for relevant
soldering information.
This document can be downloaded from http://
www.jedec.org

DA14580
28.4 PACKAGE OUTLINES
Figure 70: QFN48 Package Outline Drawing

DA14580
Figure 71: QFN40 Package Outline Drawing

DA14580
Figure 72: WLCSP34 Package Outline Drawing

DA14580
Status Definitions
Version Datasheet Status Product Status Definition
1.<n> Target Development This datasheet contains the design specifications for product
development. Specifications may change in any manner without
notice.
2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary char-
acterization data for products in pre-production. Specifications
may be changed at any time without notice in order to improve
the design.
3.<n> Final Production This datasheet contains the final specifications for products in
volume production. The specifications may be changed at any
time in order to improve the design, manufacturing and supply.
Major specification changes are communicated via Customer
Product Notifications. Datasheet changes are communicated
via www.dialog-semiconductor.com.
4.<n> Obsolete Archived This datasheet contains the specifications for discontinued
products. The information is provided for reference only.
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General Description  42 kB System SRAM

Datasheet Revision 3.4 09-Nov-2016

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 OTP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12.1 OPERATING MODES . . . . . . . . . . . . . . . . . . 33

Datasheet Revision 3.4 09-Nov-2016

22 General Purpose ADC. . . . . . . . . . . . . . . . . . . . . . 65

28 Package Information . . . . . . . . . . . . . . . . . . . . . . 230

Datasheet Revision 3.4 09-Nov-2016

Figure 1: DA14580 Block Diagram

Datasheet Revision 3.4 09-Nov-2016

2 Pinout • Quad Flat Package No Leads (QFN) with 48 pins

Figure 2: WLCSP34 ball assignment XT

P0_4 6 DA14580 31 SW_CLK

Pin 0: GND plane

Figure 3: QFN48 Pin Assignment

Datasheet Revision 3.4 09-Nov-2016

Figure 4: QFN40 Pin Assignment

Table 1: Pin Description

Datasheet Revision 3.4 09-Nov-2016

Table 1: Pin Description

Datasheet Revision 3.4 09-Nov-2016

Table 1: Pin Description

Datasheet Revision 3.4 09-Nov-2016

Part Number Package Size (mm) Shipment Form Pack Quantity

Table 3: Ordering Information (Production)

Part Number Package Size (mm) Shipment Form Pack Quantity

Table 4: Ordering Information (Preprogrammed OTP)

Part Number Package Shipment Form Pack Quantity Description

Part Number Legend:

Datasheet Revision 3.4 09-Nov-2016

Datasheet Revision 3.4 09-Nov-2016

Table 5: OTP Header range of frequencies. However, this trimming is done

Datasheet Revision 3.4 09-Nov-2016

the status of these blocks and continues with the

Power Up Is it Power Up or Wake Up

Figure 6: General Startup Flow

The system will enter the Power/Wake-Up sequence

4.4.1 Power/Wake-Up Sequence

Datasheet Revision 3.4 09-Nov-2016

VBAT1V > 0.5V

Figure 7: Power/Wake-Up Sequence

4.4.2 OTP Mirroring

can be calibrated. In the second case, the BootROM

Figure 8: Wake-Up OTP Mirroring

The flow chart of Figure 8 assumes that the OTP con-

4.4.3 BootROM Sequence

Datasheet Revision 3.4 09-Nov-2016

Start copy of Boot from Ext SPI

Run patching function Boot from Ext SPI

Figure 9: BootROM Sequence

Datasheet Revision 3.4 09-Nov-2016

Datasheet Revision 3.4 09-Nov-2016

1. Active Mode: System is active and operates at

Datasheet Revision 3.4 09-Nov-2016

Sleep modes described in the previous section. These

Note 1: 1 kB = 1024 bytes. 1 Mbit = 10241024 bits. 1 GB = 10241024*1024 bytes.