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Lect 5

The document discusses the process of an assembler in two passes: 1) Pass 1 defines symbols and generates a symbol table. 2) Pass 2 generates machine code. It initializes a location counter, reads cards from Pass 1, looks up operation codes, evaluates operands, generates effective addresses, assembles instructions into proper formats, and increments the location counter for the next instruction. Pseudo-operations like EQU, USING, and DC are also processed.

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186 views8 pages

Lect 5

The document discusses the process of an assembler in two passes: 1) Pass 1 defines symbols and generates a symbol table. 2) Pass 2 generates machine code. It initializes a location counter, reads cards from Pass 1, looks up operation codes, evaluates operands, generates effective addresses, assembles instructions into proper formats, and increments the location counter for the next instruction. Pseudo-operations like EQU, USING, and DC are also processed.

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Lua
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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‫برمجة النظم‬

(٥) ‫محاضرة‬ ‫رابعة حاسب‬

‫ أحمد الحربي‬/‫دكتور‬

Assemblers ‫تابع‬

For each instruction in Pass 2, we create the equivalent machine

language instruction as shown below. For example, for statement 3:

LA 15, SETUP

.(6) ST ‫ في‬SETUP ‫ معرفة قيمة‬-١

.(binary op code for LA) MOT ‫ في‬op code ‫ معرفة قيمة‬-٢

:‫ كما يلي‬address ‫ تكوين‬-٣

.(15) ‫ وھو‬base register ‫ نحدد‬-

.(0) ‫ معرفة محتواه عند ھذه الخطوة ھو‬-

Offset = value of symbol – content of base register

=6–0=6

:‫ كما يلي‬address ‫يكون‬

Offset (index register, base register)

1
‫)‪6 (0, 15‬‬

‫‪ -‬بالمثل يتم تكوين ‪ addresses‬لباقي ‪ instructions‬في الكود‪.‬‬

‫‪Algorithm‬‬

‫األشكال ‪ 3.10-11‬تشرح ‪ PASS 1 & PASS 2‬للـ ‪ Assembler‬بشىء من التفصيل‪.‬‬


‫‪2‬‬
PASS 1: Defines symbols.

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PASS 2: GENERATE CODE

Pass 2 must structure the generated code into the appropriate

format for later processing by the loader. The Location Counter is

initialized as in pass 1, and the processing continues as follows.

• A card is read from the source file left by pass 1. As in pass 1.

• The operation code field is examined to specify if it is a pseudo-op.

• If it is not, the table of machine op-codes (MOT) is searched to find

a match for the card's op-code field.

• The matching MOT entry specifies the length, binary op-code, and

the format-type of the instruction.

• The operand fields of the different instruction format types require

somewhat different processing.

• For the RR format instructions, each of the two register

specification fields is evaluated.

• The two fields are inserted into their respective four-bit fields in the

second byte of the RR-instruction.

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• For RX-format instructions, the register and index fields are

evaluated and processed in the same way as the register

specifications for RR-format instructions.

• The storage address operand is evaluated to generate an Effective

Address (EA). Then the base register table (BT) must be examined

to find a suitable base register (B). The corresponding displacement

can then be determined.

• The 4-bit base register specification and 12-bit displacement fields

are then assembled into the third and fourth bytes of the instruction.

• Only the RR, SI and RX instruction types are explicitly shown in

the flowchart (Fig. 3.11). The other instructions are handled

similarly.

• After the instruction has been assembled, it is put into the

necessary format later processing by the loader.

• A listing line containing a copy of the source card, its assigned

storage location, and its hexadecimal representation is then printed.

• Finally, the location counter is incremented and processing is

continued with the next card.

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• As in pass 1, each of the pseudo-ops calls for special processing.

The EQU pseudo-op requires very little processing in pass 2,

because symbol definition was completed in pass 1. It is necessary

only to print the EQU card as part of the printed listing.

• The USING and DROP pseudo-ops, which were largely ignored in

pass 1, require additional processing in pass 2. The operand fields

of the pseudo-ops are evaluated; then the corresponding.

• Base Table entry is either marked as available, if USING, or

unavailable, if DROP. The base table is used extensively in pass 2

to compute the base and displacement fields for machine

instructions with storage operands.

• The DS and DC pseudo-ops are processed essentially as in pass 1.

• In pass 2, however, actual code must be generated for the DC

pseudo-op depending upon the data types specified; this involves

various conversions (e.g., floating point character to binary

representation) and symbol evaluations (e.g., address constants).

• The END pseudo-op indicates the end of the source program and

terminates the assembly. Various "housekeeping" tasks must how

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be performed. For example, code must be generated for any literals

remaining in the Literal Table (LT).

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