STW120CT

Computer Architecture and

Networks Processors
(Instruction Pipelining)
(Week 5)
 Processor
• A processor (CPU) is the logic circuitry that responds to and
processes the basic instructions that drive a computer.
• It interprets and executes machine level instructions
Basic Elements of Processor
1.ALU(Arithmetic and Logic Unit) : carries out arithmetic
and logic operations
2.FPU(Floating Point Unit) : manipulates numbers more
quickly than the basic microprocessor circuitry can
3.Registers : hold instructions and other data
4.L1 and L2 cache memory :
 Computer Components
• Von Neumann Architecture (discussed earlier) is based on
three key concepts:

1. Data and instructions are stored in a single read-write memory

2. The contents of this memory are addressable by location, without

regard to the type of data contained there

3. Execution occurs in a sequential fashion (unless explicitly modified)

from one instruction to the next

• An alternative to the von Neumann architecture is the Harvard

architecture
 Von Neumann Architecture
Memory

Backing
Control Unit Arithmetic Logic Unit (ALU) Storage
(not always
Accumulator included at
this level)

Input Output
Harvard Architecture
 Computer Components: Top Level
• A memory module
View
consists of a set of
locations, defined by
sequentially numbered
addresses. Each location
contains a binary
number that can be
interpreted as either an
instruction or data. An
I/O module transfers
data from external
devices to CPU and
memory, and vice versa.
It contains internal
buffers for temporarily
holding these data until
they can be sent on.
Processor
Organization
The processor must able to do:
•Fetch instruction: The processor reads an instruction from memory
(register, cache, main memory).
•Interpret instruction: The instruction is decoded to determine what action
is required.
•Fetch data: The execution of an instruction may require reading data from
memory or an I/O module.
•Process data: The execution of an instruction may require performing
some arithmetic or logical operation on data.
•Write data: The results of an execution may require writing data to
memory or an I/O module.
CPU with system
bus
• Give simplified view of processor
CPU internal
structure
Basic instruction
•cycle
Use the simplified two-step description
• The two steps are referred to as the fetch cycle and the execute cycle.
• At the beginning of each instruction cycle, the processor fetches an
instruction from memory.
• After an instruction has been interpreted, the processor performs
(executes) the required action
Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to
by PC
Increment PC
Unless told otherwise

Instruction loaded into the Instruction Register (IR)

Once the instruction has been fetched, the processor

interprets (decodes) the instruction and performs required
actions

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Execute Cycle
After an instruction has been interpreted, the processor performs (executes) the required
action. In general, these actions fall into the following four categories:

Processor-memory Transfer
Data transfer between CPU and main memory

Processor-I/O Transfer
Data transfer between CPU and I/O module

Data processing
Some arithmetic or logical operation on data

Control
Alteration of sequence of operations
e.g. jump

Combination of above
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 Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

• Most common classes of interrupts:

• Program Generated by some condition that occurs as a result of an
instruction execution, such as arithmetic overflow, division by zero,
attempt to execute an illegal machine instruction, or reference outside a
user’s allowed memory space.
• Timer Generated by a timer within the processor. This allows the operating
system to perform certain functions on a regular basis.
• I/O Generated by an I/O controller, to signal normal completion of an
operation, request service from the processor, or to signal a variety of error
conditions.
• Hardware Failure Generated by a failure such as power failure or memory
parity error.
Instruction
•cycle
An instruction cycle includes the following stages:
• Fetch: Read the next instruction from memory into the processor.
• Execute: Interpret the opcode and perform the indicated operation.
•Interrupt: If interrupts are enabled and an interrupt has occurred,
save the current process state and service the interrupt.
 Instruction Cycle with
•Interrupts
To accommodate interrupts, an interrupt cycle is added to the
instruction cycle.
• In the interrupt cycle, the processor checks to see if any interrupts
have occurred, indicated by the presence of an interrupt signal.
Multiple interrupts
• Two approaches can be taken to dealing with multiple interrupts:
• The first is to disable interrupts while an interrupt is being processed.
• A second approach is to define priorities for interrupts and to allow an
interrupt of higher priority to cause a lower-priority interrupt handler to be
itself interrupted
 Register
•organization
Within the processor there is a set of register that function as level of memory
above main memory and cache in the hierarchy
• The registers in the processor perform two roles:
• User-visible registers: Enable the machine- or assembly language programmer to minimize
main memory references by optimizing use of registers. These registers can be divided into:
• General purpose,
• Data,
• Address,
• Condition codes
• Control and status registers: Used by the control unit to control the operation of the
processor and by privileged, operating system programs to control the execution of
programs. These are also further divided into:
• Program counter (PC):
• Instruction register (IR):
• Memory address register (MAR):
• Memory buffer register (MBR):
Program Status Word
(PSW)
• Contain status information
• Common fields or flags include the following:
• Sign Flag (bit 7): Contains the sign bit of the result of the last arithmetic operation. 0 for
positive, and 1 for negative number
• Zero Flag (bit 6): Set when the result is 0.
• Carry Flag (bit 0): Set if an operation resulted in a carry (addition) into or borrow
(subtraction) out of a high-order bit. Used for multiword arithmetic operations.
• Equal: Set if a logical compare result is equality.
• Overflow Flag (bit 11): Used to indicate arithmetic overflow.
• Interrupt Enable/Disable: Used to enable or disable interrupts.
• Supervisor: Indicates whether the processor is executing in supervisor or user mode.
Other status flags include:
Parity flag (bit 2): If LSB of result is even number of 1, set parity flag
Adjust flag (bit 4): set if arithmetic operation generate carry or borrow out of 3 bits results. Commonly
used in BCD
Pipelining
Strategy
• New inputs are accepted at one end
before previously accepted inputs
appear as outputs at the other end.
• The pipeline has two independent
stages.
• The first stage fetches an instruction and
buffers it.
• The second stage is executing the
instruction
• With pipelining, a processor
can
simultaneously work on
multiple
instructions. The processor
overlaps
operations by moving data or
instructions into a conceptual
pipe with
all stages of the pipe processing
simultaneously. For example,
while one
Instruction processing can be decomposed
into:
• Fetch instruction (FI): Read the next expected instruction into a buffer.
• Decode instruction (DI): Determine the opcode and the operand specifiers.
• Calculate operands (CO): Calculate the effective address of each source
operand.
• Fetch operands (FO): Fetch each operand from memory. Operands in
registers need not be fetched.
• Execute instruction (EI): Perform the indicated operation and store the
result, if any, in the specified destination operand location.
• Write operand (WO): Store the result in memory.
Pipeline
Hazards
• A pipeline hazard occurs when the pipeline, or some portion of the
pipeline, must stall because conditions do not permit continued
execution. There are three types of hazards:
• Resource: occurs when two (or more) instructions that are already in the
pipeline need the same resource,
• Data: occurs when there is a conflict in the access of an operand
location, and
• Control: occurs when the pipeline makes the wrong decision on a branch
prediction.
Superscalar processors
• Superscalar approach is the ability to execute instructions
independently and concurrently in different pipelines.
• The concept can be further exploited by allowing instructions to be
executed in an order different from the program order.
Instruction level
parallelism
• Refers to the degree to which the instructions of a program can be
executed in parallel
• A combination of compiler based optimisation and hardware
techniques can be used to maximise instruction level parallelism

• Demerits:
• True data dependency
• Procedural dependency
• Resource conflicts
• Output dependency
• Antidependency
References
• Computer Organization and Architecture – Designing for Performance (10th
Edition), William Stallings

• Computer Organization and Design – The Hardware/Software Interface (5th

Edition), David A. Patterson & John L. Hennessy