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Ec0033-Asic Design-Model Qp-Vii Sem

This document contains exam questions for an ASIC design course. It asks students to complete tasks related to VHDL modeling, logic synthesis, fault modeling, placement and routing algorithms. Specifically, questions 14a and 14b ask students to apply the D-algorithm to determine a test vector for an SA1 fault shown in a figure, and define built-in self-test (BIST) components. Question 15a asks students to apply the Karnaugh-La algorithm to find the minimum cut cost shown in another figure.

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131 views1 page

Ec0033-Asic Design-Model Qp-Vii Sem

This document contains exam questions for an ASIC design course. It asks students to complete tasks related to VHDL modeling, logic synthesis, fault modeling, placement and routing algorithms. Specifically, questions 14a and 14b ask students to apply the D-algorithm to determine a test vector for an SA1 fault shown in a figure, and define built-in self-test (BIST) components. Question 15a asks students to apply the Karnaugh-La algorithm to find the minimum cut cost shown in another figure.

Uploaded by

skarthikpriya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Reg. No. 13 a.

Write a Synthesizable memory model in VHDL


(OR)
SRM UNIVERSITY b. Write short notes on various types of simulation

VADAPALANI CAMPUS 14 a. Determine the Test vector for SA1 fault shown below in figure1 using
D algorithm
MODEL EXAMINATION – OCT 2016 (OR)
b. What is BIST? Explain the various components associated with it.
Seventh Semester – Electronics and Communication Engineering
15 a. Apply KL algorithm for figure2 and find the minimum cut cost
PEC0033 – ASIC DESIGN (OR)
Duration: 3 Hrs Max. Marks: 100 b. With an example explain left edge channel routing algorithm and Lee
maze routing
PART – A (10 X 2 = 20 Marks)
Answer ALL Questions
X
1. Size a 3 input NOR gate to achieve equal rise time and fall time
2. Design a XOR gate using Transmission gates
3. Draw ACT1 logic module B
Y
4. What is shanon’s expansion theorem/Lexpander
5. List different types of FSM Synthesis/Different encoding
6. What is logic mapping / optimization Z
7. Draw a boundary scan cell/Types of Fault modeling C
8. Find the test vector for SA1 at the output of 2 input NAND gate/Various Figure1
faults
9. What are the objectives of placement/Partitioning
10. What is the goal of detail routing/

PART – B (5 X 16= 80 Marks)


Answer ALL questions

11. a. Explain the various ASIC design approaches


(OR)
b. Implement D latch ,DFF using Transmission gates. Figure2

12. a. Draw and explain the features of XILINX XC3000 architecture


(OR)
b. Draw and explain the features of Altera Flex architecture

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