Points Addressed in this Lecture

• Read-only memory
• Implementing logic with ROM
Lecture 8: ROM & Programmable Logic Devices • Programmable logic devices
Professor Peter Cheung
• Implementing logic with PLDs
Department of EEE, Imperial College London • Static hazards
(Floyd 10.1,10.3-5, 11.1-11.3)
(Tocci 12.1, 12.4-5, 13.1-13.4)

E1.2 Digital Electronics I 8.1 Nov 2007 E1.2 Digital Electronics I 8.2 Nov 2007

Memory Terminology

• Memory Cell: circuit that stores 1-bit of information

• Memory Word: 8 – 64 bits
• Byte: a group of 8 bits
• Capacity (=Density)
- 4096 20-bit words
= 81,920 bits = 4096*20 = 4K*20
- 1 M or 1 meg = 220
- 1 G or 1 giga = 230
• Address
• Read Operation (=fetch operation)
• Write Operation (=store operation)

E1.2 Digital Electronics I 8.3 Nov 2007 E1.2 Digital Electronics I 8.4 Nov 2007
 A ROM Device
Read-only Memory (ROM) – E.g. 64x1 bit ROM +5 Volts

• A ROM cell can store 1 bit of information

BIN/1 of 8
• Data can be read but not changed (written) 0 8 16 24 32 40 48 56

– RAM is read-write capable 1 9 17 25 33 41 49 57

• ROM is non-volatile A0
2 10 18 26 34 42 50 58

– the data is "remembered" even when the power supply to the A1

3 11 19 27 35 43 51 59

chip is turned off 4 12 20 28 36 44 52 60

A2
– the data can be read after turning the power on again 5 13 21 29 37 45 53 61

– RAM is volatile 6 14 22 30 38 46 54 62

• Applications 7 15 23 31 39 47 55 63
MUX
– permanent storage of programmes for micro-processors A3 7
. OUT
.
– look-up tables of data A4 .
0

– implementing combinational logic A5 .} G

0 0
_
2 7

E1.2 Digital Electronics I 8.5 Nov 2007 E1.2 Digital Electronics I 8.6 Nov 2007

A ROM Cell

• Notes e
Row

rag
– 6 address inputs - half for row select, half for column Sto
0 or 1 Column
select
– row select energises all the switch transistors in one
row • A voltage is stored to represent a 0 or 1 as
– column select uses a multiplexer to select just one required
column
• If the “row-line” is addressed, the switch closes
– outputs are normally high but "pulled down" if a cell is
and the stored voltage appears on the “column-
programmed
line”
• The switch is implemented with a (MOS)
transistor
E1.2 Digital Electronics I 8.7 Nov 2007 E1.2 Digital Electronics I 8.8 Nov 2007
 Storage Mechanism • Field Programmable ROM (PROM)
– programmable using a PC-based system
• The storage mechanism for the 0 or 1 depends on the – a semiconductor fuse is blown to program a cell to 1
design of the ROM
• Electrically Erasable Programmable ROM (EEPROM)
• Mask Programmed ROM – programmable using a PC-based system
– the mask programmed ROM is programmed at the time of – the gate capacitance of a MOS transistor is charged
manufacture (electrically) to store a 0 or discharged (electrically) to store
– the switch transistor is made to have a low threshold voltage to a1
program a 0 and a high threshold to program a 1 Row-line Row-line

Row-line
'0'
'0' Column-line Column-line
‘0’ Column-line
PROM Cell EPROM Cell

Mask Progammed Cell

E1.2 Digital Electronics I 8.9 Nov 2007 E1.2 Digital Electronics I 8.10 Nov 2007

Implementing Logic with ROM

Different ROM technology
n
• 2 x 1-bit ROM devices have n inputs and 1 output
– they can be used to implement logic directly
– E.g. OUT = X.Y+Z
X Y Z OUT
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

– Programme the first 8 addresses according to the OUT column

– Connect X to A2, Y to A1 and Z to A0 of the ROM
– Usually "cheaper" than using gates for complex logic involving
many variables

E1.2 Digital Electronics I 8.11 Nov 2007 E1.2 Digital Electronics I 8.12 Nov 2007
 Programmable Logic Devices (PLDs) • PALs are programmed
like PROMs using fuses
• Several different "architectures" available – one-time programmable

– We will focus only on PAL and CPLD • CPLDs are programmed

like EEPROMs
• PALs and CPLDs are examples of PLDs – Electrically erasable
– PAL: Programmable Array Logic • PLAs
– CPLD: Complex Programmable Logic Device – Devices with
– implement SOP expressions in canonical form programmable AND and
programmable OR
– made from a Programmable AND section and a Fixed OR
section
– typically can implement 8 product terms

E1.2 Digital Electronics I 8.13 Nov 2007 E1.2 Digital Electronics I 8.14 Nov 2007

PAL Architecture Detail of AND Gates in PALs

A0 A1 A2 A3 A4 A5 A6 A7 4 bit example
&
f = A 0. A1. A 3 + "
&

&
>1 &
&
f
& ≥1 f
&

& 1 1 1 1

&
A0 A1 A2 A3
A0 A1 A2 A3 A4 A5 A6 A7
other inputs not shown
f = A 0. A1. A 2. A 4. A 6 + A1. A 3. A 4
E1.2 Digital Electronics I 8.15 Nov 2007 E1.2 Digital Electronics I 8.16 Nov 2007
 Summary of Combinational Logic Building Blocks • Arithmetic Circuits
– binary adders, comparators, multipliers
• Gates
– issues of signed or unsigned number representation are
– seven basic gates from which all other circuits are made important
– AND/NAND, OR/NOR, XOR/XNOR, NOT
• Programmable Logic Devices
• Multiplexers – ROMs
– act as switches to connect one output to one of a number of • implement arbitrary logic functions
input signals • efficient for large combination logic circuits
– can also be used to implement logic – CPLDs
• Decoders • implement canonical SOP Boolean expressions
– inverted multiplexers (sometimes called demultiplexers) – Advantages:
– act as switches to connect one input to one of a number of • reduction in chip count
output signals • easy upgrade by just reprogramming
– also includes circuits such as Binary to 7 Segment decoders – Disadvantages
– four to seven bit decoders • programming equipment required
• non-standard parts to stock and document
E1.2 Digital Electronics I 8.17 Nov 2007 E1.2 Digital Electronics I 8.18 Nov 2007

Static Hazards Avoid Static Hazards

• Gates have finite propagation delay
– This can cause glitches in logic waveforms • Using a Karnaugh map, look for groups of minterms which do NOT
• Consider an inverter overlap
– These are potential hazards
– propagation delay of ~2nS
• Avoid the hazard by introducing additional groups so that no non-
• E.g. Implementation of f ( A , B , C ) = A B + AC overlapping groups remain
A\BC 00 01 11 10
– If we use an inverter to generate A from A then changes in A 0 1 1
will be later than changes in A . 1 1 1
B & A • Groups are AC + AB which do not overlap
A
>1 f – Potential hazard
1 A
& • Introduce the additional term BC to avoid the hazard
C Td
A C + AB + BC

E1.2 Digital Electronics I 8.19 Nov 2007 E1.2 Digital Electronics I 8.20 Nov 2007