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Vlsi Btech List New

This document lists 51 potential VLSI BTECH project topics. The topics include designs of reversible circuits, multipliers, noise cancellation algorithms, I2C/SPI interfaces, CORDIC algorithms, BCD multiplication, digital filters, FFT processors, error detection, test pattern generation, FIR filters, UART implementations, VLIW processors, traffic light controllers, AES encryption, and reconfigurable cryptographic processors, among other topics related to digital circuits and systems. The projects involve designing and implementing circuits and algorithms using technologies like FPGA, Verilog HDL, and VLSI.

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62 views4 pages

Vlsi Btech List New

This document lists 51 potential VLSI BTECH project topics. The topics include designs of reversible circuits, multipliers, noise cancellation algorithms, I2C/SPI interfaces, CORDIC algorithms, BCD multiplication, digital filters, FFT processors, error detection, test pattern generation, FIR filters, UART implementations, VLIW processors, traffic light controllers, AES encryption, and reconfigurable cryptographic processors, among other topics related to digital circuits and systems. The projects involve designing and implementing circuits and algorithms using technologies like FPGA, Verilog HDL, and VLSI.

Uploaded by

Green India Technologies
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI BTECH PROJECT LIST

1. Design of Testable Reversible Sequential Circuits


2. FPGA implementation of high speed 8 bit vedic multiplier using
Barrel shifter
3. Design and implementation of 32 bit unsigned multiplier using
CLAA and CSLA
4. Design and Implementation of Adaptive filtering algorithm for
Noise Cancellation in speech signal on FPGA
5. Design of an I2C and SPI interface using Verilog HDL
6. Low power Square and Cube Architectures Using Vedic Sutras
7. Design of efficient Floating-Point Fused Add-Subtract Unit using
Carry select adder
8. Design of power optimized BIST logic for UART using Verilog
9. Design of Low Power Comparator Circuit Based on Reversible
Logic Technology
10. Power optimization of LBIST for Feedback Shift Register
11. Optimized area and power of a DS-CDMA Implementation
With Iterative MAI Cancellation
12. Design and implementation of a low power Self-Motivated
Arbitration Scheme for the AHB Bus
13. Design and implementation of a Wide-Range PLL Using
Self-Healing Pre – scaler /VCO
14. An high performance FFT processor design using CORDIC
algorithm
15. Design of Area and speed efficient BCD Multiplication
Using Verilog HDL
16. An area optimized Digital filter using Distributive Arithmetic
based on FPGA
17. FPGA Implementation of Sine and Cosine Generators using
CORDIC Algorithm
18. Achieving Reduced area by Multi-Bit flip flop design.
19. BER Analysis and MAl Cancellation in CDMA
Communication System.
20. Concurrent Error Detection for Orthogonal Latin Squares
Encoders and Syndrome Computation.
21. Design of Digit-Serial FIR Filters Algorithms Architectures,
and a CAD Tool.
22. Design of Low Power Test Pattern Generator using Low
Transition LFSR for high Fault Coverage Analysis.
23. Low-Cost FIR Filter Designs Based on Faithfully Rounded
Truncated Multiple Constant Multiplication Accumulation.
24. Reduction of Power Consumption using Multi bit flip flops.
25. Security-Enabled Near-Field Communication Tag With
Flexible Architecture Supporting Asymmetric Cryptography
26. VHDL Implementation of UART with Status Register
27. A self checking approach for SEUMBUS hardened FSMs
design based on the replication of one-hot code.
28. An On-Chip Delay Measurement Technique Using Signature
Registers for Small-Delay Defect Detection.
29. Design and Implementation of 64-Bit Execute Stage for
VLIW Processor Architecture on FPGA.
30. Design of Low Power TPG Using LP-LFSR.
31. Efficient FPGA Implementation of Steerable Gaussian
smoothers.
32. FFT Implementation with Fused Floating-Point Operations
33. High speed Modified Booth Encoder multiplier for signed
and unsigned numbers.
34. Design and simulation of Low power and area efficient Carry
Select Adder.
35. Design and Test of General-Purpose SPI Master Slave IPs
on OPB Bus.
36. FPGA Implementation of Pipelined 2D DCT and
Quantization Architecture for JPEG Image Compression
37. FPGA-based for Implementation of Multi-Serials to Ethernet
Gateway.
38. High performance and low power VLSI architecture of
Viterbi decoder using asynchronous QDI techniques.
39. Implementation of BIST Capability using LFSR Techniques
in UART.
40. Power Optimization of Linear Feedback Shift Register
(LFSR) for Low Power BIST.
41. Product Reed Solomon Codes for Implementing NAND
Flash Controller on FPGA chip.
42. Design and analysis of low density parity check encoder for
fixed and mobile communication systems.
43. Design and Implement of FFT Processor for OFDMA
System Using FPGA.
44. Design and development of Traffic light controller on FPGA
45. Design and implementation of Finite Impulse Response
filters on FPGA.
46. Design and simulation of an Adaptive Huffman Decoding
Algorithm for MP3.
47. A Compact AES Encryption Core on Xilinx FPGA.
48. An On-Chip AHB Bus Tracer With Real-Time Compression
and Dynamic Multi resolution Supports for SoC.
49. A Low-power Variable-length FFT Processor Base on
Radix-24 Algorithm.
50. A High-Performance Unified-Field Reconfigurable
Cryptographic Processor.
51. A Fast Hardware Approach for Approximate Efficient
Logarithm and Antilogarithm Computations.

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