Lecture 7

Memory and Array Circuits

Konstantinos Masselos
Department of Electrical & Electronic Engineering
Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostas
E-mail: [email protected]

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 1
 Based on slides/material by…

‹ J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
“Digital Integrated Circuits: A Design Perspective”, Prentice Hall

‹ D. Harris http://www.cmosvlsi.com/coursematerials.html
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems
Perspective”, Addison Wesley

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 2
 Recommended Reading

‹ J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”:

Chapter 12

‹ Weste and Harris, “CMOS VLSI Design: A Circuits and Systems

Perspective”: Chapter 11

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 3
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 4
 Semiconductor Memory Classification

RWM NVRWM ROM

Random Non-Random
EPROM Mask-Programmed
Access Access
E 2 PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 5
 Memory Arrays

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory Read Only Memory

Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)

Serial In Parallel In First In Last In

Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM

ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 6
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 7
 Memory Architecture: Decoders

M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 Word 2
N Words

Cell A1 Cell

Decoder
A K -1
S N-2
Word N-2 Word N-2
S N_ 1
Word N-1 Word N-1

Input-Output Input-Output
(M bits) (M bits)

N words => N select signals Decoder reduces # of select signals

Too many select signals K = log 2 N

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 8
 Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

2 L- K Bit Line
Storage Cell

AK
AK+1 Row Decoder Word Line

AL -1

M.2 K

Sense Amplifiers / Drivers Amplify swing to

rail-to-rail am plitude

A0
Column Decode r Selects appropriate
A K -1 word

Input-Output
(M bits)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 9
 Hierarchical Memory Architecture

Row
Address

Column
Address

Block
Address

Global Data Bus

Control Block Selector Global
Circuitry Am plifier/Driver

I/O

Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 10
 Memory Timing: Definitions

Read Cycle

READ

Read Access Read Access Write Cycle

WRITE

Write Access
Data Valid

DATA

Data Written

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 11
 Memory Timing: Approaches

MSB LSB

Address
Row Address Colum n Address
Bus

RAS Address
Address
Bus

Address transition
CAS initiate s memor y operation

RAS-CAS timing

DRAM Timing SRAM Timing

Multiplexed Adressing Self-timed

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 12
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 13
 Read-Only Memories

‹ Read-Only Memories are nonvolatile

• Retain their contents when power is removed
‹ Mask-programmed ROMs use one transistor per bit
• Presence or absence determines 1 or 0

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 14
 ROM Example

‹ 4-word x 6-bit ROM Word 0: 010101

• Represented with dot diagram Word 1: 011001
• Dots indicate 1’s in ROM
Word 2: 100101
weak
pseudo-nMOS Word 3: 101010
A1 A0
pullups

2:4
DEC

ROM Array

Y5 Y4 Y3 Y2 Y1 Y0

Looks like 6 4-input pseudo-nMOS NORs

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 15
 MOS NOR ROM

V DD
Pull-up devices

WL[0]
GND
WL[1]

WL[2]
GND
WL[3]

BL[0] BL[1] BL[2] BL[3]

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 16
 MOS NOR ROM Layout

Metal1 on top of diffusion

WL[0]
G ND (diffusion)
WL[1]
Polysilicon
B asic cell
10 λ x 7 λ M etal1

WL[2] 2λ

WL[3]

Only 1 layer (contact mask) is used to program memory array

Programming of the memory can be delayed to one of
last process steps

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 17
 MOS NOR ROM Layout

BL[0] BL[1] BL[2] BL[3]

Threshold raising
implant

WL[0]
GND (diffusion)
Basic Cell
8.5 λ x 7 λ
Metal1 over diffusion
WL[1]

Polysilicon
WL[2]

WL[3]

Threshold raising implants disable transistors

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 18
 MOS NAND ROM

V DD

Pull-up devices

BL[0] BL [1] BL[2] BL[3]

WL[0]

WL[1]

WL[2]

WL[3]

All word lines high by default with exception of selected row

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 19
 MOS NAND ROM Layout

Diffusion

Polysilicon

Basic cell

5λx6λ

Threshold

lowering

implant

No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 20
 Precharged MOS NOR ROM

VD D
φ p re
Precharge devices

WL[0]
GND
WL[1]

WL[2]
GND
WL[3]

BL[0] BL[1] BL[2] BL[3]

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 21
 Building Logic with ROMs

‹ Use ROM as lookup table containing truth table

• n inputs, k outputs requires 2n words x k bits
• Changing function is easy – reprogram ROM
‹ Finite State Machine
• n inputs, k outputs, s bits of state
• Build with 2n+s x (k+s) bit ROM and (k+s) bit reg

inputs
n ROM Array
2n wordlines

inputs outputs
DEC

n ROM k k
s s
state
k outputs

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 22
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 23
 Nonvolatile Read-Write Memories (NVRW)

‹ Architecture virtually identical to the ROM structure

• the memory core consists of an array of transistors placed on a word-line/bit-
line grid
‹ The memory is programmed by selectively disabling or enabling some of
those devices
• in a ROM this is accomplished by mask level alterations
• in a NVRW memory a modified transistor that permits its threshold to be
altered electrically is used instead – the modified threshold is retained
indefinitely (or long) even when the supply voltage is turned off
‹ To reprogram the memory the programmed values must be erased after
which a new programming round can be started
• The method of erasing is the main differentiating factor between the various
classes of reprogrammable non volatile memories
• The programming of the memory is typically an order of magnitude slower
than the reading operation

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 24
 PROMs and EPROMs

‹ Programmable ROMs
• Build array with transistors at every site
• Burn out fuses to disable unwanted transistors
‹ Electrically Programmable ROMs
• Use floating gate to turn off unwanted transistors
• EPROM, EEPROM, Flash

Source Gate Drain Polysilicon

Floating Gate
Thin Gate Oxide
(SiO2)

n+ n+

p bulk Si

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 25
 Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
+ p +
n n
Substrate

(a) Device cross-section (b) Schematic symbol

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 26
 Floating-Gate Transistor Programming

20 V 0V 5V

20 V 0V 5V
10 V→ 5 V −5 V − 2.5 V

S D S D S D

Avalanche injection. R emoving programm ing voltage Programm ing results in

leaves charge trapped. higher V T .

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 27
 Characteristics of Non Volatile Memories

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 28
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 29
 Read-Write Memories (RAM)

• STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

• DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 30
 6-transistor CMOS SRAM Cell

WL

V DD
M2 M4
Q
Q M6
M5

M1 M3

BL BL

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 31
 SRAM Read/Write

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 32
 CMOS SRAM Analysis (Read)

‹ Precharge both bitlines high

‹ Then turn on wordline
‹ One of the two bitlines will be pulled down by the cell
‹ Ex: A = 0, A_b = 1 bit bit_b
• bit discharges, bit_b stays high word

• But A bumps up slightly N2

P1 P2
N4
‹ Read stability A A_b
• A must not flip N1 N3

• N1 >> N2
A_b bit_b

1.5

1.0
word bit

0.5

A
0.0
0 100 200 300 400 500 600
time (ps)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 33
 CMOS SRAM Analysis (Write)

‹ Drive one bitline high, the other low

‹ Then turn on wordline
‹ Bitlines overpower cell with new value
bit bit_b
‹ Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 word
• Force A_b low, then A rises high P1 P2
N2 N4
‹ Writability
A A_b
• Must overpower feedback inverter N1 N3
• N2 >> P1

A_b

1.5 A

bit_b
1.0

0.5
word

0.0
0 100 200 300 400 500 600 700
time (ps)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 34
 SRAM Sizing

‹ High bitlines must not overpower inverters during reads

‹ But low bitlines must write new value into cell

bit bit_b
word
weak
med med
A A_b
strong

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 35
 6T-SRAM — Layout

VDD
M2 M4

Q Q

M1 M3

GND
M5 M6 WL

BL BL

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 36
 Resistance-load SRAM Cell

WL

VD D

RL RL

Q Q
M3 M4

BL M1 M2 BL

Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 37
 Multiple Ports

‹ We have considered single-ported SRAM

• One read or one write on each cycle
‹ Multiported SRAM are needed for register files
‹ Examples:
• Multicycle MIPS must read two sources or write a result on some cycles
• Pipelined MIPS must read two sources and write a third result each cycle
• Superscalar MIPS must read and write many sources and results each cycle

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 38
 Dual-Ported SRAM

‹ Simple dual-ported SRAM

• Two independent single-ended reads
• Or one differential write

bit bit_b
wordA
wordB

‹ Do two reads and one write by time multiplexing

• Read during ph1, write during ph2

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 39
 True dual port SRAM

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 40
 Multi-Ported SRAM

‹ Adding more access transistors hurts read stability

‹ Multiported SRAM isolates reads from state node
‹ Single-ended design minimizes number of bitlines
bA bB bC bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG

write
circuits

read
circuits

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 41
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 42
 3-Transistor DRAM Cell

BL1 BL2

WWL WWL

RWL
RWL

X V DD -V T
X M3
M2
M1 V DD
BL1
CS

BL2 V DD -V T ΔV

No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = VW W L -V T n

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 43
 3T-DRAM — Layout

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 44
 1-Transistor DRAM Cell

BL
WL Write "1" R ead "1"
WL

M1 CS X GN D V DD − V T

VD D
BL
V D D /2 V DD /2
C BL sensing

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
Δ V = V B L – V PR E = ( V B I T – V PR E ) ------------------------
C +C S BL

Voltage swing is small; typically around 250 mV.

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 45
 DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to

charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than V D D .

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 46
 1-T DRAM Cell

Capacitor

Metal word line

M1 word
SiO2 line
poly
Field Oxide
n+ n+
Inversion layer Diffused
poly induced by bit line
plate bias
Polysilicon
Polysilicon
plate
(a) Cross-section gate

(b) Layout

Used Polysilicon-Diffusion Capacitance

Expensive in Area

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 47
 Advanced 1T DRAM Cells

Word line
Cell plate Capacitor dielectric layer
Insulating Layer

Cell Plate Si

Capacitor Insulator Transfer gate Isolation

Refilling Poly Storage electrode

Storage Node Poly

Si Substrate
2nd Field Oxide

Trench Cell Stacked-capacitor Cell

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 48
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 49
 Periphery

‹ Decoders

‹ Sense amplifiers

‹ Input/output buffers

‹ Control/timing circuit

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 50
 Row Decoders

Collection of 2M complex logic gates

Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 51
 A NAND Decoder using 2-input Pre-Decoders

WL 1

WL 0

A 0A 1 A 0 A 1 A 0 A 1 A 0A 1 A 2A 3 A 2 A 3 A 2 A 3 A 2 A 3

A1 A 0 A0 A1 A3 A2 A2 A3

Splitting decoder into two or more logic layers

produces a faster and cheaper implementation

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 52
 Dynamic Decoders

Precharge devices GND GND

VDD

WL 3
WL 3 VDD

WL 2
WL 2 VDD

WL 1 WL 1
VDD

WL 0 WL 0

VDD φ A0 A0 A1 A1 A0 A0 A1 A1 φ

Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder

Propagation delay is primary concern

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 53
 4 input Pass-Transistor based Column Decoder

BL 0 BL 1 BL 2 BL 3

S0

2 input NOR decoder

A0
S1

S2

A1
S3

Advantage: speed (t pd does not add to overall memory access time)

only 1 extra transistor in signal path
Disadvantage: large transistor count

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 54
 4-to-1 Tree based Column Decoder

BL 0 BL 1 BL 2 BL 3

A0

A0

A1

A1

D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 55
 Decoder for Circular Shift-Register

V DD V DD V DD V DD V DD V DD

WL 0 WL 1 WL 2
φ φ φ φ φ φ
...
R φ φ R φ φ R φ φ
V DD

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 56
 Sense Amplifiers

make ΔV as small
C ⋅ ΔV as possible
tp = ----------------
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 57
 Differential Sensing - SRAM

VDD VDD
V DD PC VDD
y M3 M4 y

x M1 M2 x x x
BL BL
EQ
SE M5 SE

WLi
(b) Doubled-ended Current Mirror Amplifier

VDD
SRAM cell i
y y
Diff.
x Sense x x x
Amp
y y
D D SE

(a) SRAM sensing scheme.

(c) Cross-Coupled Amplifier

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 58
 Latch-Based Sense Amplifier

EQ
BL BL
VD D

SE

SE

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 59
 Single-to-Differential Conversion

WL
BL
x Diff. x

+
S.A. _ V re f
cell

y y

How to make good V ref?

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 60
 Open Bitline Architecture

EQ

R L1 L0 R0 R1 L
VDD
SE

BLL BLR

... ...
CS CS CS SE CS CS CS

dum my dummy
cell cell

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 61
 DRAM Read Process with Dummy Cell

6.0

4.0
V (Volt)

BL
2.0 BL
5.0
0.0 0 4.0 WL
1 2 3 4 5

V (Volt)
t (nsec) 3.0 SE
(a) reading a zero
2.0 EQ
6.0 1.0
0.00 1 2 3 4 5
4.0
V (Volt)

(c) control signals

BL
2.0 BL

0.0 0 1 2 3 4 5
t (nsec)
(b) reading a one

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 62
 Single-Ended Cascode Amplifier

VDD

V cas c

WLC

WL

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 63
 DRAM Timing

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 64
 Address Transition Detection

V DD

DELAY
A0 td
ATD A TD

DELAY
A1 td

...
DELAY
A N-1 td

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 65
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 66
 Content Addressable Memories (CAMs)

‹ Extension of ordinary memory (e.g. SRAM)

• Read and write memory as usual
• Also match to see which words contain a key

adr data/key

read
CAM match
write

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 67
 CAM Cell Operation

‹ Read and write like ordinary SRAM

‹ For matching:
• Leave wordline low
• Precharge matchlines CAM cell

• Place key on bitlines clk weak

• Matchlines evaluate miss

row decoder
address match0

‹ Miss line
match1
• Pseudo-nMOS NOR of match lines
• Goes high if no words match match2

match3
read/write column circuitry
data

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 68
 10T CAM Cell

‹ Add four match transistors to 6T SRAM

bit bit_b
word
cell

cell_b

match

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 69
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 70
 Serial Access Memories

‹ Serial access memories do not use an address

• Shift Registers
• Tapped Delay Lines
• Serial In Parallel Out (SIPO)
• Parallel In Serial Out (PISO)
• Queues (FIFO, LIFO)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 71
 Shift Register

‹ Shift registers store and delay data

‹ Simple design: cascade of registers
• Watch your hold times!

clk

Din Dout
8

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 72
 Denser Shift Registers

‹ Flip-flops aren’t very area-efficient

‹ For large shift registers, keep data in SRAM instead
‹ Move read/write pointers to RAM rather than data
• Initialize read address to first entry, write to last
• Increment address on each cycle

Din
clk

readaddr
counter

00...00
dual-ported
SRAM
counter

writeaddr
11...11

reset
Dout

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 73
 Tapped Delay Line

‹ A tapped delay line is a shift register with a programmable number of

stages
‹ Set number of stages with delay controls to mux
• Ex: 0 – 63 stages of delay

clk
SR32

SR16

SR8

SR4

SR2

SR1
Din Dout

delay5 delay4 delay3 delay2 delay1 delay0

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 74
 Serial In Parallel Out

‹ 1-bit shift register reads in serial data

• After N steps, presents N-bit parallel output

clk

Sin

P0 P1 P2 P3

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 75
 Parallel In Serial Out

‹ Load all N bits in parallel when shift = 0

• Then shift one bit out per cycle

P0 P1 P2 P3
shift/load
clk

Sout

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 76
 Queues

‹ Queues allow data to be read and written at different rates.

‹ Read and write each use their own clock, data
‹ Queue indicates whether it is full or empty
‹ Build with SRAM and read/write counters (pointers)

WriteClk ReadClk

WriteData Queue ReadData

FULL EMPTY

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 77
 FIFO, LIFO Queues

‹ First In First Out (FIFO)

• Initialize read and write pointers to first element
• Queue is EMPTY
• On write, increment write pointer
• If write almost catches read, Queue is FULL
• On read, increment read pointer
‹ Last In First Out (LIFO)
• Also called a stack
• Use a single stack pointer for read and write

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 78
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Content Addressable Memory (CAM)
‹ Serial access memories
‹ Programmable Logic Arrays
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 79
 Programmable Logic Array

Pr oduct Terms

x0x1
A ND x2 OR
PLA NE PLA NE

f0 f1

x0 x1 x2

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 80
 PLAs

‹ A Programmable Logic Array performs any function in sum-of-products

form.
‹ Literals: inputs & complements
‹ Products / Minterms: AND of literals AND Plane OR Plane

‹ Outputs: OR of Minterms bc
ac
ab
‹ Example: Full Adder

Minterms
abc
abc
s = abc + abc + abc + abc abc
abc
cout = ab + bc + ac

a b c s cout
Inputs Outputs

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 81
 NOR-NOR PLAs

‹ ANDs and ORs are not very efficient in CMOS

‹ Dynamic or Pseudo-nMOS NORs are very efficient
‹ Use DeMorgan’s Law to convert to all NORs

AND Plane OR Plane AND Plane OR Plane

bc bc
ac ac
ab ab
abc abc
abc abc
abc abc
abc abc

a b c a b c
s cout s cout

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 82
 Pseudo-Static PLA

VD D
GND GND GND GND
GND

GND

GND

VDD f0 f1
x0 x0 x1 x1 x2 x2

AND-PLANE OR-PLANE

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 83
 PLA Schematic & Layout

AND Plane OR Plane

bc
ac
ab
abc
abc
abc
abc

a b c
s cout

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 84
 Dynamic PLA

φ A ND

GND VDD
φ OR

φO R
φAND
V DD f0 f1 GND
x0 x0 x1 x1 x2 x2

AND-PLANE O R-PLANE

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 85
 Clock Signal Generation for self-timed dynamic PLA

φ φ φ AN D

Dummy AND Row

φAN D

φAN D φOR
Dummy AND Row

φOR

(a) Clock signals (b) Timing generation circuitry.

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 86
 PLA Layout

And-Plane Or-Plane
V DD φ GND

x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 87
 PLA versus ROM

Programmable Logic Array

structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)

IDENTICAL TO ROM!

Main difference
ROM: fully populated
PLA: one element per minterm

Note: Importance of PLA’s has drastically reduced

1. slow
2. better software techniques (mutli-level logic
synthesis)

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 88
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Serial access memories
‹ Content Addressable Memory (CAM)
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 89
 Reliability and Yield

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 90
 Open Bit-line Architecture —Cross Coupling

EQ

WL1 WL0 WLD WLD WL0 WL1

CWBL CWBL
BL BL
Sense
CBL CBL
Amplifier
C C C C C C

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 91
 Folded-Bitline Architecture

WL1 WL1 WL0 WL0 WLD WLD

CWBL

BL CBL x y

... Sense
C C C C C C
EQ Amplifier

BL CBL x y
CWBL

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 92
 Transposed-Bitline Architecture

BL’
Ccross
BL
SA
BL
BL"

(a) Straightforward bitline routing.

BL’
Ccross
BL
SA
BL
BL"

(b) Transposed bitline architecture.

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 93
 Yield

Yield curves at different stages of process maturity

(from [Veendrick92])

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 94
 Redundancy

Row
Address
Redundant
rows
Fuse
:
Bank
Redundant
columns

Row Decoder
Memory
Array

Column Decoder Column

Address

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 95
 Redundancy and Error Correction

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 96
 Outline

‹ Memory classification
‹ Basic building blocks
‹ ROM
‹ Non Volatile Read Write Memories
‹ Static RAM (SRAM)
‹ Dynamic RAM (DRAM)
‹ Memory peripheral circuit
‹ Serial access memories
‹ Content Addressable Memory (CAM)
‹ Programmable Logic Array
‹ Reliability and Yield
‹ Memory trends

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 97
 Semiconductor Memory Trends

Memory Size as a function of time: x 4 every three years

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 98
 Semiconductor Memory Trends

Increasing die size

factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 99
 Semiconductor Memory Trends

Technology feature size for different SRAM generations

Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 100