ISO742x Low-Power Dual-Channel Digital Isolators: 1 Features 3 Description

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ISO7420, ISO7420M, ISO7421

SLLS984I – JUNE 2009 – REVISED JULY 2015
ISO742x Low-Power Dual-Channel Digital Isolators

1 Features 3 Description
•
1 Highest Signaling Rate: 1 Mbps The ISO7420, ISO7420M and ISO7421 provide
galvanic isolation up to 2500 VRMS for 1 minute per
• Low Power Consumption, Typical ICC per Channel UL. These digital isolators have two isolated
(3.3-V operation): channels. Each isolation channel has a logic input
– ISO7420: 1.1 mA, ISO7421: 1.5 mA and output buffer separated by a silicon dioxide
• Low Propagation Delay – 9 ns Typical (SiO2) insulation barrier. Used in conjunction with
isolated power supplies, these devices prevent noise
• Low Skew – 300 ps Typical currents on a data bus or other circuit from entering
• Wide TA Range: –40°C to 125°C (M-Grade) the local ground and interfering with or damaging
• 50-kV/μs Transient Immunity, Typical sensitive circuitry. The suffix M indicates wide
• Over 25-Year Isolation Integrity at Rated Voltage temperature range (–40°C to 125°C).
• Operates From 3.3-V and 5-V Supply and Logic These devices have TTL input thresholds and require
Levels two supply voltages, 3.3 or 5 V, or any combination.
All inputs are 5-V tolerant when supplied from a 3.3-V
• 3.3-V and 5-V Level Translation supply.
• Narrow Body SOIC-8 Package
Note: The ISO7420 and ISO7421 are specified for
• Safety and Regulatory Approvals: signaling rates up to 1 Mbps. Due to their fast
– 4242 VPK Isolation per DIN V VDE V 0884-10 response time, under most cases, these devices will
and DIN EN 61010-1 also transmit data with much shorter pulse widths.
– 2500 VRMS Isolation for 1 minute per UL 1577 Designers should add external filtering to remove
spurious signals with input pulse duration <20 ns if
– CSA Component Acceptance Notice 5A, IEC desired.
60950-1 and IEC 61010-1 Standards
– CQC Certification per GB4943.1-2011 Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications ISO7420
• Optocoupler Replacement in: ISO7420M SOIC (8) 4.90 mm × 3.91 mm
– Industrial Fieldbus ISO7421
– Profibus (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Modbus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
Simplified Schematic
VCCI VCCO
Isolation
Capacitor
INx OUTx
GNDI GNDO
VCCI and GNDI are supply and ground connections respectively for the input channels.
VCCO and GNDO are supply and ground connections respectively for the output channels.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ISO7420, ISO7420M, ISO7421
SLLS984I – JUNE 2009 – REVISED JULY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 ±5% .......................................................................... 11
2 Applications ........................................................... 1 6.14 Typical Characteristics .......................................... 12
3 Description ............................................................. 1 7 Parameter Measurement Information ................ 13
4 Revision History..................................................... 2 8 Detailed Description ............................................ 14
5 Pin Configuration and Functions ......................... 6 8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
6 Specifications......................................................... 7
8.3 Feature Description................................................. 15
6.1 Absolute Maximum Ratings ..................................... 7
8.4 Device Functional Modes........................................ 17
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7 9 Application and Implementation ........................ 18
6.4 Thermal Information .................................................. 8 9.1 Application Information............................................ 18
6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V 9.2 Typical Application ................................................. 18
±5% ............................................................................ 8 10 Power Supply Recommendations ..................... 20
6.6 Electrical Characteristics: VCC1 at 5 V ±5%, VCC2 at 11 Layout................................................................... 20
3.3 V ±5% .................................................................. 9 11.1 Layout Guidelines ................................................. 20
6.7 Electrical Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 11.2 Layout Example .................................................... 20
5 V ±5% ..................................................................... 9
12 Device and Documentation Support ................. 21
6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V
±5% .......................................................................... 10 12.1 Documentation Support ........................................ 21
6.9 Power Dissipation Characteristics .......................... 10 12.2 Related Links ........................................................ 21
6.10 Switching Characteristics: VCC1 and VCC2 at 5 V 12.3 Community Resources.......................................... 21
±5% .......................................................................... 10 12.4 Trademarks ........................................................... 21
6.11 Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 12.5 Electrostatic Discharge Caution ............................ 21
3.3 V ±5% ................................................................ 10 12.6 Glossary ................................................................ 21
6.12 Switching Characteristics: VCC1 at 3.3 V ±5%, VCC2 13 Mechanical, Packaging, and Orderable
at 5 V ±5% ............................................................... 11 Information ........................................................... 21
6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (May 2013) to Revision I Page
• VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision G (May 2013) to Revision H Page
• Changed Feature From: 4~242 Vpeak Isolation To: 4242 Vpeak Isolation ........................................................................... 1
Changes from Revision F (January 2013) to Revision G Page
• Changed VIORM in the INSULATION CHARACTERISTICS table, Specification value From: 56~6 To: 566........................ 15
• Changed VPR in the Specification value From: 10~62 To: 1062 .......................................................................................... 15
• Changed VIOTM t = 60 s (qualification) Specification value From: 4~242 To: 4242 .............................................................. 15
Changes from Revision E (June 2011) to Revision F Page
• Changed Feature From: 242 Vpeak Maximum Isolation-per DIN EN 60747-5-2 (VDE 0884 Part 2) - To: 4~242
Vpeak Isolation ....................................................................................................................................................................... 1
• Changed Feature From: IEC/VDE and CSA Approvals, IEC 60950-1–IEC 61010-1 End Equipment Standards
Approvals, All Approvals Pending To: CSA 60950-1 and IEC 61010-1 Approved ................................................................ 1
2 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: ISO7420 ISO7420M ISO7421

ISO7420, ISO7420M, ISO7421
www.ti.com SLLS984I – JUNE 2009 – REVISED JULY 2015
• Added table Note to VIORM .................................................................................................................................................... 15

• Changed VIORM in the INSULATION CHARACTERISTICS table, Specification value From: 56~0 To: 56~6...................... 15
• Changed VPR in the Specification value From: 10~50 To: 10~62 ........................................................................................ 15
• Changed VIOTM t = 60 s (qualification) Specification value From: 4~000 To: 4~242............................................................ 15
• Changed the IEC 60664-1 RATINGS TABLE. Row - Basic isolation group SPECIFICATION From: III-a To: II................. 15
• Changed CTI in the PACKAGE CHARACTERISTICS table, Min value From: >175 To 400 .............................................. 15
• Changed the text of NOTE: ................................................................................................................................................. 16
• Changed the REGULATORY INFORMATION table ............................................................................................................ 17
Changes from Revision D (July 2010) to Revision E Page
• Added new fifth bullet to Features and deleted text from 4-kVpeak bullet item ..................................................................... 1
• Changed first paragraph in Description from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421 .............. 1
• Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ........................................................ 8
• Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 10
• Changed the MAX value in the SWITCHING CHAR table 2nd row from 3.5 to 3.7 and 3rd row from 4 to 4.9................... 10
• Changed the MAX value in the 2nd SWITCHING CHAR table 2nd row from 4 to 5.6 and 3rd row from 5 to 6.3............... 10
• Changed the MAX value in the 3rd SWITCHING CHAR table 3rd row from 5 to 8.5 ......................................................... 11
• Changed the MAX value in the 4rd SWITCHING CHAR table 3rd row from 6 to 6.8 ......................................................... 11
• Changed Regulatory Information table last row, last column from: pending (E181974) to: E181974 ................................. 17
• Changed Note 2 in Function Table from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421................... 17
Changes from Revision C (March 2010) to Revision D Page
• Updated the Features List ...................................................................................................................................................... 1

• Deleted devices ISO7420F and ISO7420FM from the data sheet......................................................................................... 1
• Updated the device Description. Add paragraph - Note: The ISO7420 and ISO7421........................................................... 1
• Added Tstg to the Absolute Maximum Ratings Table ............................................................................................................ 7
• Updated the Recommended Operating Conditions table....................................................................................................... 7
• Updates throughout the Electrical Characteristics and Switching Characteristics tables ...................................................... 8
• Updated the Supply Current test conditions........................................................................................................................... 8
• Deleted the SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) graphs and the EYE DIAGRAM plots ................. 12
• Changed Figure 7................................................................................................................................................................. 13
• Changed the VIORM, VPR, and VIOTM unit values From: V To: Vpeak .................................................................................... 15
• Changed Minimum internal gap MIN value From: 0.008 To: 0.014mm ............................................................................... 15
• Changed the Barrier capacitance, input to output test conditions........................................................................................ 15
• Changed the Input capacitance test conditions ................................................................................................................... 15
• Changed VI From: 5.5 V To: 5.25 V ..................................................................................................................................... 16
• Changed From: 107mA To: 112mA...................................................................................................................................... 16
• Changed VI From: 3.6 V To: 3.45 V ..................................................................................................................................... 16
• Changed Figure 10............................................................................................................................................................... 16
• Deleted the ICC equations section......................................................................................................................................... 16
• Changed the Function Table Output values for PU (Open) From: H/L To: H ...................................................................... 17
• Changed Figure 11............................................................................................................................................................... 17
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

ISO7420, ISO7420M, ISO7421
Changes from Revision B (February 2010) to Revision C Page
• Added devices ISO7420F and ISO7420FM to the data sheet ............................................................................................... 1

• Added The suffix M indicates wide temperature range (–55°C to 125°C) and the suffix F indicates output-low option
in fail-safe condition. All other devices without the F suffix default to output-high in fail-safe state. ..................................... 1
• Added ISO7420F and ISO7420FM to the Available Options Table ....................................................................................... 6
• Changed value from a max of 4 mA to a min of –4 mA ......................................................................................................... 7
• Changed value from a min of –4 mA to a max of 4 mA ........................................................................................................ 7
• Changed Electrical Characteristics Conditions....................................................................................................................... 8
• Deleted Ci from the ELECTRICAL CHARACTERISTICS....................................................................................................... 8
• Added (All inputs switching with square wave clock signal for dynamic ICC measurement)................................................. 8
• Changed ELECTRICAL CHARACTERISTICS conditions...................................................................................................... 9
• Added High-level output voltage ISO7420 / 7421 (3.3-V side) test condition ....................................................................... 9
• Changed High-level output voltage min value........................................................................................................................ 9
• Deleted CI specification .......................................................................................................................................................... 9
• Changed ELECTRICAL CHARACTERISTICS conditions...................................................................................................... 9
• Added High-level output voltage ISO7420 / 7421 (5-V side) test condition ........................................................................... 9
• Changed High-level output voltage min value........................................................................................................................ 9
• Deleted CI specification .......................................................................................................................................................... 9
• Changed ELECTRICAL CHARACTERISTICS conditions.................................................................................................... 10
• Deleted CI specification ........................................................................................................................................................ 10
• Added (All inputs switching with square wave clock signal for dynamic ICC measurement)............................................... 10
• Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 10
• Changed PWD parameter from duration to width ................................................................................................................ 10
• Changed Switching Characteristics conditions..................................................................................................................... 10
• Changed Pulse duration distortion to Pulse width distortion ............................................................................................... 10
• Changed Switching Characteristics conditions..................................................................................................................... 11
• Changed Pulse duration distortion to Pulse width distortion ............................................................................................... 11
• Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 11
• Changed Figure 7................................................................................................................................................................. 13
• Added input to output and note 1 to Isolation resistance, input to output ............................................................................ 15
• Changed the Isolation resistance test conditions ................................................................................................................. 15
• Changed the Isolation resistance test conditions ................................................................................................................. 15
• Added note 1 to Barrier capacitance, input to output ........................................................................................................... 15
• Added Input capacitance ...................................................................................................................................................... 15
• Changed TJ = 170°C to TJ = 150°C...................................................................................................................................... 16
• Changed TJ = 170°C to TJ = 150°C...................................................................................................................................... 16
• Changed Figure 10............................................................................................................................................................... 16
• Changed the Function Table Output values for PU (Open) From: H To: H/L ...................................................................... 17
• Changed the Function Table Output values for PU (X) From: H To: H/L............................................................................. 17
• Changed the Function Table Output values for PU (X) From: H/L To: H............................................................................. 17

ISO7420, ISO7420M, ISO7421
• Added Note (2) in the Function Table .................................................................................................................................. 17

• Changed Figure 11............................................................................................................................................................... 17
Changes from Revision A (December 2009) to Revision B Page
• Switching Characteristics Table, Added Note (2) - Typical specifications are measured at ideal conditions of 25°C.
Max or Min specifications are measured at worst case conditions for VCC and temperature. ............................................... 8
Changes from Original (June 2009) to Revision A Page
• Added devices ISO7420 and ISO7420M to the data sheet ................................................................................................... 1

• Added the ICC equations section........................................................................................................................................... 16

ISO7420, ISO7420M, ISO7421
5 Pin Configuration and Functions
ISO7420: D Package
8-Pin SOIC ISO7421: D Package
(Top View) 8-Pin SOIC
(Top View)
VCC1 1 8 VCC2
VCC1 1 8 VCC2
Isolation
INA 2 7 OUTA
Isolation
OUTA 2 7 INA
INB 3 6 OUTB
INB 3 6 OUTB
GND1 4 5 GND2
GND1 4 5 GND2
Pin Functions
PIN
I/O DESCRIPTION
NAME ISO7420 ISO7421
GND1 4 4 — Ground connection for VCC1
GND2 5 5 — Ground connection for VCC2
INA 2 7 I Input, channel A
INB 3 3 I Input, channel B
OUTA 7 2 O Output, channel A
OUTB 6 6 O Output, channel B
VCC1 1 1 — Power supply, VCC1
VCC2 8 8 — Power supply, VCC2

ISO7420, ISO7420M, ISO7421
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See MIN MAX UNIT
VCC Supply voltage (2), VCC1, VCC2 –0.5 6 V
VI Voltage at IN, OUT –0.5 VCC + 0.5 (3) V
IO Output current –15 15 mA
TJ(max) Maximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
Field-induced charged-device model, JEDEC Standard 22, Test Method ±1500
V(ESD) Electrostatic discharge V
C101
Machine model, ANSI/ESDS5.2-1996 ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, Supply voltage - 3.3-V operation 3.15 3.3 3.45
V
VCC2 Supply voltage - 5-V operation 4.75 5 5.25
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.25 V
VIL Low-level input voltage 0 0.8 V
1/tui Signaling rate 0 1 Mbps
tui Input pulse duration 1 us
TJ (1) Junction temperature –40 136 °C
ISO7420, ISO7421 -40 25 105
TA Ambient temperature °C
ISO7420M -40 25 125
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information.

ISO7420, ISO7420M, ISO7421
6.4 Thermal Information

ISO742x
THERMAL METRIC (1) D (SOIC) UNIT
8 PINS
Low-K Board 212
RθJA Junction-to-ambient thermal resistance °C/W
High-K Board 116.6
RθJC(top) Junction-to-case (top) thermal resistance 71.6 °C/W
RθJB Junction-to-board thermal resistance 57.3 °C/W
ψJT Junction-to-top characterization parameter 28.3 °C/W
ψJB Junction-to-board characterization parameter 56.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ±5%

TA = –40°C to 125°C for ISO7420M, TA = –40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –4 mA; see Figure 6. VCCO (1) – 0.8 4.6
VOH High-level output voltage V
IOH = –20 μA; see Figure 6. VCCO – 0.1 5
IOL = 4 mA; see Figure 6. 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 6. 0 0.1
VI(HYS) Input threshold voltage hysteresis 400 mV
IIH High-level input current (1)
10 μA
INx at 0 V or VCCI
IIL Low-level input current –10 μA
CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 8. 25 50 kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT)
ISO7420
ICC1 Supply current for VCC1 0.4 1
DC to 1 Mbps VI = VCCI or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 3 6
ISO7421
(1) VCCI = Input-side power supply, VCCO = Output-side power supply

ISO7420, ISO7420M, ISO7421
6.6 Electrical Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%

(1)
IOH = –4 mA; ISO7421 (5-V side) VCCO – 4.6
see Figure 6. 0.8
ISO7420 / 7421 (3.3-V side). VCCO – 0.4 3
IOH = –20 μA; see Figure 6, VCCO – 0.1 VCC
IIH High-level input current (1)
10 μA
INx at 0 V or VCCI
CMTI Common-mode transient immunity VI = VCCI or 0 V; seeFigure 8 . 25 40 kV/μs
ISO7420
ICC1 Supply current for VCC1 0.4 1 mA
DC to 1 Mbps VI = VCCI or 0 V, 15 pF load
ICC2 Supply current for VCC2 2 4.5 mA
ISO7421
ICC1 Supply current for VCC1 2 4 mA
DC to 1 Mbps VI = VCCI or 0 V, 15 pF load
ICC2 Supply current for VCC2 1.5 3.5 mA
6.7 Electrical Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%

IOH = –4 mA; VCCO (1) –
ISO7420 / 7421 (5-V side). 4.6
see Figure 6. 0.8
ISO7421 (3.3-V side) VCCO – 0.4 3
IOH = –20 μA; see Figure 6 VCCO – 0.1 VCC
IIH High-level input current 10 μA
INx at 0 V or VCCI (1)
CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 8. 25 40 kV/μs
ISO7420
ICC1 Supply current for VCC1 0.2 0.7
ISO7421

ISO7420, ISO7420M, ISO7421
6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±5%

(1)
IOH = –4 mA; see Figure 6. VCCO – 0.4 3
IOH = –20 μA; see Figure 6. VCCO – 0.1 3.3
IIH High-level input current 10 μA
INx at 0 V or VCCI (1)
Common-mode transient
CMTI VI = VCCI or 0 V; seeFigure 8 . 25 40 kV/μs
immunity
ISO7420
ICC2 Supply current for VCC2 2 4.5
ISO7421
6.9 Power Dissipation Characteristics

ISO742x
THERMAL METRIC D (SOIC) UNIT
8 PINS
VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF
PD Device power dissipation 55 mW
Input a 1-Mbps 50% duty-cycle square wave
6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ±5%

tPLH, tPHL Propagation delay time See Figure 6. 9 14 ns
(1)
PWD Pulse width distortion |tPHL – tPLH| 0.3 3.7 ns
tsk(pp) Part-to-part skew time 4.9 ns
tsk(o) Channel-to-channel output skew time 3.6 ns
tr Output signal rise time See Figure 6. 1 ns
tf Output signal fall time 1 ns
tfs Fail-safe output delay time from input power loss See Figure 7. 6 μs
(1) Also known as pulse skew.
6.11 Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%

PWD (1) Pulse width distortion |tPHL – tPLH| 0.5 5.6 ns
tsk(o) Channel-to-channel output skew time 4 ns


ISO7420, ISO7420M, ISO7421
Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5% (continued)

6.12 Switching Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%

(1)
PWD Pulse width distortion |tPHL – tPLH| 0.5 4 ns
tsk(o) Channel-to-channel output skew time 4 ns
6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±5%

tPLH, tPHL Propagation delay time 12 20 ns
PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 6. 1 5 ns
tsk(o) Channel-to-channel output skew time 5.5 ns
tr Output signal rise time 2 ns
See Figure 6.

ISO7420, ISO7420M, ISO7421
6.14 Typical Characteristics
14 1.6
Input Voltage Switching Threshold − V

tpd − Propagation Delay Time − ns
12 VCC1, VCC2 at 3.3 V 1.5 VIT+, 5 V
1.4
10
1.3 VIT+, 3.3 V
8
VCC1, VCC2 at 5 V
1.2
6
1.1 VIT−, 5 V
4
1.0
VIT−, 3.3 V
2 0.9
0 0.8
−55 −35 −15 5 25 45 65 85 105 125 −55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C G004

Figure 1. Propagation Delay Time vs Free-Air Temperature Figure 2. Input Voltage Switching Threshold vs Free-Air
Temperature
2.62 0
IOH − High-Level Output Current − mA

TA = 25°C
2.61 −10
Fail-Safe Voltage Threshold − V
2.60 FS+ −20

2.59
−30
2.58
−40
2.57 VCC1, VCC2 at 3.3 V
−50
2.56
−60
2.55 FS−
2.54 −70
VCC1, VCC2 at 5 V
2.53 −80
2.52 −90
−55 −35 −15 5 25 45 65 85 105 125 0 1 2 3 4 5 6

VOH − High-Level Output Voltage − V G007
Figure 3. Fail-Safe Voltage Threshold vs Free-Air Figure 4. High-Level Output Current vs High-Level Output
Temperature Voltage
80
IOL − Low-Level Output Current − mA
TA = 25°C
70
60 VCC1, VCC2 at 5 V
50
40
30 VCC1, VCC2 at 3.3 V
20
10
0
0 1 2 3 4 5 6
VOL − Low-Level Output Voltage − V G008
Figure 5. Low-Level Output Current vs Low-Level Output Voltage

ISO7420, ISO7420M, ISO7421
7 Parameter Measurement Information
Isolation Barrier
VCCI
VI 1.4 V 1.4 V
IN OUT
0V
tPLH tPHL
Input (2)
(1) VI 50 W VO CL
Generator VOH
50% 90% 50%
VO
10% VOL
tr tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCCI VCCI
VI
Isolation Barrier
2.7 V
0V
IN = 0 V OUT tfs
VO
VOH
(1) VO 50% Fail-Safe HIGH
CL
VOL
(1) CL = 15 pF ± 20% includes instrumentation and fixture capacitance.
Figure 7. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCCI VCCO
C = 0.1 μ F ±1% C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
Isolation Barrier
stable.
IN OUT
S1
+
CL VOH or VOL
(1)
–
GNDI GNDO
+ VCM –
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Common-Mode Transient Immunity Test Circuit

ISO7420, ISO7420M, ISO7421
8 Detailed Description
8.1 Overview
The isolator in Figure 9 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a
single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the
input. The following capacitor-resistor networks differentiate the signal into transients, which then are
converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop
whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop
measures the durations between signal transients. If the duration between two consecutive transients
exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer
to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values,
these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus
creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is
modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before
passing it on to the output multiplexer.
8.2 Functional Block Diagram
Figure 9. Conceptual Block Diagram of a Digital Capacitive Isolator

ISO7420, ISO7420M, ISO7421
8.3 Feature Description

8.3.1 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1) TEST CONDITIONS SPECIFICATION UNIT

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM Maximum working insulation voltage 566 VPK
VPR Input-to-output test voltage t = 1 s (100% production), partial discharge 5 pC 1062 VPK
t = 60 s (qualification)
VIOTM Transient overvoltage 4242 VPK
t = 1 s (100% production)
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2
UL 1577
VTEST = VISO = 2500 VRMS, t = 60 s (qualification)
VISO Isolation voltage per UL VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100% 2500 VRMS
production)
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Material group II
Rated mains voltage ≤ 150 VRMS I–IV
Installation classification
Rated mains voltage ≤ 300 VRMS I–III
8.3.2 Package Characteristics

over recommended operating conditions (unless otherwise noted)

L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm
Minimum external tracking Shortest terminal-to-terminal distance across the
L(I02) 4 mm
(creepage) package surface
Tracking resistance (comparative
CTI DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
tracking index)
DTI Distance through the insulation Minimum internal gap (internal clearance) 0.014 mm
12
Isolation resistance, input to VIO = 500 V, TA = 25°C >10 Ω
RIO
output (1) VIO = 500 V, 100°C ≤ TA ≤ max >1011 Ω
Barrier capacitance, input to
CIO VIO = 0.4 sin (2πft), f = 1 MHz 1 pF
output (1)
CI Input capacitance (2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.

ISO7420, ISO7420M, ISO7421
SPACER
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
8.3.3 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.

Safety input, output, or supply θJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 112
IS mA
current θJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 171
TS Maximum safety temperature 150 °C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test
Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
180
160 VCC1, VCC2 at 3.45 V
Safety Limiting Current − mA
140
120
100 VCC1, VCC2 at 5.25 V
80
60
40
20
0
0 50 100 150 200
Case Temperature − °C
G002
Figure 10. θJC Thermal Derating Curve per VDE

ISO7420, ISO7420M, ISO7421
8.3.4 Regulatory Information
VDE CSA UL CQC

Certified according to
DIN V VDE V 0884-10 (VDE V Recognized under UL1577
Approved under CSA Component Certified according to
0884-10):2006-12 and Component Recognition
Acceptance Notice #5A GB4943.1-2011
DIN EN 61010-1 (VDE 0411-1): Program (1)
2011-07
Basic Insulation
Basic insulation per CSA 60950-1- Basic Insulation, Altitude ≤
Maximum Transient Overvoltage, 07 and IEC 60950-1 (2nd Ed), 5000 m, Tropical Climate, 250
4242 VPK Single Protection, 2500 VRMS
390 VRMS maximum working VRMS maximum working
Maximum Working Voltage, 566 voltage voltage
VPK
Certificate number:
Certificate number: 40016131 Master contract number: 220991 File number: E181974
CQC14001109540
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
8.4 Device Functional Modes
Table 2. Function Table (1)

INPUT OUTPUT
VCCI VCCO
INA, INB OUTA, OUTB
H H
PU PU L L
Open H (2)
PD PU X H (2)
X PD X Undetermined
(1) VCCI = Input-side power supply; VCCO = Output-side power supply;

PU = Powered up (VCC ≥ 3.15 V); PD = Powered down (VCC ≤ 2.1
V); X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output defaults to high level.
8.4.1 Device I/O Schematics

Input Output
VCCI VCCI VCCI VCCO
1 MW
500 W 8W
IN
OUT
13 W
Figure 11. Device I/O Schematics

ISO7420, ISO7420M, ISO7421
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

ISO742x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3.15 V to 5.25 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application

ISO7421 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VCC1 VCC2
ISO7421
Figure 12. Isolated 4-20 mA Current Loop
9.2.1 Design Requirements

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO742x only require two external bypass capacitors to operate.

ISO7420, ISO7420M, ISO7421
Typical Application (continued)

9.2.2 Detailed Design Procedure
ISO7420
VCC1 1 8 VCC2
0.1 µF 0.1 µF
INA 2 7 OUTA
INB 3 6 OUTB
GND1 4 5 GND2
ISO7421
VCC1 1 8 VCC2
0.1 µF 0.1 µF
OUTA 2 7 INA
INB 3 6 OUTB
GND1 4 5 GND2
Figure 13. Typical ISO7420 and ISO7421 Circuit Hookup
9.2.3 Application Curve

100
Life Expectancy – Years
28 Years VIORM at 566 V
10
0 120 250 500 750 880 1000
VIORM – Working Voltage – V

G001
Figure 14. Life Expectancy vs Working Voltage

ISO7420, ISO7420M, ISO7421
10 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 15). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284.
11.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
space free FR-4
40 mils from planes, 0r ~ 4.5
traces , pads,
and vias
Power plane
10 mils
Low-speed traces
Figure 15. Recommended Layer Stack

ISO7420, ISO7420M, ISO7421
12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
• SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
• Isolation Glossary, SLLA353
• Digital Isolator Design Guide, SLLA284
12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
ISO7420 Click here Click here Click here Click here Click here
ISO7420M Click here Click here Click here Click here Click here
ISO7421 Click here Click here Click here Click here Click here
ISO7421M Click here Click here Click here Click here Click here
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ISO7420D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 IS7420
& no Sb/Br)
ISO7420DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 IS7420
& no Sb/Br)
ISO7420MD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 I7420M
& no Sb/Br)
ISO7420MDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 I7420M
& no Sb/Br)
ISO7421D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 IS7421
& no Sb/Br)
ISO7421DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 IS7421
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7421 :
• Enhanced Product: ISO7421-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7420DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7420MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7421DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7420DR SOIC D 8 2500 350.0 350.0 43.0
ISO7420MDR SOIC D 8 2500 350.0 350.0 43.0
ISO7421DR SOIC D 8 2500 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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ISO7420, ISO7420M, ISO7421

ISO742x Low-Power Dual-Channel Digital Isolators

Changes from Revision H (May 2013) to Revision I Page

• VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1

Changes from Revision G (May 2013) to Revision H Page

Changes from Revision F (January 2013) to Revision G Page

Changes from Revision E (June 2011) to Revision F Page

2 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: ISO7420 ISO7420M ISO7421

• Added table Note to VIORM .................................................................................................................................................... 15

Changes from Revision D (July 2010) to Revision E Page

Changes from Revision C (March 2010) to Revision D Page

• Updated the Features List ...................................................................................................................................................... 1

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Changes from Revision B (February 2010) to Revision C Page

• Added devices ISO7420F and ISO7420FM to the data sheet ............................................................................................... 1

4 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: ISO7420 ISO7420M ISO7421

• Added Note (2) in the Function Table .................................................................................................................................. 17

Changes from Revision A (December 2009) to Revision B Page

Changes from Original (June 2009) to Revision A Page

• Added devices ISO7420 and ISO7420M to the data sheet ................................................................................................... 1

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

5 Pin Configuration and Functions

6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: ISO7420 ISO7420M ISO7421

6.2 ESD Ratings

6.3 Recommended Operating Conditions

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

6.4 Thermal Information

6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ±5%

(1) VCCI = Input-side power supply, VCCO = Output-side power supply

8 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: ISO7420 ISO7420M ISO7421

6.6 Electrical Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%

(1) VCCI = Input-side power supply, VCCO = Output-side power supply

6.7 Electrical Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%

(1) VCCI = Input-side power supply, VCCO = Output-side power supply

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±5%

(1) VCCI = Input-side power supply, VCCO = Output-side power supply

6.9 Power Dissipation Characteristics

6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ±5%

(1) Also known as pulse skew.

6.11 Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%

(1) Also known as pulse skew.

Product Folder Links: ISO7420 ISO7420M ISO7421

Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5% (continued)

6.12 Switching Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%

(1) Also known as pulse skew.

6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±5%

(1) Also known as pulse skew.

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

6.14 Typical Characteristics

Input Voltage Switching Threshold − V

12 VCC1, VCC2 at 3.3 V 1.5 VIT+, 5 V

TA − Free-Air Temperature − °C G004