INTERNATIONAL INSTITUTE OF INFORMATION

TECHNOLOGY, BANGALORE

Project Report on
Verilog Implementation of Different
Types of Caches

Project members :

Vaibhav Sonewane (MT2019527)

Swapnil Rawat(MT2019526)

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Contents:

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Design:
Memory Specification:
assumption:1 word =1 byte

1 block=4 words = 32 bits

memory size = 128 byte = 128 words
128/4 = 32 blocks in memory (since in each block four words are present)

General Cache Specification:

cache size = 16 words
16/4 = 4 lines in cache

line size = block size

i.e. 1 line = 4 words = 32 bits

(NOTE: Number of extra bits that will be required for associating tag, valid bit or/and lru with
each cache line will depend on the type of cache )

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Direct Mapping Cache:
In Direct mapping, each memory block is assigned to a specific line in the
cache.
If a line is previously taken up by a memory block when a new block needs to
be loaded, the old block is trashed.

L0

L1

L2

L3

Formula to find which block from memory will go to which line number in cache

k mod n

k : memory block number

n : number of lines in cache

CPU to cache Address: 7 bits

Address is split into tag, word-offset, line offset as follows

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 6 4 3 2 1 0

Tag Line
Line no.
No. Block
Blockoffset
offset

Working:
Note: Write back policy is employed

s0: cache read:

valid+tag match => s0
valid+tag dosen’t match => s1
not valid => s1

cache write:
valid+tag match => s0
valid+tag dosen’t match =>write the memory with the current block => s2
not valid => s0

s1: read block from memory

cache read:
update cache
output result to cpu
goto s0

cache write:
write new word into the block read from memory
update the cache
goto s0
(note: memory still has old data and not has been updated. Memory will be updated only when
we replace the block from cache, since memory write is costly)

s2: make memory_write signal low and memory_read signal high to read new block from memory
for which cpu has sent the address
goto s1

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K- way Set Associative Cache:
Instead of having exactly one line that a block can map to in the cache, we will
group a few lines together creating a SET. Then a block in memory can map to
any one of the lines of a specific set.

L0

L1

L2

S1
L3

Formula to find which block from memory will go to which block number in the
cache

k mod n

k : memory block number

n : number of sets

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CPU to cache Address: 7 bits

Address is split into tag, word-offset, line offset as follows

6 3 2 1 0

Tag Line
Set No
no. Block
Blockoffset
offset

Working:
Note: Write through policy is employed

Select set => s0

S0: line1 valid + tag match => s0

line1 valid + line2 valid + tag match in line 2 => s0

line1 valid + line2 valid + tag doesn’t match => check lru : line 1 is lru => s1
line 2 is lru => s2

line1 valid + line2 not valid + tag doesn’t match in line 1 => s2

line1 not valid + line2 valid + tag match in line 2 => s0

line1 not valid + line2 valid + tag doesn’t match in line 2 => s1

line1 not valid + line2 not valid => s1

s1: Read block from memory/ write word to the memory

update cache
make line2 as lru
go to s0

s2: Read block from memory/ write word to the memory

update cache
make line1 as lru
go to s0

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Fully Associative Cache:
Any block can go into any line of the cache.

L0

L1

L3
L2

L3
L4

Mru

CPU to cache Address: 7 bits

Address is split into tag, word-offset, line offset as follows

6 2 1 0

Tag Block offset

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Working:
Note: Write through policy is employed

Select set => s0

S0: line 0 valid + line1 valid + line 2 valid + line 3 valid + tag match => cache hit
find the line in which tag is matched and make that as mru
if read => s0
if write => s2

line 0 valid + line1 valid + line 2 valid + line 3 invalid + tag match => cache hit
find the line in which tag is matched and make that as mru
if read => s0
if write => s2

line 0 valid + line1 valid + line 2 invalid + line 3 invalid + tag match => cache hit
find the line in which tag is matched and make that as mru
if read => s0
if write => s2

line 0 valid + line1 invalid + line 2 invalid + line 3 invalid + tag match => cache hit
find the line in which tag is matched and make that as mru
if read => s0
if write => s2

line 0 valid + line1 valid + line 2 valid + line 3 valid + tag dosen’t match => cache miss
if read => s2
if write => s2

line 0 valid + line1 valid + line 2 valid + line 3 invalid + tag dosen’t match => cache miss
if read => s1
if write => s1

line 0 valid + line1 valid + line 2 invalid + line 3 invalid + tag dosen’t match => cache miss
if read => s1
if write => s1

line 0 valid + line1 invalid + line 2 invalid + line 3 invalid + tag dosen’t match => cache miss
if read => s1
if write => s1

line 0 invalid + line1 invalid + line 2 invalid + line 3 invalid + tag dosen’t match => cache
miss
if read => s1
if write => s1

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s1: Read block from memory/ write word to the memory

new block is to be written into the invalid line

set the line as MRU and Valid
go to s0

s2: Read block from memory/ write word to the memory

Replace the block in MRU line
go to s0

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Simulation Results:
Direct Mapping cache:

2-Way Associative Cache:

Fully Associative :

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Conclusion:
All the three Caches i.e i ) Direct Mapping Cache
ii ) 2-way set Associative Cache
iii ) Fully-Associative Cache
are working fine and are showing the expected hits and misses.

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