TI Designs

Dual Channel-to-Channel Isolated Universal Analog Input

Module for PLC Reference Design

TI Designs Design Features

This dual channel-to-channel isolated universal analog • Measurement up to ±12 V
input module reference design for programmable logic • Current Measurement up to ±55 mA
controllers (PLCs) combines precision and flexibility. It
can measure voltage as well as current, and it • Thermocouple and 2-, 3-, 4-Wire RTD Support
supports thermocouples, RTD, and 4- to 20-mA loops. • 4- to 20-mA Loop Power Supply
It is a high density universal multi-channel module and • Passive Analog Front-End
needs only four input terminals per channel.
• Analog Bandwidth up to 1 kHz
Design Resources • Small Burden Resistor of 27.4 Ω
• Accuracy:
TIDA-00550 Design Folder
– < 0.002% (25°C)
TIDA-00549 Tools Folder
ADS1262 Product Folder – < 0.05% (–35°C to 85°C)
LMT01 Product Folder • Simultaneous 50- and 60-Hz Rejection
LM5017 Product Folder • IEC61000-4-5 class II (±1 kV at 42 Ω)
LM2903 Product Folder
• HART Ready (Requires TIDA-00549 Plug-in Board)
TPS7A4901 Product Folder
TPS7A3001 Product Folder Featured Applications
TPS7A4101 Product Folder
• Isolated Multi-Channel Analog Input Module for
TLV70433 Product Folder
PLCs
TPS61093 Product Folder

ASK Our E2E Experts

30 V
9000
5V
8000
LM5017 16 to 33 V

7000
Number of Occurrences

±5 V
24 V/25 mA 2.5 or 3.3 V 3.3 V ±2.5 or ±1.7 V

TPS7A4101 TPS7A4901 TLV70433 TPS7A3001 6000

TPS61093 5V

5000

SPI ISO7141CC SPI 4000

ADS1262 3000

AFE
9x AIN 2000
µ+&594 LMT01 LM2903

1000
GPIOs

0
348.4 348.6 348.8 349 349.2 349.4 349.6 349.8 350
Output Voltage (µV) D001

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

All trademarks are the property of their respective owners.

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1 Key System Specifications

Table 1. Key System Specifications

PARAMETER SPECIFICATION DETAILS
Number isolated of channels 2 —
Secondary input
Operating voltage Primary input (J2) Section 3.7
(BeagleBone)
Ranges 16 to 33 V 5V Section 3.7
Power consumption per channel 400 mW Section 3.7
High-voltage measurement Section 3.1, Section 4.1
Low-voltage measurement Section 3.1, Section 4.2
Current measurement Section 3.1, Section 4.3
Operating modes Section 3.1, Section 3.7.4,
4- to 20-mA loop
Section 4.4, Section 4.7
Thermocouple with cold-junction compensation Section 3.3, Section 4.5
2-, 3-, and 4-wire RTD Measurement Section 3.9, Section 4.6
Analog inputs Voltage, HV Voltage, SE Voltage, DIFF Current —
±12.39 V ±2.20 V ±1.25 V ±55 mA
±1.25 V ±0.62 V ±45 mA
±0.62 V ±0.31 V ±22 mA
Ranges Section 3.1, Section 3.10
±0.31 V ±0.15 V ±11 mA
±0.15 V ±0.07 V ±5.5 mA
±0.07 V ±0.03 V ±2.7 mA
Input impedance 100 kΩ ~1 GΩ ~1 GΩ 43 Ω Section 3.1
Input accuracy —
25°C ±0.001% ±0.0006% ±0.0006% ±0.002% Section 3.10
–35°C to 85°C ±0.035% ±0.05% ±0.05% ±0.05% Section 3.10
Loop power supply Min. 24-V DC (0 to 25 mA) Section 3.7.4, Section 4.7
Thermocouple accuracy (25°C) ±0.7°C Section 4.5
RTD (3-wire) accuracy (25°C) ±0.07°C Section 4.6
Signaling Four LEDs at terminal inputs Section 3.4
Surge transient immunity EN 61000-4-5 class 2 (±1 kV, 24 A) Section 3.8
Operating temperature –40°C to 85°C Section 2
Storage temperature –40°C to 125°C —
Form factor —
Each channel 93 × 27 mm (3.66 × 1.06 in) —
Entire board 159 × 55 mm (6.26 × 2.17 in) —
HART communication Supported by TIDA-00549 Section 3.10

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2 System Description
The TIDA-00550 universal analog input module is a versatile dual channel-to-channel isolated low-input
terminal count, high-performance design. It includes a high-voltage, low-voltage, and current measurement
signal path. The high-voltage path can be used in parallel with the low-voltage or current path.
Temperature sensors such as resistance temperature detectors (RTDs) and thermocouples (TC),
including cold-junction compensation (CJC), can be directly connected to the terminal pins. In addition, the
4- to 20-mA loop supports remote sensor transmitters without an additional power supply. The TI Design
TIDA-00549 can be used to add HART communication to the 4- to 20-mA loop.
The passive analog front-end (AFE) avoids distortion of the measurement signal. Noise from active
components such as op amps, which are used in comparable designs, is therefore eliminated. This
BeagleBone Cape (1) compatible design can be powered either from an external PLC power supply (16 to
33 V) or directly from the BeagleBone Black (5 V).
Each channel uses only four isolated channels, all dedicated to the digital interface (SPI). The general
output pins (GPO) required for the mode switching are provided by the analog-to-digital converter (ADC)
itself. The data stream of the local temperature sensor for the cold junction compensation shares the
same SPI isolator as the ADC.
The four terminal input pins can withstand 33 V continuously (important in the event of wrong wiring of the
PLC supply voltage) and are immune to EN61000-4-5 class 2 (±1 kV at 24 A). The four blue signaling
LED visible at the terminal inputs allows fast discovery of the selected mode of the particular channel.
The isolated switches and the TPS61093 support a temperature range of –40°C to 85°C. All other devices
can operate in the extended temperature range of -40°C to 125°C. The TPS61093 has only a supporting
function here (transforming the BeagleBone voltage to 16.5 V) and is not an integral part of the design.
The board includes two exact same channels. The AM3359 (2) Sitara processor on the BeagleBone board
distinguishes the two channels by two separate chip select signals, CS0 and CS1. The block diagram in
Figure 1 shows one channel only. The functionality of the devices is described in the following sections.

30 V

5V

LM5017 16 to 33 V

±5 V
24 V/25 mA 2.5 or 3.3 V 3.3 V ±2.5 or ±1.7 V

TPS7A4101 TPS7A4901 TLV70433 TPS7A3001

TPS61093 5V

SPI ISO7141CC SPI

ADS1262

9x AIN
AFE
µ+&594 LMT01 LM2903

GPIOs

Figure 1. Block Diagram (One Channel)

(1)
See the System Reference Manual at https://github.com/CircuitCo/BeagleBone-Black/blob/master/BBB_SRM.pdf?raw=true
(2)
See the product folder at http://www.ti.com/product/AM3359

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To get familiar with the physical board, Figure 2 describes the interfacing components of the design.
24-V DC BeagleBone connectors HART modem connectors Fiber optics channels

Terminal inputs

BeagleBone cape address selection Power Good LEDs 4- to 20-mA LED Custom LED

Figure 2. Physical Board

2.1 Highlighted Products

2.1.1 ADS1262
The ADS1262 is a low-noise, low-drift, 38.4-kSPS, delta-sigma (ΔΣ) ADC with an integrated PGA,
reference, and internal fault monitors. The sensor-ready ADC provides complete, high-accuracy, one-chip
measurement solutions for the most demanding sensor applications, including weigh scales, strain-gauge
sensors, TCs, and RTDs.
The ADCs are comprised of a low-noise, CMOS PGA (gains 1 to 32), a ΔΣ modulator, followed by a
programmable digital filter. The flexible AFE incorporates two sensor-excitation current sources suitable
for direct RTD measurement. A single-cycle settling digital filter maximizes multiple-input conversion
throughput, while providing 130-dB rejection of 50- and 60-Hz line cycle interference.
The ADS1262 is available in a 28-pin TSSOP package and fully specified over the –40°C to 125°C
temperature range.

2.1.2 ISO7141CC
The ISO7141CC provides galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE.
The ISO7141CC is a quad-channel isolator with three forward and one reverse-direction channels. This
device is capable of 50-Mbps maximum data rate with a 5-V supply and 40-Mbps maximum data rate with
a 2.7- or 3.3-V supply, with integrated filters on the inputs for noise-prone applications. The suffix CC
states the default output state is high.
Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation
barrier. Used with isolated power supplies, these devices prevent noise currents on a data bus or other
circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices
have TTL input thresholds and can operate from 2.7-, 3.3-, and 5-V supplies. All inputs are 5-V tolerant
when supplied from a 2.7- or 3.3-V supply.

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2.1.3 LMT01
The LMT01 is a high-accuracy, 2-pin temperature sensor with an easy-to-use pulse count interface, which
makes it an ideal digital replacement for PTC or NTC thermistors both on and off board in automotive,
industrial, and consumer markets. The LMT01 digital pulse count output and high accuracy over a wide
temperature range allow pairing with any MCU without concern for integrated ADC quality or availability
while minimizing software overhead. TI’s LMT01 achieves a flat ±0.5°C accuracy with very fine resolution
(0.0625°C) over a wide temperature range of –20°C to 90°C without system calibration or hardware or
software compensation.
Unlike other digital IC temperature sensors, the LMT01's single-wire interface is designed to directly
interface with a GPIO or comparator input, thereby simplifying hardware implementation. Similarly, the
LMT01’s integrated EMI suppression and simple 2-pin architecture make it ideal for onboard and off-board
temperature sensing. The LMT01 offers all the simplicity of analog NTC or PTC thermistors with the added
benefits of a digital interface, wide specified performance, EMI immunity, and minimum processor
resources.

2.1.4 LM5017
The LM5017 is a 100-V, 600-mA synchronous step-down regulator with integrated high-side and low-side
MOSFETs. The constant on-time (COT) control scheme employed in the LM5017 requires no loop
compensation, provides excellent transient response, and enables very high step-down ratios. The on-time
varies inversely with the input voltage resulting in nearly constant frequency over the input voltage range.
A high-voltage startup regulator provides bias power for internal operation of the IC and for integrated gate
drivers.
A peak current limit circuit protects against overload conditions. The undervoltage lockout (UVLO) circuit
allows the input undervoltage threshold and hysteresis to be independently programmed. Other protection
features include thermal shutdown and bias supply undervoltage lockout (VCC UVLO).

2.1.5 LM2903
The LM2903 consists of two independent voltage comparators that are designed to operate from a single
power supply over a wide range of voltages. Operation from dual supplies also is possible as long as the
difference between the two supplies is 2 V to 36 V, and VCC is at least 1.5 V more positive than the input
common-mode voltage. Current drain is independent of the supply voltage. The outputs can be connected
to other open-collector outputs to achieve wired-AND relationships.

2.1.6 TPS7A4901
The TPS7A49 series of devices are positive, high-voltage (36 V), ultralow-noise (15.4-μVRMS, 72-dB
PSRR) linear regulators that can source a 150-mA load.
These linear regulators include a CMOS logic-level-compatible enable pin and capacitor-programmable
soft-start function that allows for customized power-management schemes. Other available features
include built-in current limit and thermal shutdown protection to safeguard the device and system during
fault conditions.
The TPS7A49 family is designed using bipolar technology and is ideal for high-accuracy, high-precision
instrumentation applications where clean voltage rails are critical to maximize system performance. This
design makes the device an excellent choice to power operational amplifiers, ADCs, digital-to-analog
converters (DACs), and other high-performance analog circuitry.
In addition, the TPS7A49 family of linear regulators is suitable for post DC-DC converter regulation. By
filtering out the output voltage ripple inherent to DC-DC switching conversion, maximum system
performance is provided in sensitive instrumentation, test and measurement, audio, and RF applications.

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2.1.7 TPS7A3001
The TPS7A30 series of devices are negative, high-voltage (–35 V), ultralow-noise (15.1-μVRMS, 72-dB
PSRR) linear regulators that can source a maximum load of 200 mA.
These linear regulators include a CMOS logic-level-compatible enable pin and capacitor-programmable
soft-start function that allows for customized power-management schemes. Other features include built-in
current limit and thermal shutdown protection to safeguard the device and system during fault conditions.
The TPS7A30 family is designed using bipolar technology and is ideal for high-accuracy, high-precision
instrumentation applications where clean voltage rails are critical to maximize system performance. This
design makes the device an excellent choice to power operational amplifiers, ADCs, DACs, and other
high-performance analog circuitry.
In addition, the TPS7A30 family of linear regulators is suitable for post DC-DC converter regulation. By
filtering out the output voltage ripple inherent to DC-DC switching conversion, maximum system
performance is provided in sensitive instrumentation, test and measurement, audio, and RF applications.

2.1.8 TPS7A4101
The TPS7A41 is a very high voltage-tolerant linear regulator that offers the benefits of a thermally-
enhanced package (MSOP-8) and is able to withstand continuous DC or transient input voltages of up to
50 V.
The TPS7A41 is stable with any output capacitance greater than 4.7 μF and any input capacitance greater
than 1 μF (over temperature and tolerance). Thus, implementations of this device require minimal board
space because of its miniaturized packaging (MSOP-8) and a potentially small output capacitor. In
addition, the TPS7A41 offers an enable pin (EN) compatible with standard CMOS logic to enable a low-
current shutdown mode.
The TPS7A41 has an internal thermal shutdown and current limiting to protect the system during fault
conditions. The MSOP-8 packages has an operating temperature range of TJ = –40°C to 125°C. In
addition, the TPS7A41 is ideal for generating a low-voltage supply from intermediate voltage rails in
telecom and industrial applications; not only can it supply a well-regulated voltage rail, but it can also
withstand and maintain regulation during very high and fast voltage transients. These features translate to
simpler and more cost-effective electrical surge-protection circuitry for a wide range of applications.

2.1.9 TLV70433
The TLV704 series of low-dropout (LDO) regulators are ultralow quiescent current devices designed for
extremely power-sensitive applications. Quiescent current is virtually constant over the complete load
current and ambient temperature range.
The TLV704 operates over a wide operating input voltage of 2.5 to 24 V. Thus, the device is an excellent
choice for both battery-powered systems as well as industrial applications that undergo large line
transients.

2.1.10 TPS61093
The TPS61093 is a 1.2-MHz, fixed-frequency boost converter designed for high integration and high
reliability. The IC integrates a 20-V power switch, I/O isolation switch, and power diode. When the output
current exceeds the overload limit, the isolation switch of the IC opens up to disconnect the output from
the input, thus protecting the IC and the input supply. The isolation switch also disconnects the output
from the input during shutdown to minimize leakage current. When the IC is shut down, the output
capacitor is discharged to a low voltage level by internal diodes. Other protection features include 1.1-A
peak overcurrent protection (OCP) at each cycle, output overvoltage protection (OVP), thermal shutdown,
and UVLO. The output can be boosted up to 17 V.

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3 System Design Theory

3.1 AFE
The ADS1262 is a high-performance 32-bit ΔΣ ADC. This keeps the attached AFE simple and cost-
effective. The built-in PGA is able to scale the analog input signal 1×, 2×, 4×, 8×, 16×, or 32× to use the
entire ADC measurement range. The AFE (see Figure 3) has three independent input paths:
• High-voltage input
• Low-voltage input
• Current input
D3_AFE1 250uA
R15_AFE1 AIN1 IDAC0
1 2
SW_RTD_LOOP AVSS_iso
49.9
Blue
1

2
AVSS_iso R14_AFE1
K1_AFE1 AIN2 REFP
5.11k
CPC1017N
C17_AFE1

0.01%, 5ppm
8200pF

1.2475V
D4_AFE1 R16_AFE1 C18_AFE1
4 3 4.99k 0.1µF
4-20mA LOOP
5 2 GND C19_AFE1
8200pF
R17_AFE1
4

6 1
AIN3 REFN
5.11k
BAS70JW-7-F

J1_AFE1
1 R18_AFE1
AIN0 V
2 82.5k
4

3
3
4 K2_AFE1
C20_AFE1 D5_AFE1 CPC1017N R19_AFE1 C21_AFE1
0.01µF SM6T36CA 0.1%, 10ppm 17.8k 5600pF
1844236
36V

GND GND
GND GND D6_AFE1
R20_AFE1
1

1 2
SW_HV
49.9
Blue
AVSS_iso

R21_AFE1
AIN4 mV/TC/RTD/VBIAS
5.11k
C22_AFE1
C23_AFE1 D7_AFE1 8200pF
0.01µF SM6T36CA C24_AFE1
36V 0.1µF

GND C25_AFE1
8200pF
GND GND R22_AFE1
AIN6 mV/TC/RTD
5.11k
D8_AFE1 K3_AFE1
2 1 2 3
C26_AFE1
AVSS_iso
Blue HART_IN
0.1µF
C27_AFE1 D9_AFE1 R23_AFE1 1 4
0.01µF SM6T36CA SW_BURDEN
49.9
36V CPC1017N
R24_AFE1
AIN8 I
0.1%, 10ppm, 1/10W

5.11k
GND GND C28_AFE1
R25_AFE1 8200pF
27.4 C29_AFE1
0.1µF

GND C30_AFE1
8200pF
R26_AFE1
GND AIN9 I/IDAC1
TP4_AFE1
TP6_AFE1
TP5_AFE1 5.11k
R27_AFE1
AIN7 GND
5.11k
GND GND GND GND GND

Figure 3. AFE Schematic

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A basic requirement of such a universal design is a low terminal input count per channel to relax the real
estate at the terminals of an analog input module. By supporting the RTD 4-wire connection mode, a
minimum input count of four is given.
On the other hand, the ADC must have multiple input channels to separate the inputs path as much as
possible to maintain the highest performance. The ADS1262 has 10 analog input channels, which are
sufficient for this design.
Nevertheless, some signal switching is required to condense all supported measurement modes to the
four terminal inputs. Three isolated switches (K1, K2, and K3 of type CPC1017Ni from IXYS) are used to
route the I/O signals according to the selected mode. The function for each terminal is documented in
Table 2, and Figure 4 shows the assignments of the terminal pin number on the hardware. For more
information about the mode control, see Section 3.4.

Table 2. Terminal Functionality Overview

TERMINAL RTD (2- RTD (3- RTD (4- 4- to 20-
V mV (SE) mV (DIFF) CURRENT TC
INPUT WIRE) WIRE) WIRE) mA LOOP
T1 V — — — — tie to T2 tie to T2 RTD++ Loop+
T2 — mV mV+ mA+ TC+ RTD+ RTD+ RTD+ Loop–
T3 — GND mV– mA– TC– RTD– RTD– RTD– Tie to T4
T4 GND Tie to T3 GND GND — Tie to T3 RTD– – RTD– – Tie to T3

Figure 4. Terminal Pin Assignments

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The connection for each mode is shown in Figure 5.

1
2
V 3
High-voltage
4

V Low-voltage (SE)

V Low-voltage (DIFF)

A Current

TC

RTD 2-wire

RTD 3-wire

RTD 4-wire

Sensor
Transmitter 4- to 20-mA loop

Figure 5. Connection Diagram

Due to the independent input paths, the high-voltage mode can run in parallel with the low-voltage or
current inputs, making this design even more flexible and expanding the number of channels available by
two.
From a protection point-of-view, this AFE is designed per IEC61000-4-5 class 2. It can tolerate ±1-kV
(24-A) surge pulses. See Section 3.8 for more information about protection.
The following subsections examine the purpose of each terminal pin individually.

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3.1.1 Terminal Input T1

Terminal pin T1 is used for
• Voltage input in high-voltage mode
• 24-V output in 4- to 20-mA loop mode
• Excitation current output in RTD modes
In the high-voltage mode, the isolated switch K1 is open and K2 closed. The ±12 V is attenuated by the
R18:19 resistor divider bringing the input voltage to the input range of the ADS1262. The input resistance
is around 100 kΩ, but can be increased if required. See Section 4.1 for more information and test results.
In the 4- to 20-mA loop mode, the isolated switch K1 is closed and K2 is open. The nominal loop voltage
of 24 V is passed through D4 (pins 3-4) and K1 is finally available at T1.
In the RTD mode, the switch constellation is the same as in the loop mode. The ADC current source
IDAC0 is internally connected to AIN1. The RTD measurement is performed in a ratiometric manner,
meaning the current flowing through the RTD also flows through the precision reference resistor R16. The
voltage drop of R16 is used as a reference voltage for the ADC. The minimum accepted reference voltage
the ADS1262 is 0.9 V. With R16 = 4.99 kΩ and the excitation current of 250 μA, the reference voltage is
U = R × I = 4.99 kΩ × 250 μA = 1.2475 V.
Unfortunately, the current through RREF and RRTD will not be 100% the same. The leakage current of K2 is
around 4 nA at 85°C at the load pins (switched signal) with a load voltage, VL, of 60 V. The second
component where current is lost is the TVS diode D5. The leakage at the breakdown voltage, VBR, of 30.8
V is typical 1 nA at 85°C. However, the maximum voltage during RTD measurement at both K2 and D5 is
about 950 mV, which is much smaller than VL and VBR. This means that a much smaller leakage current
can be expected. Nevertheless, the error IRTD to IREF at the maximum voltages would be 0.0002% and,
therefore, is already at high voltages neglectable.
The 4- to 20-mA loop leakage is not an issue since the current leaks before it reaches the sensor
transmitter.

3.1.2 Terminal Input T2 and T3

T2 and T3 are the inputs for almost all measurement modes (except high-voltage mode). Internally, this
input is split in the voltage path and in the current path.
The voltage path measures the low-voltage (single-ended or differential), TC voltage and RTD voltage. No
additional semiconductor is attached, meaning only the differential anti-aliasing filter with a cut-off
frequency of 142 Hz separates the input of the system from the input of the ADC. Error sources, such as
noise, offset or distortion as introduced by amplifiers are avoided this way. The input range of the signal is
±2.2 V (±2.5 V with PGA disabled). The PGA can gain the input signal by factor 1, 2, 4, 8, 16, and 32
introducing multiple input ranges programmable by software.
Since the components of the anti-aliasing filter are in the signal path, high-performance part should be
used. C22, C24, and C25 are C0G/NP0 type capacitors with a 5% tolerance. The resistors are 1% metal
film.
The current path anti-aliasing filter uses the same parameter as the voltage path. The burden resistor,
R25, converts the current to measure into a proportional voltage accepted by the ADC input. When the
isolated switch K3 is closed, the particular channel is in current mode; otherwise the channel is in voltage
mode.
Using different ADC1262 input pairs for the voltage and current path has the advantage that the voltage
drop over K3 is not being measured in current mode — at the cost of more analog input channels being
used. The switch-on resistance, RDSON, of K3 varies between 3 and 16 Ω over temperature and would
make a high-precision measurement impossible. Here, only the voltage drop over R25 is measured,
meaning the precision of the measurement is only dependent on this component. This design uses a
0.1%, 10ppm part. The parameter of R25 is dependent on the system requirements. See Section 4.3 for
test results with the components used in this design.
The current mode is also used to measure the 4- to 20-mA loop. In addition, it provides the HART voltage
signal to the HART modem plug-in board (TIDA-00549) through C26.

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3.1.3 Terminal Input T4

T4 is the ground of the system. All ground-based signals must refer to T4. Floating signals, for example
from TCs, will leave this pin unconnected. Because the nominal analog supply voltage of the ADS1262 is
±2.5 V, it is also the mid-point of the analog input range.

3.2 Data Converter

The heart of the system is the ADS1262, a high-performance 32-bit ΔΣ ADC. It offers a high integration of
essential components required in an ADC signal chain, such as a PGA, a MUX, or a high-precision low-
noise voltage reference. This fact can drive down cost, complexity, and real estate of an analog input
module. Due to the high-dynamics range and the bipolar input of the ADC, a passive AFE is possible,
which avoids additional noise sources.
Although the ADS1262 already includes a high-precision internal clock (7.3728 MHz ±2%) and a precision
crystal in the system with ±50 ppm (equals ±0.005%), it depends on the application whether this external
crystal with a higher accuracy is required.

3.3 CJC
CJC is required for proper TC measurement (1). The local temperature measured at the terminal screws is
added to the temperature measured by the TC to obtain the correct temperature at the TC. The local
temperature is measured with the LMT01. The 2TO-92 package comes handy to measure the cold-
junction temperature where it is actually generated, at the terminal block (see Figure 6). The two large
pads (without solder masks) are thermally connected to T2 and T3 to mirror the temperature at the
terminal screws as accurate as possible. The LMT01 is glued to the pads in a way that the temperatures
of T2 and T3 influence the LMT01 equally.

Figure 6. LMT01 Mounting

(1)
For more information on the theory, please see TIDA-00189 Design Guide Isolated Loop Powered Thermocouple Transmitter Section 5
(TIDU449)

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The digital pulse-train output provides its (digital) information by two different currents (34 μA indicating a
logical '0', 125 μA indicating a logical '1'). By measuring the voltage drop, VDROP, of the connected burden
resistor R7 at the output of the LMT01, the information can be extracted. With the value of 1.65 kΩ, the
voltage is U= R × I = 1.65 kΩ × 34 μA = 56 mV ('0') and 206 mV ('1') (see Figure 7).
DVDD_iso DVDD_iso DVDD_iso DVDD_iso DVDD_iso DVDD_iso

R1_ADC1 R2_ADC1 R3_ADC1

6.65k 261k C4_ADC1 47k
0.1µF SPI_ISO_CLK

SPI_ISO_MOSI
GND
SW_TEMP R4_ADC1 SPI_ISO_CS
576k

8
U3_ADC1 U2_ADC1B SPI_ISO_MISO
8
U2_ADC1A 50mV/198mV LM2903PW
6
2 LM2903PW V+ 7
R5_ADC1 B
V+ 1 2 VP VN 1 5 V-
R6_ADC1 47k A
3 V-
101mV
340k

4
4

LMT01LPG R7_ADC1 R8_ADC1

R9_ADC1 1.65k 8.25k
47k 400mV

GND GND GND GND GND

Figure 7. LMT01 Schematics

This information is modulated onto the SPI MISO line, saving an isolated channel. Software ensures the
ADS1262 MISO line and the LMT01 output do not interfere. Once the LMT01 is enabled, every ~100 ms it
pushes a new pulse-train with the temperature information. The length (pulse count) of the pulse train is
dependent on the temperature value and is between 1 (corresponds to –49.9375°C) and 4096
(205.9375°C) pulses. With a nominal pulse frequency of 88 kHz and a maximum design operating
temperature of 125°C (2812 pulses) one pulse train has a maximum length of 88 kHz-1 × 2812 = 32 ms
(Figure 8 shows a screenshot at 25°C (1204 pulses = 13.6 ms)).

Figure 8. LMT01 Pulse Train at 25°C

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The minimum time of inactivity between two pulse trains at 125°C is > 68 ms. This is enough time to turn
off the LMT01 after the measurement (see Section 3.5 on how to control the LMT01). Figure 9 shows the
enabling of the LMT01, one pulse train, and the disabling of the LMT01. The disable time is time critical
and needs to be shorter than 68 ms. Otherwise the start of a second pulse train interferes with SPI
communication. The scope shows a time of 65 ms without optimization of the GPO switching.

Figure 9. Controlling the LMT01

The dual-comparator LM2903 in Figure 7 injects the pulse-train signal to the MISO line and turns on and
off the LMT01. Its open-drain output is high-Z when the voltage at the comparator’s negative input is
smaller than the voltage on the positive input.
For comparator U2B, this is the case when the LMT01 is not powered because the pulse-train burden
resistor R7 is connected to GND. Because the voltage at the positive input is fixed at around 100 mV and
higher than the negative input, the output is high-Z. When the LMT01 is enabled, the comparator just
copies the incoming pulse train to the output, but with CMOS compatible voltage 0 V (low) and 3.3 V
(high-Z).
The second comparator of the LM2903 is used to translate the signal SW_TEMP from range ±2.5 V to
0 or 3.3 V to turn on and off the LMT01. When the GPO is low, the comparator output is enabled and pulls
pin VP of the LMT01 low (disabled); otherwise, the output is high-Z, powering the LMT01 over R1.

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3.4 Signaling
Each universal input channel is equipped with four blue-colored mode LEDs (D1, D3, D6, and D8) visibly
outside the case by transferring the LED light using fiber optic channels. Three of the four LEDs (D3, D6,
and D8) are in series with the three optical switches K1, K2, and K3. This saves control signals and
provides direct feedback when current is flowing through the switches (switch on). The fourth LED (D1) is
software-programmable by the GPIO expander. As shown in Table 3, all modes can be clearly decoded
by D3, D6, and D8. One enhancement could be to turn on diode D1 in low-voltage or TC mode manually
to provide feedback in every mode (also switches are off in this mode).

Table 3. Mode LED Assignment

MODE D3 D6 D8 D1 LEDs

4- to 20-mA loop
On Off On On/Off
mode enabled

RTD mode enabled On Off On On/Off

Current mode
Off On/Off On On/Off
enabled

High-voltage mode
Off On On/Off On/Off
enabled

Low-voltage or TC
Off On/Off Off On/Off
mode enabled

Note that the high-voltage mode can work in parallel with the current mode and low-voltage or TC mode;
therefore, D6 can be either on or off here.
Additional three status LEDs (D2, D12, and D14) for each input channel and one global status LED (D11)
are available on board to provide feedback on supply voltages and enabled features. The status LEDs will
not be visible from the outside when the board is mounted in a case. Table 4 shows the function of each
status LED.

Table 4. Status LED Assignment

LED COLOR FUNCTION
D2 Red Software programmable
D11 Green 24-V DC available
D12 Green 4- to 20-mA loop enabled
D14 Green DVDD available (3.3 V)

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D11 is used to indicate feedback for the primary voltage (24-V DC from the PLC back-end power supply)
while D14 can be used to verify availability of proper isolated voltage (isolated power supply working
correctly). There is no separate indication of the analog supply rails (±2.5 V).

3.5 Isolated General Purpose Output

The TIDA-00550 requires at least six control signals to switch between the different modes. This design
uses programmable GPIOs of the ADS1262 to save the cost of additional isolator channels. The two
available GPIOs control an SN74HC594 shift register to provide the six required outputs. This shift register
has the advantage to support the extended temperature range of –40°C to 125°C at low cost. Both GPOs
from the ADS1262 (AIN5 and AIN7) are used to provide a simple synchronous serial bus to drive the
SN74HC594. AIN5 (or GPIO2) acts as clock and AIN7 (or GPIO4) as data line. Both pins are controlled by
writing to the ADS1262 GPIO data register (GPIODAT). Each level change of any of the GPO requires a
separate SPI transfer from the main controller, which is acceptable since the mode of the TIDA-00550
changes rather seldom. Figure 10 shows the connections to the serial bus of the expander.
AVDD_iso

C5_ADC1
0.1µF

AVSS_iso

U5_ADC1

16
VCC QA
15 SW_TEMP
R11_ADC1 13 1
RCLR QB SW_4_20MA
47k
C10_ADC1 12 2
RCLK QC SW_ASUPPLY
0.1µF
10 3 R12_ADC1
SRCLR QD
AVSS_iso 1.65k
GPIO2 11
SRCLK QE
4
SW_HV
AIN7 14
SER QF
5
SW_RTD_LOOP
6
QG SW_BURDEN
7 R13_ADC1
QH
475
9
QH'
1

2
8 D1_ADC1 D2_ADC1
GND
Blue 150120RS75000
Red
2

1
SN74AHC594PWR

AVSS_iso AVSS_iso AVSS_iso

Figure 10. Driving the GPIO Expander

Figure 11 shows a waveform screenshot. Signal C1 is measured at pin 11 (SRCLK) of the expander, C2
is measured at pin 13 (#RCLR), and C3 is measured at pin 14 (SER).

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Note that the SN74HC594 is connected to the AVDD/AVSS of the ADS1262, driving the GPO level to low
(AVSS) and high (AVDD), as displayed in Figure 11.

Figure 11. GPIO Access Waveforms

To provide a safe behavior of the design during operation mode changes, all output registers are cleared
first, new data is shifted in, and finally the new data are passed to the outputs.
1. Set C1 (SRCLK) low → RC (R11, C10) network gets discharged.
2. Wait until C2 (#RCLR) is low (outputs buffer cleared).
3. Clock in new data byte; make sure the high pulses of the clock signal are short to avoid energizing of
the RC network (In this example, the clock frequency is about 5 kHz).
4. Set C1 high (RC network energizes).
5. Wait until C2 (#RCLR) is high.
6. Apply an additional clock pulse to clock in the new data to output register.
7. Keep C1 high until next communication with the GPIO expander.

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The entire procedure takes about 42 ms, but can be adjusted by changing τ of the RC network. Figure 12
shows an example communication. In this case, the high-voltage mode will be enabled. By sending value
0x10 (most-significant bit first), the output QE (high-voltage mode enabled) of the SN74AHC594 is driven
high.

Figure 12. GPIO Expander Data Shift

The different modes are selected by the GPIO expander output. Table 5 provides information about the
GPO patterns to set a certain mode.

Table 5. GPO Signal to Mode Mapping

GPO SIGNALS V mV TC 4- to 20-mA LOOP RTD
SW_TEMP 0 0 0/1 (1) 0 0
SW_4_20MA 0 0 0 1 0
SW_ASUPPLY 0 0 0 0 1
SW_HV 1 0 0 0 0
SW_RTD_LOOP 0 0 0 1 1
SW_BURDEN 0 0 0 1 0
(1)
Signal SW_TEMP enables the LMT01 and is enabled occasionally only. No TC measurement can be performed when the local
temperature measurement is on progress. See Section 3.3.

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3.6 Data Isolation

The ISO7141CC isolates the data between the field and the PLC side. It supports the minimum required
number of four channels to support a 4-wire SPI. Although equipped with enable capability the
ISO7141CC is always on. The reason is the pulse train from the local temperature sensor LMT01, which is
delivered independently of the SPI bus, but sharing the SPI_MISO line. However, there is still the option to
enable or disable the isolator by an additional GPO from the host processor to save power.
The SPI_MISO line must still be gated by the SPI_CS signal because multiple universal input channels
may share a SPI. Component U4, a single-gate buffer SN74LVC1G125, passes the SPI_MISO signal if
SPI_CS is low. The pulse train signal is asynchronous to the SPI_CS signal, and thus must be monitored
independently when a pulse train from the LMT01 is expected (LMT enabled).

3.7 Power
The power section is split in the PLC-side part and in the field-side part. To power the board a nominal
voltage of 24-V DC (operating range: 16-V to 33-V DC) is provided from the PLC side. Due to the low
power consumption of the board (< 400 mW), a power connection from the field side is not provided to
avoid additional protection.

3.7.1 Input Stage

This TI Design can be powered in two ways. The primary option is to connect the nominal 24-V DC to J2.
When the board is used in conjunction with a BeagleBone Black, it can be powered from the provided 5-V
DC by header P9. The TPS61093, a 17-V DC step-up converter, boosts the 5-V DC to around 16.5-V DC,
which is still in the accepted supply voltage range. The step-up converter is disabled if a valid voltage is
detected on connector J2. Status LED D11 is turned on if the board has a proper input voltage from either
input.

3.7.2 Isolated Power Supply

The provided input voltage passes a PI-filter for bidirectional filtering and then connects straight to the
LM5017, a constant on-time synchronous buck regulator. It will buck the input voltage to 10 V. This is just
enough to operate the LM5017 internal LDO from the secondary voltage instead of the higher input
voltage, thus decreasing power dissipation of the LM5017. The switching frequency of the converter is
around 264 kHz to keep the efficiency high and the harmonics away from the sensitive ADS1262
modulator frequency, fMOD, of 921.6 kHz. With nearest harmonics at 793 kHz (third harmonic) and 1.057
MHz (fourth harmonic), fMOD is located about in the middle.
The converted voltage is connected to the primary winding of a customized transformer from company
Würth Electronics (see Section 5.2 for an orderable part number). It provides the following voltages at the
secondary side:
• 30-V DC for a 24-V DC loop power supply
• 5.6-V DC for a 3.3-V DC digital power (DVDD) and a 2.5-V DC analog positive rail (AVDD)
• –5.6-V DC for a –2.5-V DC analog negative rail (AVSS)

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3.7.3 Point-of-Load (POL) Power Supplies

The three voltages from the transformer are rectified by standard diodes before they are passed to the
LDOs.
The LDO TLV70433 (U13) provides 3.3-V DC to supply the digital part of the ADS1262, the ISO7141CC,
and the LM2903.
The TPS7A4901 (U14) and TPS7A3001 (U16) are high-performance LDOs supplying the analog section
of the ADS1262 with a positive voltage, AVDD, and a negative voltage, AVSS. This power supply allows
direct measurement of bipolar signals without additional signal.
AVSS can be in range of –2.5-V DC to 0 V while AVDD must always be AVSS + 5-V DC. This way,
unipolar and bipolar power supplies are supported. The default analog supply of the ADS1262 in this
design is ±2.5-V DC, but the TIDA-00550 has the capability to shift this supply to –1.7-V DC and 3.3-V
DC. The main reason for this feature is to support the RTD measurement (see Section 3.7.4 for more
information), but is not limited to it. The GPO signal SW-ASUPPLY is responsible for the voltage selection
(low = ±2.5-V DC, high = –1.7-V DC and 3.3-V DC). It drives a MOSFET on each rail changing the ratio of
each LDO feedback resistors and setting the target voltage this way. It is unlikely that both voltages switch
at the same time causing lower and higher voltages in range 4.2-V to 5.8-V DC. This voltage range can be
safely handled by the ADS1262.
AVDD_iso

AVDD_iso

U14_PWR2
C45_PWR2R55_PWR2
0.01µF 113k C46_PWR2 D17_PWR2
8 1
IN OUT MMSZ4685-V
10µF
3.6V
5 2
EN FB
6 3
NR/SS NC
R56_PWR2
R57_PWR2GND GND
7 4 100k 169k
DNC GND
C48_PWR2 9
PAD
0.01µF
TPS7A4901DRBR Q4_PWR2
3

2N7002KW
1 SW_ASUPPLY
SW_ASUPPLY
R58_PWR2
GPIO Low: 2.5V (default)
2

47k GPIO High: 3.3V

GND GND GND GND AVSS_iso

AVSS_iso

AVSS_iso

U16_PWR2
C51_PWR2R60_PWR2 R61_PWR2 MMSZ4682-V
8 1 0.01µF 113k 47k D18_PWR2
C52_PWR2 2.7V
2

IN OUT
10µF
5 EN FB 2 1

3 NC NR/SS 6 Q5_PWR2
3

2N7002KW GND GND

7 DNC GND 4
C58_PWR2 9 R66_PWR2 SW_ASUPPLY
PAD
10µF C59_PWR2 73.2k
TPS7A3001DRBR 0.01µF GPIO Low: -2.5V (default)
GPIO High: -1.7V

R69_PWR2
100k

GND GND GND GND

Figure 13. Bipolar Power Supply

The DVDD, AVDD, and AVSS supply rails integrate Zener diodes (D15, D16, and D18) to ensure the
voltage never lifts up above absolute maximum voltages harming the integrated circuits by providing low
impedance to ground. Such voltages may be generated by a surge at the terminal pins. For more details,
see Section 3.8.

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3.7.4 Current-Limiting 24-V DC Power Supply

The current-limiting 24-V DC power supply is designed to drive remote devices (for example, sensor
transmitters) with a 4- to 20-mA loop interface (see Figure 14). As long as the loop stays in its normal
operating conditions, up to 25-V DC are delivered at terminal pin 1. If more than about 22 mA are drawn
the power supply will slowly enter the current-limiting state by decreasing the output voltage. The current
limiting circuit is located at high-side, meaning the current set by the remote device will be flowing through
the burden resistor for most accurate results because no additional current monitor between the loop-
powered device and the burden resistor is required. The supply can be enabled and disabled by the signal
SW_4_20MA.
The isolated power supply transformer provides a separate secondary winding for the power supply. The
wide input range LDO TPS7A4101 (U12) regulates the 30 V from the transformer to 25 V. The current
drawn is constantly monitored by the R46/Q2. The voltage drop across R46 generates the basis-emitter
voltage, VBE, of the PNP transistor Q2. If the current increases, VBE also increases, causing Q2 to start
conducting. The upper feedback resistor R48 of the LDO is connected to the collector and emitter of Q2,
which will lower the resistance and increase the feedback voltage of the LDO, VFB. This will decrease the
output voltage.
Another reason to use this topology is the simple injecting of the HART transmitter signal. The HART
signal provided by the TIDA-00549 is directly fed into the feedback node of the LDO (signal HART_OUT).
25V@20mA
U12_PWR2A
25V R46_PWR2
8 1
IN OUT 4-20mA LOOP
20.5

2
R47_PWR2 5 2 C40_PWR2
R48_PWR2
EN FB R49_PWR2
C41_PWR2 47k 4.7µF 953k 1
2.2µF EP GND
5.11k
Q2_PWR2
9

3
GND BC856A-7-F
3

TPS7A4101DGNR
1 Q3_PWR2
2N7002KW
2

R51_PWR2 R52_PWR2 R53_PWR2

47k 953k 47k

GND AVSS_iso GND GND C42_PWR2

270pF GND
HART_OUT

SW_4_20MA

Figure 14. 4- to 20-mA Loop Supply

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3.8 Protection
Protection against surges is an important property of every component used in factory automation and
control. Take care with any interface to the outside world. In this design, the terminal pins are protected
because these pins are the only connection to the outside. Having protection at analog signals is always a
tradeoff because the leakage of the protection will have influence to the sensitive signal to measure. For
instance, inappropriate protection may decrease the input impedance of an analog signal due to leakage,
unnecessarily loading the signal source. Protection of the power supply is not implemented here. It is
assumed that the power supply embedded in the PLC uses already sufficient protection. For more
information on power supply protection (and much more), see the TI Design TIDA-00233 (1).
To protect the signal lines, the TIDA-00550 uses primarily TVS diodes to clamp excessive high and low
voltages to ground. As an additional requirement, all terminal pins must be tolerant to steady PLC power
supply voltages. Unlike in a surge event, a PLC power supply up to 33 V can be connected for a longer
period of time because of incorrect wiring during installation. For this event, no significant current should
flow into the board. With this requirement, the breakdown voltage, VBR, is given directly. The bidirectional
TVS diode SM6T36CA has a nominal VBR of 36 V, where 1 mA will flow through the TVS diode. This
means at PLC power supply level (up to 33 V) the TVS diode will have no effect and the voltage will be
seen by the AFE. The sensitive part of the front-end are the analog inputs of the ADS1262. The internal
ESD diode will start conducting 0.3 V beyond the analog supply rail, which is ±2.8 V. The design has to
ensure that the current does not exceed 10 mA through the ESD diodes. Therefore, each analog input is
protected by a 5.11-kΩ resistor. At 33 V, the current through an ESD diode will be
IESD = (33 V – 2.8 V) / 5.11 kΩ = ~6 mA. See Figure 15 for the schematics.

(1)
See the product folder at http://www.ti.com/tool/TIDA-00233

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J1_AFE1
1
2
3
4
C20_AFE1 D5_AFE1
1844236 0.01µF SM6T36CA
36V

GND GND

C23_AFE1 D7_AFE1
0.01µF SM6T36CA
36V

GND GND

C27_AFE1 D9_AFE1
0.01µF SM6T36CA
36V

GND GND

GND
TP4_AFE1
TP6_AFE1
TP5_AFE1

GND GND GND GND

Figure 15. Input Protection

The protection circuit gets more challenged if a surge happened at the terminal pins. The target is that a
class 2 (±1-kV) surge with a current of 24 A (42-Ω resistance requirement for non-power lines) can be
handled without damaging the board, according to EN61000-4-5.
On such an event the TVS diode will still try to clamp the ±1 kV to its nominal VBR of 36 V, but the dynamic
resistance of the TVS diode, RD, will now come into play. The resulting clamping voltage, VCL, which is
seen by the circuitry, will be higher than VBR. With a peak pulse current, IPP, of 24 A and RD = 0.427 Ω, the
value of the VCL increases to RD × IPP + VBR = 48.05 V at 25°C ambient temperature. In a worst case
scenario with an ambient temperature of 125°C, VCL even rises to 50.04 V. This voltage can still be
handled by the ADS1262 input pin. The maximum current over the internal ESD diode is now ~9.3 mA.
The capacitors C20, C23, and C27 in front of the TVS diodes are supposed to help the diodes to catch the
steep surge pulse.
The protection circuit will have some impact on the analog input signal under normal conditions. The TVS
diode will drain a leakage current, IRM, of maximal 1000 nA at the stand-off voltage, VRM, of 30.8 V and
85°C ambient temperature. For the high-voltage input the input impedance is 100 kΩ due to the resistor
divider. The impedance change through the TVS diode leakage is negligible. For the low-voltage input, the
maximum input voltage over the diode is ±2.5 V, which is less than 10% of VRM. With a typical IRM of 100
nA at VRM, a typical leakage current of < 10 nA can be expected decreasing the input impedance from 1
GΩ to about 250 MΩ. For the current measurement with its worst-case 18 bits (noise-free) resolution the
leakage current is lower than ½ LSB and therefore also not relevant.
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3.9 RTD Measurement

RTDs measure the temperature at a remote location. The resistance of the element changes with
temperature, thus providing information by a voltage drop when a constant current is applied. In Factory
Automation, two approaches are used.
The first option is the use of a so-called sensor transmitter (2). The sensor transmitter measures and
processes the temperature and sends the information over a 4- to 20-mA loop to the current input of an
analog input module. This option is supported by TIDA-00550 in the 4- to 20-mA loop mode. The second
option is the direct connection of an RTD. No additional hardware is required between the RTD and the
input of the analog input mode. This option is also supported and is discussed in this chapter.
The ADS1262 integrates all required features for a direct RTD measurement, such as two matched
current sources, support of an external differential reference for ratiometric measurement, as well as
enhanced features like rotating current sources to eliminate variances in the two current sources. A
temperature using RTD can be measured in three ways: the 2-wire, 3-wire and 4-wire connection scheme.
This design supports all three measurements methods.
RTD elements are available in different accuracy classes. To achieve this accuracy, the wire resistance
must be compensated. An AWG24 wire with a diameter of 0.511 mm (0.0201 in) has a resistance of
84.2 mΩ/m (25.67 mΩ/ft). Assuming the RTD sensor is 50 m (164 ft) away from the PLC, the resistance of
a 2-wire connection sums up to 2 × 50 × 84.2 mΩ = 8.45 Ω. With the RTD resistance of 100 Ω at 0°C
(Pt100), the error would be more than 8% at this temperature point and even more at lower temperatures.
The 3-wire and 4-wire connection schemes address this issue.
The supported Pt100 covers the temperature range from –200°C to 850°C. Within this area, the resistance
of the RTD element changes from 18.52 to 390.48 Ω. The °C/R curve is nonlinear. Typically, the
microprocessor unit compensates using a look-up table and interpolation.
The selected components in this design work with a constant RTD current, IRTD, of 250 μA. Other currents
are also possible, but need a change of the reference resistor, RREF. See Table 6 for a comparison of
different IRTD. While the first three columns use the minimum reference resistor value for a certain IRTD
(resulting in the minimum required reference voltage, VREF, of 0.9 V), the last column shows the actual
configuration in the design. The nominal AVDD voltage of 2.5-V DC is not sufficient for 250- and 500-μA
operation. Also for 100 μA, the margin is very small. For this reason, the analog power supply of the
ADS1262 is shifted up by 800 mV with AVSS = –1.7-V DC and AVDD = 3.3-V DC for all RTD
measurements. This provides enough of a margin also for higher IRTD currents. This feature is not limited
to the RTD mode. It can be also used to adjust the analog input range in other modes. The TIDA-00550
uses a reference resistor of 4.99 kΩ to protect AIN1 from surges at the same time. See Section 3.8 for
more details on protection.
(2)
See TI Design TIDA-00851 for an example (http://www.ti.com/tool/TIDA-00851)

Table 6. RTD Current Comparison

USED
CASE LOWER CURRENT USED CURRENT HIGHER CURRENT
CONFIGURATION
Excitation current (µA) 100 250 500 250
Reference resistor (kΩ) 9000 3600 1800 4990
Reference voltage (V) 0.9 0.9 0.9 1.2
Min IDAC voltage (V) 1.1 1.1 1.1 1.1
Max RTD V-drop (V) 0.039 0.098 0.195 0.098
Diode V-drop (V) 0.4 0.4 0.4 0.4
50-m wire V-drop (V) 0.001 0.002 0.004 0.002
Min AVDD (V) 2.44 2.5 2.599 2.847
PGA gain (V/V) 16 8 4 8

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IRTD takes a certain path for RTD measurements (see also Figure 16 for component names). First, it flows
through RREF (R16) used to generate VREF for the ratiometric measurement. With RREF = 4.99 kΩ and
IRTD = 250 µA, VREF is about 1.25 V. Next, IRTD passes diode D4. This diode protects inputs AIN1, AIN2,
and AIN3 from the 24-V 4- to 20-mA loop power (Mode IV). The next component, the isolated switch K1,
is required to disconnect the RTD reference from the high-voltage input in Mode I (this mode accepts
±12.39 V at the input). Finally, IRTD appears at the terminal pin 1 where the RTD is connected.

3.9.1 2-Wire RTD Measurement

The 2-wire mode is the simplest and cheapest, but also the most imprecise measurement method. The
RTD connects to the PLC input module with only two wires. The constant current IRTD (from IDAC0) is
carried over the connection wires and, thus, the measurement of the RTD also includes these wires. The
resistance of the wires, RLEAD, causes a voltage drop, which is measured along the actual RTD resistance
RRTD. This method should only be used for short, low-impedance wires to minimize this error. The
temperature-dependent resistance of the wires does not allow a simple subtraction of the wire resistance
from the measurement. Figure 16 shows the current flow (red lines) and the measurement path (green
lines) for the 2-wire connection.
D3 250uA
R15 A IN1 I DA C0
1 2
S W_RTD _LOOP A VS S_iso
49.9
B lue
1

2 A VS S_iso R14
K1 A IN2 RE FP
5.11 k
CP C1017N
C17

0.01%, 5ppm
8200pF

1.2475V
D4 R16 C18
4 3 4.99k 0.1µF
4-20m A LOOP
5 2 GND C19
8200pF
R17
4

6 1
A IN3 RE FN
5.11 k
B AS 70J W-7-F

J1
1 R18
A IN0 V
2 82.5k
4

3
3

t 1844236
4
C20
0.01µF
D5
S M6T36CA
K2
CP C1017N
0.1%, 10ppm
R19
17.8k
C21
5600pF
36V

GND GND
GND GND D6
R20
1

1 2
S W_HV
49.9
B lue
A VS S_iso

R21
A IN4 m V/TC /RTD /V BI AS
5.11 k
C22
C23 D7 8200pF
0.01µF S M6T36CA C24
36V 0.1µF

GND C25
8200pF
GND GND R22
A IN6 m V/TC /RTD
5.11 k
D8 K3
2 1 2 3
C26
A VS S_iso
B lue HA RT _I N
0.1µF
C27 D9 R23 1 4
0.01µF S M6T36CA S W_B URDE N
49.9
36V CP C1017N
R24
A IN8 I
0.1%, 10ppm, 1/10W

5.11 k

GND GND C28

R25 8200pF
27.4 C29
0.1µF

GND C30
8200pF
R26
GND A IN9 I/I DA C1
TP 4 TP 6 TP 5 5.11 k
R27
A IN7 GND
5.11 k

GND GND GND GND GND

Figure 16. RTD 2-Wire Connection

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3.9.2 3-Wire RTD Measurement

The 3-wire method is most common. It is a good trade-off between accuracy and cost of wire. In this
connection scheme, two current sources, IDAC0 and IDAC1 of the ADS1262, are used. Both currents are
injected on the measurement wires, like in the 2-wire connection. Assuming the wires have the same RLEAD
and the current from the sources match, both voltage drops across RLEAD are subtracted from the equation.
Both currents will flow towards ground with the third wire.
To compensate for current mismatches of the sources, the IDAC rotation feature has been implemented in
the ADS1262. Two consecutive measurements are averaged, the first with IDAC0 at AIN1 and IDAC1 at
AIN9 and the second with IDAC0 at AIN9 and IDAC1 at AIN1, thus removing the mismatch of both current
sources.
D3 250uA
R15 A IN1 I DA C0
1 2
S W_RTD _LOOP A VS S_iso
49.9
B lue

2
A VS S_iso R14
K1 A IN2 RE FP
5.11 k
CP C1017N
C17

0.01%, 5ppm
8200pF

1.2475V
D4 R16 C18
4 3 4.99k 0.1µF
4-20m A LOOP
5 2 GND C19
8200pF
R17

3
6 1
A IN3 RE FN
5.11 k
B AS 70J W-7-F

J1
1 R18
A IN0 V
2 82.5k

3
3

t 1844236
4
C20
0.01µF
D5
S M6T36CA
K2
CP C1017N
0.1%, 10ppm
R19
17.8k
C21
5600pF
36V

GND GND
GND GND D6
R20

2
1 2
S W_HV
49.9
B lue
A VS S_iso

R21
A IN4 m V/TC /RTD /V BI AS
5.11 k
C22
C23 D7 8200pF
0.01µF S M6T36CA C24
36V 0.1µF

GND C25
8200pF
GND GND R22
A IN6 m V/TC /RTD
5.11 k
D8 K3
2 1 2 3
C26
A VS S_iso
B lue HA RT _I N
0.1µF
C27 D9 R23 1 4
0.01µF S M6T36CA S W_B URDE N
49.9
36V CP C1017N
R24
A IN8 I
0.1%, 10ppm, 1/10W

5.11 k

GND GND C28

R25 8200pF
27.4 C29
0.1µF

GND C30
8200pF
R26
GND A IN9 I/I DA C1
TP 4 TP 6 TP 5 5.11 k
R27
A IN7 GND
5.11 k

GND GND GND GND GND

Figure 17. RTD 3-Wire Connection

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3.9.3 4-Wire RTD Measurement

The 4-wire connection is more costly due to the required four wires. Nevertheless, it is quite straight
forward due to its symmetry and delivers the most accurate results. Two wires are connected to each of
the RTD leads. One pair supplies the current; the other pair measures the voltage. There is no
overlapping of supply lines and measurement lines at all. The measurement input of the ADS1262 has an
impedance of > 250 MΩ. Therefore, the error from the voltage drop over the measuring wires is less than
1 ppm.
D3 250uA
R15 A IN1 I DA C0
1 2
S W_RTD _LOOP A VS S_iso
49.9
B lue

2
A VS S_iso R14
K1 A IN2 RE FP
5.11 k
CP C1017N
C17

0.01%, 5ppm
8200pF

1.2475V
D4 R16 C18
4 3 4.99k 0.1µF
4-20m A LOOP
5 2 GND C19
8200pF
R17

3
6 1
A IN3 RE FN
5.11 k
B AS 70J W-7-F

J1
1 R18
A IN0 V
2 82.5k

3
3

t 1844236
4
C20
0.01µF
D5
S M6T36CA
K2
CP C1017N
0.1%, 10ppm
R19
17.8k
C21
5600pF
36V

GND GND
GND GND D6
R20

2
1 2
S W_HV
49.9
B lue
A VS S_iso

R21
A IN4 m V/TC /RTD /V BI AS
5.11 k
C22
C23 D7 8200pF
0.01µF S M6T36CA C24
36V 0.1µF

GND C25
8200pF
GND GND R22
A IN6 m V/TC /RTD
5.11 k
D8 K3
2 1 2 3
C26
A VS S_iso
B lue HA RT _I N
0.1µF
C27 D9 R23 1 4
0.01µF S M6T36CA S W_B URDE N
49.9
36V CP C1017N
R24
A IN8 I
0.1%, 10ppm, 1/10W

5.11 k

GND GND C28

R25 8200pF
27.4 C29
0.1µF

GND C30
8200pF
R26
GND A IN9 I/I DA C1
TP 4 TP 6 TP 5 5.11 k
R27
A IN7 GND
5.11 k

GND GND GND GND GND

Figure 18. RTD 4-Wire Connection

3.10 Optional Hart Communication

The TIDA-00549 is a plug-in board for the TIDA-00550, extending its functionality with HART. The
TIDA-00550 includes two sockets per channel to connect the HART modem hardware. The TIDA-00549
has its own isolation and connects through UART to the back end.
The received HART signal is decoupled from the 4- to 20-mA current by C26. Signal conditioning is done
on the HART board. The HART signal to be send to sensor transmitters is connected to the feedback loop
of the 4- to 20-mA loop LDO (U12). This provides a very power efficient method to modulate the HART
signal on top of the 4- to 20-mA current. Figure 19 shows the HART modem board.

Figure 19. Picture of the HART Modem Board (TIDA-00549)

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4 Test Setup and Results

This section shows the test results of the TIDA-00550. Test software (not provided) has been written on
the MSP430FR5969 LaunchPad (Figure 20) handling the SPI of the TIDA-00550. A separate capture input
of the MSP430 counts the pulses from the LMT01. The user interface is a simple command line terminal
allowing user input settings, which is basically the mode selection and read/write capability of the
ADS1262 register bank (see Figure 21). The register access is important to get and set the gain and offset
register values of the ADS1262.

Figure 20. MSP430FR5969 LaunchPad Figure 21. Test Program Options

The user interface can also be set to quiet mode with very limited feedback. This mode is used by an
automated test environment (ATE). The test script is written in python and connects the TIDA-00550 with
the ATE including
• Climate chamber T40/25 from CTS
• 8.5-digit digital multimeter (DMM) 3458A from HP
• Source Measurement Unit Agilent B2912A from KeySight
• Power Supply E3631A from Agilent
• MSP430FR5959 LaunchPad from Texas Instruments
• RTD simulator Type 1049 from Time Electronics
• Resistor Ladder R1-3000 from CMT
• Standard PC
The raw test results are written to a .csv file for further data processing.

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4.1 Mode I (High-Voltage) Measurements

With the bipolar power supply set to ±2.5-V DC and the internal PGA enabled (gain = 1 V/V), the
ADS1262 samples a terminal single-ended input voltage value up to ±12.39 V at terminal pins 1 and 4.
The resistor divider R18:R19 provides a fixed attenuation of about 15 dB, converting the input signal to
±2.2 V suitable for the ADS1262 input. The absolute resistor tolerance of 0.1% provides a stable
attenuation and can be relaxed if gain calibration is performed during production. More important is the
temperature stability to maintain optimum results over temperature. The selected value of 10 ppm is a
good trade-off between cost and stability.
The maximum voltage drop over the on-resistance of the isolated switch, RDSON, can be neglected
because the 0.1% tolerance of R18 is about 10 times higher than RDSON and therefore the dominating
factor in the equation of the signal attenuation.
The external antialiasing filter together with the circuitry inside the ADS1262 has its –3-dB corner
frequency at around 1000 Hz and –100-dB attenuation at around 921 kHz; providing effective signal
suppressing around the delta-sigma modulator frequency (see Figure 22).

Figure 22. High-Voltage Anti-Aliasing Filter Curve

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To measure DC performance of an ADC, the input must be set to a heavily decoupled constant input
voltage while a series of samples are taken. Due to the symmetrical bipolar ADC input range, the input is
shorted to GND to perform DC measurements. The analog input is shorted to ground at the terminal pins
of the board to include the AFE to the measurement (Figure 23).

Climate chamber
CTS
T-40/25

Isolation
1 TIDA-00550 24-V DC PSU
2 (One channel) Agilent
E3631A
3
4

3.3-V DC
SPI

UART MSP430FR5969
Host PC
LaunchPad

Figure 23. Test Setup for High-Voltage Noise Measurement

Figure 24 to Figure 26 show the histograms for signals samples with 20 SPS at temperatures 25°C, 85°C,
and –35°C. Figure 27 to Figure 29 are taken at the same temperature points, but with 2400 SPS to use
the entire bandwidth of the high-voltage input path. No calibration has been performed to show the overall
system offset, which is at about 340 μV and nearly constant over temperature.

180 180
Mean: 335.396 µV Mean: 337.534 µV
160 STD: 0.2695 µV 160 STD: 0.3075 µV

140 140
Number of Occurrences

Number of Occurrences

120 120

100 100

80 80

60 60

40 40

20 20

0 0
334.5 335 335.5 336 336.5 336.5 337 337.5 338 338.5 339
Output Voltage (µV) D002
Output Voltage (µV) D003

Figure 24. Distribution at 25°C and 20 SPS Figure 25. Distribution at 85°C and 20 SPS

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180 800
Mean: 342.959 µV Mean: 335.416 µV
160 STD: 0.2864 µV 700 STD: 4.2736 µV

140
Number of Occurrences

Number of Occurrences
600
120
500
100
400
80
300
60
200
40

20 100

0 0
341.5 342 342.5 343 343.5 344 318 323 328 333 338 343 348
Output Voltage (µV) D004
Output Voltage (µV) D005

Figure 26. Distribution at –35°C and 20 SPS Figure 27. Distribution at 25°C and 2400 SPS

700 800
Mean: 337.787 µV Mean: 343.364
600 STD: 4.6049 µV 700 STD: 4.2890 µV
Number of Occurrences

Number of Occurrences
600
500
500
400
400
300
300
200
200

100 100

0 0
320 325 330 335 340 345 350 355 325 330 335 340 345 350 355 360
Output Voltage (µV) D006
Output Voltage (µV) D007

Figure 28. Distribution at 85°C and 2400 SPS Figure 29. Distribution at –35°C and 2400 SPS

As expected, the distribution follows a Gaussian curve. Based on the standard deviation of the Gaussian
curve, important DC parameters can be calculated. The effective number of bits (Equation 1) and noise
free bits (Equation 2) can be directly calculated:
æ 2N ö
Effective  bits = log 2 ç              [N = 32]
ç stddev (histogram ) ÷÷
è ø (1)
The number of noise-free bits is 6.6× the standard deviation, or 2.7 bits less than the effective bits, making
sure 99.9% of all samples are included.
æ 2N ö
Noise-free  bits = log 2 ç = Effective  bits - 2.7  bits
ç stddev (histogram ) ´ 6.6 ÷÷
è ø (2)
With the obtained effective bits and noise-free bits, the input referred noise can be calculated by taking the
range of the input range (dependent on gain) into account (Equation 3 and Equation 4). The full-scale
range is –2.5 V to 2.5 V = 5 V.
æ Full-scale  range ö
ç ÷
RMS noise  µV RMS =   è
( ) ø
Gain
2 effective  bits (3)
æ Full-scale  range ö
ç ÷
Peak noise  µV PP =   è
( ) ø
Gain
noise-free  bits
2 (4)

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Table 7 shows the performance for various temperatures and two data rates.

Table 7. High-Voltage Mode DC Performance at Various Data Rates and Temperatures

DATA RATE EFFECTIVE NOISE-FREE
TEMP (°C) NOISE (µVRMS) NOISE (µVPP) FILTER
(SPS) BITS BITS
20 –35 24.0 21.3 0.287 1.890 SINC4
20 –20 23.9 21.2 0.301 1.984 SINC4
20 0 24.0 21.3 0.285 1.881 SINC4
20 25 24.1 21.4 0.270 1.779 SINC4
20 55 24.0 21.3 0.289 1.907 SINC4
20 85 23.9 21.2 0.308 2.029 SINC4
2400 –35 20.1 17.4 4.289 28.305 SINC1
2400 –20 20.1 17.4 4.224 27.875 SINC1
2400 0 20.1 17.4 4.166 27.494 SINC1
2400 25 20.1 17.4 4.274 28.203 SINC1
2400 55 20.1 17.3 4.396 29.010 SINC1
2400 85 20.0 17.3 4.605 30.389 SINC1

The nominal data rate of 20 SPS was selected for slowly changing (DC-like) signals. For example, if AC
signals with a bandwidth up to 1 kHz (anti-aliasing filter limit), a data rate of 2400 SPS with SINC1 filter
can be used. This combination provides a –3-dB corner frequency of 1015 Hz.
Another key parameter is the error of the signal chain across the full input range. The test setup uses the
SMU B2912A to generate the analog input voltage. The 8.5-digit DMM 3458A measures the voltage and
will be used as a reference voltage to measure the error. The setup is drawn in Figure 30.

DMM Climate chamber

HP CTS
3458A T-40/25
Isolation

SMU + 1 TIDA-00550 24-V DC PSU

Keysight 2 (One channel) Agilent
B2912A E3631A
3
- 4
3.3-V DC
SPI

UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 30. Test Setup for High-Voltage Full Input Range

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The result is plotted in Figure 31 and Figure 32. Gain calibration was performed at 25°C only. Calibration
at other extreme temperature points like –35°C and 85°C might not be feasible during production, but
would lead to a smaller error over the entire temperature range, especially since the error is quite linear
over the entire input range.

0.0010% 0.04%
25°C
0.03% 85°C
± ƒ&
0.0005% 0.02%

0.01%
Error

Error
0.0000 0

-0.01%

-0.0005% -0.02%

-0.03%

-0.0010% -0.04%
-100% -50% 0 50% 100% -100% -50% 0 50% 100%
VIN Percent of FSR D008 VIN Percent of FSR D009

Figure 31. Input Error at Room Temperature Figure 32. Input Error at 25°C, 85°C, and –35°C

At calibration temperature, the error is maximal 0.001% (~124 µV). Over temperature range, especially at
cold temperatures, the error increases up to 0.035% (~4.3 mV).
All measurements use a gain of 1 V/V in this mode, using the entire voltage range of ±12.39 V. Input
signals up to ±6.195 V can use a gain of 2 V/V and input signals up to ±3.0975 V can use a gain of 4 V/V.
Signals below ±2.2 V should be measured with the low-voltage mode because the signal is already within
the ADS1262 native input range.

4.2 Mode II (Low-Voltage) Measurements

The low-voltage path passes the signal straight to the input of the ADS1262 to avoid additional noise
sources, offset, and gain error.
The maximum absolute voltages to terminal pins T2/T3 are ±2.2 V (PGA enabled) and ±2.6 V (1) (PGA
disabled). This is not to be confused with the differential input voltage, VIN, which is the difference of the
positive and the negative voltage — the actual measured information. The maximum VIN for each PGA
gain setting is shown in Table 8.
(1)
Note the ADS1262 can measure beyond the supply rails if PGA is disabled.

Table 8. Full-Scale Voltage Input Ranges

PGA GAIN (V/V) FULL SCALE RANGE
1 ±2.2 V
2 ±1.25 V
4 ±0.625 V
8 ±0.3125 V
16 ±0.15625 V
32 ±0.078125 V
Bypass ±2.6 V

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The minimum and maximum absolute voltages on the positive input, VINP, and on the negative input, VINN,
are dependent on the PGA gain, the differential input voltage, and the tolerance of the power supply
voltages AVDD and AVSS:
space
(Gain - 1)
V INP >   AVSS + 0.3 V + V IN ´
2
(Gain - 1)
V INN <   AVDD - 0.3 V - V IN ´
2
The anti-aliasing filter has a cut-off frequency of 142 Hz, making it suitable for DC signals. If more
bandwidth is required, the cut-off frequency can be adapted.

Climate chamber
CTS
T-40/25

Isolation
1 TIDA-00550 24-V DC PSU
2 (One channel) Agilent
E3631A
3
4
3.3-V DC
SPI

UART MSP430FR5969
Host PC
LaunchPad

Figure 33. Test Setup for Low-Voltage Noise Measurement

Performance measurements of DC-like signals are important to understand how many effective and noise-
free bits can be expected from slowly changing signals like temperature sensors deliver. Figure 34 to
Figure 36 show the histogram for a gain of 1 V/V for various temperatures while Figure 37 to Figure 39
show measurements with a gain of 32 V/V. As expected, the mean and standard deviation at a gain of
32 V/V is about 32 times lower than a gain of 1 V/V due to the reduced analog input range. All histograms
are uncalibrated, meaning no offset calibration or chopping, to show the system offset.

140 200
Mean: 349.050 µV Mean 345.212 µV
120 STD: 0.2799 µV STD: 0.3131 µV
Number of Occurrences

Number of Occurrences

150
100

80
100
60

40
50

20

0 0
348 348.5 349 349.5 350 344 344.5 345 345.5 346 346.5
Output Voltage (µV) D010
Output Voltage (µV) D011

Figure 34. Distribution at 25°C and Gain 1 V/V Figure 35. Distribution at 85°C and Gain 1 V/V

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180 180
Mean: 358.362 µV Mean: 11.44 µV
160 STD: 0.3084 µV 160 STD: 0.0358 µV

140 140
Number of Occurrences

Number of Occurrences
120 120

100 100

80 80

60 60

40 40

20 20

0 0
357 357.5 358 358.5 359 359.5 11 11.05 11.1 11.15 11.2 11.25 11.3
Output Voltage (µV) D012
Output Voltage (µV) D013

Figure 36. Distribution at –35°C and Gain 1 V/V Figure 37. Distribution at 25°C and Gain 32 V/V

140 200
Mean: 10.793 µV Mean: 11.546 µV
120 STD: 0.0632 µV STD: 0.0327 µV
Number of Occurrences

Number of Occurrences
150
100

80
100
60

40
50

20

0 0
10.6 10.65 10.7 10.75 10.8 10.85 10.9 10.95 11 11.4 11.45 11.5 11.55 11.6 11.65 11.7
Output Voltage (µV) D014
Output Voltage (µV) D015

Figure 38. Distribution at 85°C and Gain 32 V/V Figure 39. Distribution at –35°C and Gain 32 V/V

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Table 9 shows the effective bits, noise-free bits, and noise resulting from the standard deviation for
several temperature-gain combinations. For all measurements, a data rate of 20 SPS and SINC4 filter was
selected.

Table 9. DC Performance Low-Voltage Mode

TEMP (°C) GAIN (V/V) EFFECTIVE BITS NOISE-FREE BITS NOISE (µVRMS) NOISE (µVPP)
1 24.0 21.2 0.308 2.028
2 24.0 21.3 0.145 0.951
4 23.9 21.2 0.080 0.525
–35 8 23.7 21.0 0.047 0.308
16 23.1 20.4 0.035 0.226
32 22.3 19.6 0.031 0.200
Bypass 23.4 20.7 0.458 3.020
1 24.0 21.3 0.292 1.924
2 24.0 21.3 0.149 0.977
4 24.0 21.2 0.077 0.503
–20 8 23.6 20.9 0.049 0.322
16 23.1 20.3 0.036 0.237
32 22.2 19.5 0.033 0.214
Bypass 23.7 21.0 0.370 2.437
1 24.1 21.4 0.279 1.838
2 24.1 21.4 0.137 0.898
4 24.0 21.2 0.078 0.509
0 8 23.6 20.9 0.049 0.318
16 22.9 20.2 0.041 0.268
32 22.1 19.3 0.036 0.235
Bypass 23.8 21.1 0.339 2.236
1 24.1 21.4 0.277 1.828
2 24.1 21.4 0.140 0.923
4 23.9 21.2 0.078 0.515
25 8 23.6 20.9 0.050 0.326
16 23.0 20.3 0.038 0.249
32 22.1 19.4 0.035 0.231
Bypass 24.0 21.3 0.294 1.935
1 24.0 21.3 0.293 1.933
2 24.0 21.3 0.150 0.984
4 23.9 21.1 0.083 0.544
55 8 23.5 20.8 0.052 0.341
16 22.9 20.2 0.041 0.269
32 22.0 19.3 0.038 0.250
Bypass 24.0 21.3 0.292 1.927
1 23.9 21.2 0.312 2.059
2 24.0 21.2 0.155 1.018
4 23.6 20.9 0.096 0.633
85 8 23.1 20.4 0.070 0.460
16 22.3 19.6 0.060 0.396
32 21.4 18.6 0.058 0.383
Bypass 23.8 21.1 0.332 2.189

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The test setup is shown in Figure 40 and the measurements results are shown in Figure 41 to Figure 44.

DMM Climate chamber

HP CTS
3458A T-40/25

Isolation
SMU + 1 TIDA-00550 24-V DC PSU
Keysight 2 (One channel) Agilent
B2912A E3631A
3
- 4

3.3-V DC
SPI
UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 40. Test Setup for Low-Voltage Full Input Range

To get highest data rate using the FIR filter a data rate of 20 SPS was chosen. This way one can get a
fairly high (for example, temperature) update rate while proper 50- or 60-Hz rejection is performed. Thus,
this system can be used across continents without the need of main frequency adaption. On top of that,
the usage of the FIR filter provides a better bandwidth-to-data rate ratio compared to SINC filter. While the
best –3-dB bandwidth is 8.85 Hz (SINC1), the FIR reaches 13 Hz (which depends on the type of analog
input signal whether this is an advantage or disadvantage, of course). Last but not least, the FIR is the
single-cycle fully settled conversion. For SINC filters, the required number for fully settled samples is
dependent on the order (SINC1 = 1, SINC5 = 5, and so on).
The input error for the measurements at room temperature stays below 0.001% for a gain of 1 V/V and
does not change significantly for gains up to 32 V/V. The error towards higher temperature stays about the
same while it increases for temperatures colder ambient temperatures.

0.001% 0.1%
± ƒ&
25°C
85°C
0.0005% 0.05%
Error

Error

0 0

-0.0005% -0.05%

-0.001% -0.1%
-100% -50% 0 50% 100% -100% -50% 0 50% 100%
VIN Percent of FSR D016 VIN Percent of FSR D017

Figure 41. Input Error at 25°C Figure 42. Input Error at Border Temperatures

36 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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0.1% 0.01%
± ƒ& 1 V/V 16 V/V
± ƒ& 2 V/V 32 V/V
0°C 4 V/V Bypass
0.05% 25°C 0.005% 8 V/V
55°C
85°C
Error

Error
0 0

-0.05% -0.005%

-0.1% -0.01%
-100% -50% 0 50% 100% -100% -50% 0 50% 100%
VIN Percent of FSR D018
VIN Percent of FSR D019

Figure 43. Input Error 25°C, All Gain Figure 44. Input Error at Gain 32, All Temps

4.3 Mode III (Current-Mode) Measurements

The current measurement mode uses terminal input 2 and 3, the same as for low-voltage measurements,
but internally a different pair of AD1262 input pins. This enables the measurement of the voltage drop
across the burden resistor R25 only — leaving RDSON of K3 out of the equation. In this configuration the
accuracy and temperature stability is dominated by R25 (0.1%, 10 ppm).
The voltage drop over the resistor should be as small as possible; as a result, the resistor value should be
low. Benefits are the lower power dissipation (less self-heating) of the burden resistor and the
measurement of higher currents. On the other side, the burden resistor has to provide a certain voltage to
maintain precise measurements of smaller currents. It is a trade-off in terms of dynamic range and power
dissipation. The TIDA-00550 uses a 27.4-Ω resistor and accepts the current input ranges shown in
Table 10 with this value. The minimum voltage is the voltage required for a reliable current measurement.

Table 10. Full-Scale Current Input Ranges

PGA GAIN (V/V) FULL SCALE RANGE MINIMUM VOLTAGE
1 ±55.0 mA ±2.4 V
2 ±45.6 mA ±2.00 V
4 ±22.8 mA ±1.00 V
8 ±11.4 mA ±0.50 V
16 ±5.7 mA ±0.25 V
32 ±2.85 mA ±0.13 V

The entire input voltage range at PGA gain 1 V/V is not used. The reason is the max power dissipation of
R25 rated 0.1 W up to 70°C (0.08 W at 85°C). With a voltage drop of ±2.2 V (full input range), the power
dissipation would be 0.18 W. The maximum current of 55 mA is still state of the art. If one requires the full
input of 80 mA, a resistor with higher power dissipation rating is recommended. The test setup diagram
given in Figure 45 is the same for low-voltage noise measurement.

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Climate chamber
CTS
T-40/25

Isolation
1 TIDA-00550 24-V DC PSU
2 (One channel) Agilent
E3631A
3
4

3.3-V DC
SPI
UART MSP430FR5969
Host PC
LaunchPad

Figure 45. Test Setup for Current Noise Measurement

Figure 46 to Figure 51 show the histograms of the current input with gain of 1 V/V and 32 V/V at different
temperatures.

180 200
Mean: 343.902 µV Mean: 339.542 µV
160 STD: 0.5023 µV STD: 0.5537 µV

140
Number of Occurrences

Number of Occurrences

150
120

100
100
80

60
50
40

20

0 0
342 342.5 343 343.5 344 344.5 345 345.5 337.5 338 338.5 339 339.5 340 340.5 341 341.5
Output Voltage (µV) D020
Output Voltage (µV) D021

Figure 46. 20 SPS, Gain: 1 V/V, Temp: 25°C Figure 47. 20 SPS, Gain: 1 V/V, Temp: 85°C

38 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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160 300
Mean: 355.093 µV Mean: 6.008 µV
140 STD: 0.5068 µV STD: 0.0943 µV
250
Number of Occurrences

Number of Occurrences
120
200
100

80 150

60
100
40
50
20

0 0
353.5 354 354.5 355 355.5 356 356.5 357 5.7 5.8 5.9 6 6.1 6.2 6.3 6.4 6.5
Output Voltage (µV) D022
Output Voltage (µV) D023

Figure 48. 20 SPS, Gain: 1 V/V, Temp: –35°C Figure 49. 20 SPS, Gain: 32 V/V, Temp: 25°C

180 200
Mean: 4.950 µV Mean: 8.264 µV
160 STD: 0.0912 µV STD: 0.0604 µV

140
Number of Occurrences

Number of Occurrences
150
120

100
100
80

60
50
40

20

0 0
4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 8 8.1 8.2 8.3 8.4 8.5 8.6
Output Voltage (µV) D024
Output Voltage (µV) D025

Figure 50. 20 SPS, Gain: 32 V/V, Temp: 85°C Figure 51. 20 SPS, Gain: 32 V/V, Temp: –35°C

The noise measurement is shown in Table 11. Compared to the voltage input paths, the current input path
effective and noise-free bits are about 0.8 bits less. The main reason for this performance drop is the
layout, which is not optimal due to space constrains. While the signals traces from terminal pin 2 and 3 for
the voltage path are symmetrical, this is not the case for the current path.

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Table 11. DC Performance Current Mode

TEMP (°C) GAIN (V/V) EFFECTIVE BITS NOISE-FREE BITS NOISE (µVRMS) NOISE (µVPP)
1 23.2 20.5 0.507 3.344
2 23.2 20.5 0.262 1.728
4 23.1 20.4 0.139 0.914
–35 8 22.8 20.1 0.084 0.551
16 22.3 19.5 0.063 0.413
32 21.4 18.7 0.058 0.379
Bypass 22.8 20.1 0.687 4.530
1 23.2 20.5 0.512 3.379
2 23.2 20.5 0.258 1.699
4 23.1 20.4 0.141 0.927
–20 8 22.7 20.0 0.090 0.591
16 22.1 19.4 0.069 0.452
32 21.3 18.6 0.059 0.390
Bypass 23.1 20.3 0.572 3.772
1 23.3 20.6 0.485 3.196
2 23.2 20.5 0.260 1.711
4 23.1 20.3 0.144 0.949
0 8 22.7 20.0 0.091 0.598
16 22.1 19.4 0.070 0.459
32 21.2 18.5 0.064 0.422
Bypass 23.1 20.4 0.565 3.729
1 23.2 20.5 0.503 3.314
2 23.2 20.5 0.264 1.737
4 22.9 20.2 0.155 1.019
25 8 22.4 19.7 0.115 0.755
16 21.5 18.8 0.106 0.697
32 20.7 17.9 0.095 0.622
Bypass 23.2 20.5 0.506 3.337
1 23.2 20.5 0.517 3.409
2 23.2 20.4 0.265 1.747
4 23.0 20.3 0.147 0.969
55 8 22.7 19.9 0.095 0.623
16 22.0 19.3 0.074 0.488
32 21.1 18.4 0.069 0.454
Bypass 23.2 20.5 0.504 3.327
1 23.2 20.5 0.520 3.432
2 23.1 20.4 0.271 1.788
4 22.9 20.2 0.156 1.024
85 8 22.4 19.7 0.113 0.743
16 21.6 18.9 0.096 0.629
32 20.7 18.0 0.092 0.602
Bypass 23.2 20.5 0.524 3.453

40 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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The error over the analog input range is about 0.002% at room temperature. Like the voltage results, the
error is dependent on the temperature, not on the gain setting. The test setup is shown in , and the results
with different gains and ambient temperatures in Figure 53 to Figure 56.

DMM Climate chamber

HP CTS
3458A T-40/25

Isolation
SMU + 1 TIDA-00550 24-V DC PSU
Keysight 2 (One channel) Agilent
B2912A E3631A
3
- 4

3.3-V DC
SPI
UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 52. Test Setup for Current Input Range

0.004% 0.05%
± ƒ&
0.04% 25°C
0.03% 85°C
0.002%
0.02%
0.01%
Error

Error

0 0
-0.01%
-0.02%
-0.002%
-0.03%
-0.04%
-0.004% -0.05%
0 20% 40% 60% 80% 100% 0 20% 40% 60% 80% 100%
IIN Percent of FSR D026
IIN Percent of FSR D027

Figure 53. Input Error at 25°C Figure 54. Input Error Over Temperature

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0.004% 0.04%
± ƒ&
± ƒ&
0°C
0.002% 0.02% 25°C
55°C
85°C
Error

Error
0 0

-0.002% -0.02%
1 V/V 8 V/V
2 V/V 16 V/V
4 V/V 32 V/V
-0.004% -0.04%
0 20% 40% 60% 80% 100% 0 20% 40% 60% 80% 100%
IIN Percent of FSR D028
IIN Percent of FSR D029

Figure 55. Input Error at Various Gains Figure 56. Input Error Gain of 32 V/V and Various
Temperatures

4.4 Mode IV (4- to 20-mA Loop Mode) Measurements

The 4- to 20-mA loop mode is designed for connecting sensor transmitters with the 4- to 20-mA interface
to the TIDA-00550. It uses Mode III (current) with a fixed PGA gain setting of 4 V/V for best modulation of
the ADS1262 analog input range. As shown in Table 10, up to 22.8 mA can be measured with this gain
stage. The analog bandwidth of a 4- to 20-mA is specified to 25 Hz. The analog bandwidth of the FIR filter
at 20 SPS is 13 Hz. It depends on the application whether this bandwidth is enough or a SINC filter with
higher data rate should be used. Figure 57 shows the error at gain of 4 V/V and FIR filter.
0.04%
± ƒ&
± ƒ&
0°C
0.02% 25°C
55°C
85°C
Error

-0.02%

-0.04%
0 20% 40% 60% 80% 100%
IIN Percent of FSR D030

Figure 57. 4- to 20-mA Loop Error Over Temperature

The effective bits of 23 (noise-free bits of 20.3) are more than sufficient since common sensor transmitters
output not more than 16 bits.

Table 12. 4- to 20-mA System Noise

TEMP (°C) GAIN (V/V) EFFECTIVE BITS NOISE-FREE BITS NOISE (µVRMS) NOISE (µVPP)
–35 4 23.1 20.4 0.139 0.914
–15 4 23.1 20.4 0.141 0.927
0 4 23.1 20.3 0.144 0.949
25 4 22.9 20.2 0.155 1.019
55 4 23.0 20.3 0.147 0.969
85 4 22.9 20.2 0.156 1.024

42 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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4.5 Mode V (Thermocouple) Measurements

The thermocouple mode uses the low-voltage mode path. By nature, thermocouples provide a floating
voltage. To reference this voltage to the system, the ADS1262 built-in VBIAS feature is used, which
provides a reference input voltage for isolated sensors on pin AINCOM. The generated voltage is
VBIAS = (VAVDD + VAVSS) / 2 = 0 V (for a ±2.5-V analog supply). Here, this pin is connected to terminal pin 2,
which is the positive input of the thermocouple signal. The thermocouple voltage range is very small
relative to the ADC input range of ±2.2 V. For type K thermocouples, for instance, the expected voltage is
–6.5 to 54.9 mV for the full temperature range of –270°C to 1372°C. This fits well in PGA gain setting 32
V/V with an input voltage range of ±78 mV. Figure 58 shows the test setup.

DMM Climate chamber

HP CTS
3458A T-40/25

Isolation
SMU + 1 TIDA-00550 24-V DC PSU
Keysight 2 (One channel) Agilent
B2912A E3631A
3
- 4

3.3-V DC
SPI
UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 58. Test Setup for Thermocouple Measurement

The higher error at negative temperatures at the thermocouple (see Figure 59) results from a smaller
ΔV/ΔC in this region. For example, ΔV/ΔC from 100°C to 200°C is 4.042 mV/100°C while from –100°C to
–200°C is only 2.337 mV/100°C. As seen in the low voltage measurements (see Section 4.2), the error at
this small voltage range is symmetrical, thus resulting in the higher error of the TC at negative
temperatures.
0

-0.2

-0.4
Error (°C)

-0.6
± ƒ&
± ƒ&
0°C
-0.8 25°C
55°C
85°C
-1
-400 -200 0 200 400 600 800 1000 1200 1400
TC Temperature (°C) D031

Figure 59. TC Error (°C) at Various Ambient Temperatures

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4.6 Mode VI (RTD) Measurements

During the tests, the 3-wire connection method was measured because it is the most complex connection
using both current sources. Figure 60 shows the test setup.

DMM Climate chamber

HP CTS
3458A T-40/25

Isolation
1 TIDA-00550 24-V DC PSU
RTD resistors 2 Agilent
Time Electronics (One channel) E3631A
Type 1049 3
4

3.3-V DC
SPI
UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 60. Test Setup for 3-Wire RTD Measurement

A resistor network from Time electronics for RTD resistor emulation comes into play here. It provides 13
resistors to generate the temperature points between –200°C and 800°C. The accuracy of the resistors is
±0.65°C for higher temperatures. Since much better results are expected from the TIDA-00550, the exact
resistor values must be determined first. To get most precise results, the following steps were performed
for each temperature point:
1. Set the desired temperature point on the resistor network.
2. Measure the resistance with the 8.5-digit DMM using the 4-wire measurement method.
3. The resistance measured leads to an updated provided temperature point by the RTD network.
4. Connect the resistor network to the terminal inputs using the 3-wire connection and perform the actual
measurement. The updated temperature point was taken into account to obtain the error shown in
Figure 61.
This way, the resistance of the mechanical selector of the temperature point in the RTD emulator should
stay the same, but the contact resistance due to rewiring from the DMM to the TIDA-00550 may vary.
0.4

0.2
Error (°C)

-0.2

-0.4
-200 0 200 400 600 800
Temperature (°C) D032

Figure 61. RTD Error Measurement

The max temperature error measured is 0.065°C over the entire RTD temperature range. For proper
measurement, the ADS1262 analog supply voltage is set to –1.7-V/3.3-V mode.

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4.7 4- to 20-mA Loop Power Supply Measurements

The loop power supply provides the energy for the remote 4- to 20-mA transmitter at terminal pin 1. The
curve was created by connecting a standard resistor network from terminal 1 to ground (Figure 62).

DMM Climate chamber

HP CTS
3458A T-40/25

Isolation
Resistor 1 TIDA-00550 24-V DC PSU
ladder 2 (One channel) Agilent
E3631A
CMT 3
R1-3000 4

3.3-V DC
SPI
UART MSP430FR5969
GPIB
Host PC
LaunchPad

Figure 62. Test Setup for 4- to 20-mA Loop PSU

Since the resistor value is known and the voltage over the resistor is measured, the current can easily be
calculated using R = U × I. Figure 63 shows the output voltage based on the current drawn by the
transmitter.
30

25

20
Voltage (V)

15

10

0
0 5 10 15 20 25 30
Current (mA) D033

Figure 63. Dependency of Output Voltage on Drawn Current

The output voltage has a good stability in the target range of 4 to 20 mA while it decreases rapidly beyond
22 mA. The curve is strongly dependent on resistor R46 (20.5 Ω). Changing the value of resistor to a
smaller value will push the knee of the curve towards higher current values and vice versa.

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5 Design Files

5.1 Schematics
To download the schematics, see the design files at TIDA-00550.
DVDD
DVDD

C31 DVDD
DVDD 0.1µF C32
0.1µF
DVDD DVDD
R28 DGND R29
47k 47k DGND

8
U7A J9 J8

5
I2C_A0 1 V+ SN74LVC2G86DCTR U8 DGND1 2 DGND DGND 1 2 DGND
7 1 V+ SN74LVC1G332DCKR R30 3 4 3 4
CAPE_A0 2 3 4 SPI_CS1 0 +5V_JACK 5 6 5 6
V- SPI_a 6 +5V_JACK_USB 7 8 7 8
V- +5V R31 9 10 9 10
DNP

4
0 11 12 CAPE_A1 11 12 CAPE_A0

2
13 14 13 14
15 16 15 16
17 18 17 18
DGND DGND I2C_CLK 19 20 I2C_SDA 19 20
UART_TXD2 21 22 UART_RXD2 21 22
23 24 UART_TXD1 23 24
LMT01_OUT1 25 26 UART_RXD1 25 26
DVDD LMT01_OUT2 27 28 SPI_a 27 28
SPI_MISO 29 30 SPI_MOSI 29 30
SPI_CLK 31 32 31 32
33 34 33 34
35 36 35 36
DVDD DVDD C33 37 38 37 38
0.1µF 39 40 39 40
DVDD 41 42 SPI_b 41 42
R32 43 44 43 44
47k R33 DGND 45 46 45 46
8

U7B 47k

5
I2C_A1 5 V+ SN74LVC2G86DCTR U9 SSHQ-123-D-08-F-LF SSHQ-123-D-08-F-LF
3 1 V+ SN74LVC1G332DCKR
CAPE_A1 6 SPI_b 3 4 SPI_CS2 DGND DGND
V- 6
V-
4

2
LMT01_OUT[1..2]

REPEAT(CH,1,2)
DGND DGND TIDA_00550_TID_Channel.SchDoc

SPI_CLK
SPI_CLK
SPI_MOSI
SPI_MOSI
SPI_MISO
SPI_MISO
LMT01_OUT
REPEAT(LMT01_OUT)
SPI_CS[1..2] SPI_CS
REPEAT(SPI_CS)
UART_RXD[1..2] UART_RXD
REPEAT(UART_RXD)
UART_TXD[1..2] UART_TXD
REPEAT(UART_TXD)
VIN
VIN
DVDD +5V
+5V
DVDD
DGND

DGND

Text String
U_TIDA_00550_CoverSheet
J2 D20 TIDA_00550_CoverSheet.SchDoc
1 +24V
16...33V
2
L1 CD0603-B0230
1803277 U_TIDA_00550_TID_Hardware
TIDA_00550_TID_Hardware.SchDoc
DGND 10µH
DVDD DVDD TP2 U10

+5V 2
VIN SW
9

C34 R39 5 10
EN VO
0.1µF 47k D10
R34 R35 R36 R37 R38 R40 16.88V
4 CP1 OUT 8 VIN
47k 47k 47k 6.65k 6.65k C35 100k TP7
DGND 4.7µF Text
Text String
String C36 7 CD0603-B0230
FB
S1 U11 0.1µF
3

2
1 4 1 8 3 R41
A0 VCC CP2
2 3 1 Q1 1 261k D11
GND
416131160802 2 7 2N7002KW 6 11 150120VS75000
A1 WP SS EP
C39 Green

1
2

3 6 I2C_CLK 2.2µF
A2 SCL
TPS61093DSKR
4 5 I2C_SDA R42 R43 C37 C38 R44 R45
VSS SDA
47k 200k 1µF 0.1µF 8.06k 8.25k DVDD
I2C_A1 24LC256-I/ST
I2C_A0 TP8 TP3

DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
TP10

Figure 64. BeagleBone Cape Functionality (Main Top Level Sheet)

46 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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ADC
TIDA_00550_TID_ADS1262.SchDoc
SPI_CLK SPI_CLK LMT01_OUT LMT01_OUT
SPI_CS SPI_CS
SPI_MOSI SPI_MOSI
SPI_MISO SPI_MISO

AFE
TIDA_00550_TID_AFE.SchDoc
AIN0 AIN0
AIN1 AIN1
AIN2 AIN2 AVDD_iso
AIN3 AIN3 AVSS_iso
AIN4 AIN4 DVDD_iso
AIN6 AIN6 GND
AIN7 AIN7
AIN8 AIN8 SW_4_20MA
AIN9 AIN9 SW_ASUPPLY
SW_BURDEN
HART_IN DGND SW_HV
4-20mA LOOP DVDD SW_RTD_LOOP
SW_BURDEN
SW_HV AVSS_iso
SW_RTD_LOOP GND

HART PWR
TIDA_00550_TID_HART.SchDoc TIDA_00550_TID_Power.SchDoc
UART_RXD UART_RXD HART_IN
UART_TXD UART_TXD HART_OUT HART_OUT
+5V +5V +5V_iso VIN VIN
GND DGND DGND
DVDD DVDD +5V_iso AVDD_iso
AVSS_iso
4-20mA LOOP DVDD_iso
SW_4_20MA GND
SW_ASUPPLY
DGND

Figure 65. Per Channel Top Level Sheet

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DVDD_iso DVDD DVDD

if signal SW_TEMP low (-2.5/-1.7V) the LMT01 is disabled, otherwise enabled LMT01 signal shaper, Open-Drain output

DVDD
DVDD_iso DVDD_iso DVDD_iso DVDD_iso DVDD_iso DVDD_iso C1_ADC1 C2_ADC1 C3_ADC1
0.1µF 0.1µF 0.1µF
U1_ADC1

R1_ADC1 R2_ADC1 R3_ADC1 GND 16 1 DGND DGND

VCC2 VCC1
6.65k 261k C4_ADC1 47k
0.1µF SPI_ISO_CLK 14 3
OUTA INA SPI_CLK
SPI_ISO_MOSI 13 OUTB INB 4
SPI_MOSI
GND
SW_TEMP R4_ADC1 SPI_ISO_CS 12 5
OUTC INC SPI_CS
576k

8
U3_ADC1 U2_ADC1B SPI_ISO_MISO 11 6

5
50mV/198mV IND OUTD
U2_ADC1A 6 LM2903PW U4_ADC1
2 LM2903PW V+ 7 10 7 SN74LVC1G125DCKR
B EN2 EN1
R5_ADC1 V+ 1 2 1 5 V- 1
R6_ADC1 A VP VN
47k 3 V- 15 2
101mV GND2 GND1
340k 9 GND2 GND1 8 2 4
SPI_MISO

4
4
LMT01LPG R7_ADC1 R8_ADC1
R9_ADC1 1.65k 8.25k ISO7141CCDBQR DGND

3
47k 400mV

GND GND GND GND GND GND DGND DGND

LMT01_OUT

DVDD_iso AVDD_iso

AVDD_iso DVDD_iso
DVDD_iso AVDD_iso
TP1_ADC1

R10_ADC1
C5_ADC1 C6_ADC1C7_ADC1 C8_ADC1 C9_ADC1 47k
0.1µF 1µF 0.1µF 1µF 0.1µF

AVSS_iso AVSS_iso
GND GND GND
U5_ADC1 U6_ADC1

16
VCC QA
15 SW_TEMP 6
AVDD START
9 GND
20
R11_ADC1 RESET/PWDN
13
RCLR QB
1 19
DVDD SCLK
11 SPI_ISO_CLK
SW_4_20MA
47k DIN
12 SPI_ISO_MOSI
C10_ADC1 12 2 21 13 SPI_ISO_MISO
RCLK QC SW_ASUPPLY AIN0 AIN0 DOUT/DRDY
0.1µF 22 14
R12_ADC1 AIN1 AIN1 DRDY
10
SRCLR QD
3 23
AIN2 CS
10 SPI_ISO_CS
AIN2
AVSS_iso 1.65k 24
AIN3
AIN3
GPIO2 11
SRCLK QE
4 25
AIN4 XTAL1/CLKIN
15
SW_HV AIN4
GPIO2 26
AIN5 Y1_ADC1
AIN7 14
SER QF
5 27
AIN6 XTAL2
16 1 2
SW_RTD_LOOP AIN6
AIN7 28
AIN7
AIN7 ECS-73-18-10X
6 1 4
QG SW_BURDEN AIN8 AIN8 CAPP 7.3728MHz
2
AIN9
C11_ADC1
R13_ADC1 AIN9
QH
7 4700pF
475 3 5
AINCOM CAPN
9 AVSS_iso C12_ADC1 C13_ADC1
QH'
1

2
8 7 33pF 33pF
REFOUT AVSS
8 D1_ADC1 D2_ADC1
GND
Blue 150120RS75000 17 18 C14_ADC1
BYPASS DGND
Red 1µF
2

1
SN74AHC594PWR ADS1262IPWR

C15_ADC1
C16_ADC1
1µF 1µF
GND
AVSS_iso
AVSS_iso AVSS_iso AVSS_iso
AVSS_iso GND GND GND GND

AIN9 is normally connected to GND over 5kOhm -> can be used as temporary Data line
OE (594: RCLR) controlled over longer periods of high and low of GPIO0

Figure 66. ADC, LMT01, GPO, and Isolation Schematics

48 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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25V@20mA
U12_PWR2A
25V R46_PWR2
8 1
IN OUT 4-20mA LOOP

2
20.5

2
D12_PWR2 R47_PWR2 5 2 C40_PWR2
R48_PWR2
EN FB R49_PWR2
150120VS75000 C41_PWR2 47k 4.7µF 953k 1
Green 2.2µF EP GND
5.11k

1
U12_PWR2B Q2_PWR2

3
3 GND BC856A-7-F

3
NC
6 R50_PWR2 TPS7A4101DGNR
NC
7 8.25k 1 Q3_PWR2
NC
2N7002KW
TPS7A4101DGNR

2
R51_PWR2 R52_PWR2 R53_PWR2
47k 953k 47k

GND GND AVSS_iso GND GND C42_PWR2

270pF GND
HART_OUT

SW_4_20MA

4
D13_PWR2 DVDD_iso
BAS70JW-7-F
U13_PWR2
DVDD_iso
TLV70433DBVT
2 IN OUT 3

2
4 NC NC 5
C43_PWR2 D14_PWR2
0.1µF GND C44_PWR2 D15_PWR2
GND 150120VS75000
10µF MMSZ4685-V
3.6V Green

1
R54_PWR2

1
10V T1_PWR2 931
2 7
GND GND GND GND GND

AVDD_iso
4 8 30V
D16_PWR2 +5V_iso
9
AVDD_iso
3 4

2 5
10 5.6V U14_PWR2
12 1 6 C45_PWR2R55_PWR2
0.01µF 113k C46_PWR2 D17_PWR2
8 1
IN OUT MMSZ4685-V
10µF
BAS70JW-7-F 3.6V
5 2
-5.6V EN FB
11
120µH 6 3
NR/SS NC
R56_PWR2
R57_PWR2GND GND
7 4 100k 169k
DNC GND
C48_PWR2
C47_PWR2 9
PAD
GND 10µF 0.01µF
TPS7A4901DRBR Q4_PWR2

3
2N7002KW
1 SW_ASUPPLY
SW_ASUPPLY
R58_PWR2
GPIO Low: 2.5V (default)

2
47k GPIO High: 3.3V

GND GND GND GND GND AVSS_iso

AVSS_iso

AVSS_iso

U15_PWR2 C49_PWR2 C50_PWR2

7 R59_PWR2 U16_PWR2
L2_PWR2 Vin=15.37V f=264kHz BST
169k C51_PWR2R60_PWR2 R61_PWR2 MMSZ4682-V
R62_PWR2 hys=2V 0.01µF 3300pF 0.01µF 113k 47k D18_PWR2
C52_PWR2
2 8 8 1 2.7V

2
VIN VIN SW IN OUT
1.0 2.2µH D19_PWR2 10µF
VCC 6 5 EN FB 2 1
R64_PWR2 R63_PWR2
4 RON
100k 422k 5 CD0603-B0230 3 6 Q5_PWR2
FB NC NR/SS

3
2N7002KW GND GND
C54_PWR2
C53_PWR2 C55_PWR2 3 1 C56_PWR2 R65_PWR2 C57_PWR2 7 4
UVLO RTN DNC GND
2.2µF 0.1µF 2.2µF 9 0.1µF 54.9k 10µF C58_PWR2 9 R66_PWR2 SW_ASUPPLY
EP PAD
10µF C59_PWR2 73.2k
R67_PWR2 TPS7A3001DRBR 0.01µF GPIO Low: -2.5V (default)
8.66k LM5017SDX/NOPB GPIO High: -1.7V

C60_PWR2 R68_PWR2 C61_PWR2 R69_PWR2

1µF 7.68k 100k
DGND GND
1000pF

DGND DGND DGND DGND DGND DGND DGND DGND DGND GND GND GND GND GND

Figure 67. Power Schematics

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D3_AFE2 250uA
R15_AFE2 AIN1 IDAC0
1 2
SW_RTD_LOOP AVSS_iso
49.9
Blue

2
AVSS_iso R14_AFE2
K1_AFE2 AIN2 REFP
5.11k
CPC1017N
C17_AFE2

0.01%, 5ppm
8200pF

1.2475V
D4_AFE2 R16_AFE2 C18_AFE2
4 3 4.99k 0.1µF
4-20mA LOOP
5 2 GND C19_AFE2
8200pF
R17_AFE2

3
6 1
AIN3 REFN
5.11k
BAS70JW-7-F

J1_AFE2
1 R18_AFE2
AIN0 V
2 82.5k

3
3
4 K2_AFE2
C20_AFE2 D5_AFE2 CPC1017N R19_AFE2 C21_AFE2
0.01µF SM6T36CA 0.1%, 10ppm 17.8k 5600pF
1844236
36V

GND GND
GND GND D6_AFE2
R20_AFE2

2
1 2
SW_HV
49.9
Blue
AVSS_iso

R21_AFE2
AIN4 mV/TC/RTD/VBIAS
5.11k
C22_AFE2
C23_AFE2 D7_AFE2 8200pF
0.01µF SM6T36CA C24_AFE2
36V 0.1µF

GND C25_AFE2
8200pF
GND GND R22_AFE2
AIN6 mV/TC/RTD
5.11k
D8_AFE2 K3_AFE2
2 1 2 3
C26_AFE2
AVSS_iso
Blue HART_IN
0.1µF
C27_AFE2 D9_AFE2 R23_AFE2 1 4
0.01µF SM6T36CA SW_BURDEN
49.9
36V CPC1017N
R24_AFE2
AIN8 I
0.1%, 10ppm, 1/10W

5.11k
GND GND C28_AFE2
R25_AFE2 8200pF
27.4 C29_AFE2
0.1µF

GND C30_AFE2
8200pF
R26_AFE2
GND AIN9 I/IDAC1
TP4_AFE2
TP6_AFE2
TP5_AFE2 5.11k
R27_AFE2
AIN7 GND
5.11k
GND GND GND GND GND

Figure 68. AFE Schematics

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DVDD

DVDD
J3_HART2
1 2
UART_RXD
3 4
UART_TXD
5 6
7 8
9 10
11 12
+5V
DGND
TFM-106-02-S-D-A

DGND

J4_HART2
1 2
HART_IN
3 4
GND
5 6
7 8
+5V_iso
9 10
HART_OUT
11 12

TFM-106-02-S-D-A

GND GND

Figure 69. HART Connection Schematics

space
space
space
space
space
space
space
space
space
space
space
space

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5.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-00550.

Table 13. BOM

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
1 !PCB1 1 TIDA-00550 Any Printed Circuit Board
C1_ADC1, C1_ADC2, C2_ADC1,
C2_ADC2, C3_ADC1, C3_ADC2,
C4_ADC1, C4_ADC2, C5_ADC1,
C5_ADC2, C7_ADC1, C7_ADC2,
C9_ADC1, C9_ADC2, C10_ADC1,
CAP, CERM, 0.1 µF, 50 V,
2 C10_ADC2, C26_AFE1, 30 0.1uF C1005X7R1H104K TDK 0402
+/- 10%, X7R, 0402
C26_AFE2, C31, C32, C33, C34,
C36, C38, C43_PWR1,
C43_PWR2, C54_PWR1,
C54_PWR2, C56_PWR1,
C56_PWR2
C6_ADC1, C6_ADC2, C8_ADC1,
C8_ADC2, C14_ADC1,
CAP, CERM, 1 µF, 16 V, +/-
3 C14_ADC2, C15_ADC1, 11 1uF C1608X7R1C105K TDK 0603
10%, X7R, 0603
C15_ADC2, C16_ADC1,
C16_ADC2, C37
CAP, CERM, 4700 pF, 25 V,
4 C11_ADC1, C11_ADC2 2 4700pF C1608C0G1E472J TDK 0603
+/- 5%, C0G/NP0, 0603
C12_ADC1, C12_ADC2, CAP, CERM, 33 pF, 25 V,
5 4 33pF GRM1555C1E330JA01D MuRata 0402
C13_ADC1, C13_ADC2 +/- 5%, C0G/NP0, 0402
C17_AFE1, C17_AFE2,
C19_AFE1, C19_AFE2,
C22_AFE1, C22_AFE2, CAP, CERM, 8200 pF, 50 V,
6 12 8200pF GRM2195C1H822JA01D MuRata 0805
C25_AFE1, C25_AFE2, +/- 5%, C0G/NP0, 0805
C28_AFE1, C28_AFE2,
C30_AFE1, C30_AFE2
C18_AFE1, C18_AFE2,
CAP, CERM, 0.1 µF, 50 V,
7 C24_AFE1, C24_AFE2, 6 0.1uF C3216NP01H104J160AA TDK 1206_190
+/- 5%, C0G/NP0, 1206_190
C29_AFE1, C29_AFE2
C20_AFE1, C20_AFE2,
CAP, CERM, 0.01 µF, 100
8 C23_AFE1, C23_AFE2, 6 0.01uF 08051C103KAT2A AVX 0805
V, +/- 10%, X7R, 0805
C27_AFE1, C27_AFE2
CAP, CERM, 5600 pF, 50 V,
9 C21_AFE1, C21_AFE2 2 5600pF GRM2195C1H562JA01D MuRata 0805
+/- 5%, C0G/NP0, 0805
CAP, CERM, 4.7 µF, 50 V,
10 C35, C40_PWR1, C40_PWR2 3 4.7uF C3216X7R1H475M160AC TDK 1206_190
+/- 20%, X7R, 1206_190

52 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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Table 13. BOM (continued)

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
C39, C41_PWR1, C41_PWR2,
CAP, CERM, 2.2 µF, 50 V,
11 C53_PWR1, C53_PWR2, 7 2.2uF UMK316B7225KL-T Taiyo Yuden 1206
+/- 10%, X7R, 1206
C55_PWR1, C55_PWR2
CAP, CERM, 270 pF, 50 V,
12 C42_PWR1, C42_PWR2 2 270pF GRM155R71H271KA01D MuRata 0402
+/- 10%, X7R, 0402
C44_PWR1, C44_PWR2,
C46_PWR1, C46_PWR2,
CAP, CERM, 10 µF, 16 V,
13 C47_PWR1, C47_PWR2, 10 10uF C3216X7R1C106M TDK 1206
+/- 20%, X7R, 1206
C52_PWR1, C52_PWR2,
C58_PWR1, C58_PWR2
C45_PWR1, C45_PWR2,
C48_PWR1, C48_PWR2,
CAP, CERM, 0.01 µF, 25 V,
14 C49_PWR1, C49_PWR2, 10 0.01uF GRM155R71E103KA01D MuRata 0402
+/- 10%, X7R, 0402
C51_PWR1, C51_PWR2,
C59_PWR1, C59_PWR2
CAP, CERM, 3300 pF, 50 V,
15 C50_PWR1, C50_PWR2 2 3300pF GRM155R71H332KA01D MuRata 0402
+/- 10%, X7R, 0402
CAP, CERM, 10 µF, 25 V,
16 C57_PWR1, C57_PWR2 2 10uF GRM31CR71E106KA12L MuRata 1206
+/- 10%, X7R, 1206
CAP, CERM, 1 µF, 25 V, +/-
17 C60_PWR1, C60_PWR2 2 1uF GRM188R71E105KA12D MuRata 0603
10%, X7R, 0603
CAP, CERM, 1000 pF, 2000
18 C61_PWR1, C61_PWR2 2 1000pF 202R18W102KV4E Johanson Technology 1206_190
V, +/- 10%, X7R, 1206_190
D1_ADC1, D1_ADC2, D3_AFE1,
19 D3_AFE2, D6_AFE1, D6_AFE2, 8 Blue LB Q39G-L2N2-35-1 OSRAM LED, Blue, SMD BLUE 0603 LED
D8_AFE1, D8_AFE2
20 D2_ADC1, D2_ADC2 2 Red 150120RS75000 Wurth Elektronik LED, Red, SMD 3.2x1.6mm
D4_AFE1, D4_AFE2, D13_PWR1,
Diode, Schottky, 70 V, 0.07
21 D13_PWR2, D16_PWR1, 6 70V BAS70JW-7-F Diodes Inc. SOT-363
A, SOT-363
D16_PWR2
D5_AFE1, D5_AFE2, D7_AFE1, Diode, TVS, Bi, 36 V, 600
22 6 36V SM6T36CA STMicroelectronics SMB
D7_AFE2, D9_AFE1, D9_AFE2 W, SMB
D10, D19_PWR1, D19_PWR2, Diode, Schottky, 35 V, 0.2 A,
23 4 35V CD0603-B0230 Bourns 0603 Diode
D20 0603 Diode
D11, D12_PWR1, D12_PWR2,
24 5 Green 150120VS75000 Wurth Elektronik LED, Green, SMD 3.2x1.6mm
D14_PWR1, D14_PWR2
D15_PWR1, D15_PWR2, Diode, Zener, 3.6 V, 500
25 4 3.6V MMSZ4685-V Vishay-Semiconductor SOD-123
D17_PWR1, D17_PWR2 mW, SOD-123
Diode, Zener, 2.7 V, 500
26 D18_PWR1, D18_PWR2 2 2.7V MMSZ4682-V Vishay-Semiconductor SOD-123
mW, SOD-123

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Table 13. BOM (continued)

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
Terminal Block Plug, 3.5mm,
27 H1, H3 2 1840382 Phoenix Contact
4x1, Green
Fiber optics - MC 1,5/10-
28 H2 1 1841161 Phoenix Contact LWL 1,5-3,5 for Phoenix
connectors
Terminal Block Plug,
29 H4 1 1803578 Phoenix Contact
3.81mm, 2x1, Green
Terminal Block, 4x1, 3.5mm, Terminal Block, 4x1,
30 J1_AFE1, J1_AFE2 2 1844236 Phoenix Contact
Green, R/A, TH 3.5mm, R/A, TH
Terminal Block, 2x1, Connector, 2 pos.
31 J2 1 1803277 Phoenix Contact
3.81mm, R/A, TH 3.8mm RA
J3_HART1, J3_HART2, Header(Shrouded), 1.27mm, Header(Shrouded),
32 4 TFM-106-02-S-D-A Samtec
J4_HART1, J4_HART2 6x2, Tin, SMT 1.27mm, 6x2, SMT
Female Connector, 2.54mm, Female Connector,
33 J8, J9 2 SSHQ-123-D-08-F-LF Major League Electronics
23x2, TH 2.54mm, 23x2, TH
K1_AFE1, K1_AFE2, K2_AFE1, Relay, SPST-NO (1 Form
34 6 CPC1017N IXYS 4.089x3.81mm
K2_AFE2, K3_AFE1, K3_AFE2 A), 0.1 A, 1.2 VDC, SMD
Inductor, Wirewound,
35 L1 1 10uH 74404042100 Wurth Elektronik Ferrite, 10 µH, 1.2 A, 0.15 4x4mm
ohm, SMD
Inductor, Ferrite, 2.2 µH,
36 L2_PWR1, L2_PWR2 2 2.2uH LQM18PN2R2MFH MuRata 0603
0.35 A, 0.38 ohm, SMD
Q1, Q3_PWR1, Q3_PWR2,
MOSFET, N-CH, 60 V, 0.31
37 Q4_PWR1, Q4_PWR2, 7 60V 2N7002KW Fairchild Semiconductor SOT-323
A, SOT-323
Q5_PWR1, Q5_PWR2
Transistor, PNP, 65 V, 0.01
38 Q2_PWR1, Q2_PWR2 2 65 V BC856A-7-F Diodes Inc. SOT-23
A, SOT-23
RES, 6.65 k, 1%, 0.063 W,
39 R1_ADC1, R1_ADC2, R37, R38 4 6.65k CRCW04026K65FKED Vishay-Dale 0402
0402
RES, 261 k, 1%, 0.063 W,
40 R2_ADC1, R2_ADC2, R41 3 261k CRCW0402261KFKED Vishay-Dale 0402
0402
R3_ADC1, R3_ADC2, R5_ADC1,
R5_ADC2, R9_ADC1, R9_ADC2,
R10_ADC1, R10_ADC2,
R11_ADC1, R11_ADC2, R28,
R29, R32, R33, R34, R35, R36,
RES, 47 k, 5%, 0.063 W,
41 R39, R42, R47_PWR1, 29 47k CRCW040247K0JNED Vishay-Dale 0402
0402
R47_PWR2, R51_PWR1,
R51_PWR2, R53_PWR1,
R53_PWR2, R58_PWR1,
R58_PWR2, R61_PWR1,
R61_PWR2

54 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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Table 13. BOM (continued)

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
RES, 576 k, 1%, 0.063 W,
42 R4_ADC1, R4_ADC2 2 576k CRCW0402576KFKED Vishay-Dale 0402
0402
RES, 340 k, 1%, 0.063 W,
43 R6_ADC1, R6_ADC2 2 340k CRCW0402340KFKED Vishay-Dale 0402
0402
R7_ADC1, R7_ADC2, R12_ADC1, RES, 1.65 k, 1%, 0.063 W,
44 4 1.65k CRCW04021K65FKED Vishay-Dale 0402
R12_ADC2 0402
R8_ADC1, R8_ADC2, R45, RES, 8.25 k, 1%, 0.063 W,
45 5 8.25k CRCW04028K25FKED Vishay-Dale 0402
R50_PWR1, R50_PWR2 0402
RES, 475, 1%, 0.063 W,
46 R13_ADC1, R13_ADC2 2 475 CRCW0402475RFKED Vishay-Dale 0402
0402
R14_AFE1, R14_AFE2,
R17_AFE1, R17_AFE2,
R21_AFE1, R21_AFE2,
R22_AFE1, R22_AFE2, RES, 5.11 k, 1%, 0.063 W,
47 16 5.11k CRCW04025K11FKED Vishay-Dale 0402
R24_AFE1, R24_AFE2, 0402
R26_AFE1, R26_AFE2,
R27_AFE1, R27_AFE2,
R49_PWR1, R49_PWR2
R15_AFE1, R15_AFE2,
RES, 49.9, 1%, 0.063 W,
48 R20_AFE1, R20_AFE2, 6 49.9 CRCW040249R9FKED Vishay-Dale 0402
0402
R23_AFE1, R23_AFE2
RES, 4.99 k, 0.01%, 0.1 W,
49 R16_AFE1, R16_AFE2 2 4.99k RNCF0603TKY4K99 Stackpole Electronics Inc 0603
0603
RES, 82.5 k, 0.1%, 0.1 W,
50 R18_AFE1, R18_AFE2 2 82.5k RN73C2A82K5BTDF TE Connectivity 0805
0805
RES, 17.8 k, 0.1%, 0.1 W,
51 R19_AFE1, R19_AFE2 2 17.8k RN73C2A17K8BTDF TE Connectivity 0805
0805
RES, 27.4, 0.1%, 0.1 W,
52 R25_AFE1, R25_AFE2 2 27.4 RN73C2A27R4BTDF TE Connectivity 0805
0805
53 R30 1 0 ERJ-3GEY0R00V Panasonic RES, 0, 5%, 0.1 W, 0603 0603
R40, R56_PWR1, R56_PWR2,
RES, 100 k, 1%, 0.063 W,
54 R64_PWR1, R64_PWR2, 7 100k CRCW0402100KFKED Vishay-Dale 0402
0402
R69_PWR1, R69_PWR2
RES, 200 k, 1%, 0.063 W,
55 R43 1 200k CRCW0402200KFKED Vishay-Dale 0402
0402
RES, 8.06 k, 1%, 0.063 W,
56 R44 1 8.06k CRCW04028K06FKED Vishay-Dale 0402
0402
RES, 20.5, 1%, 0.25 W,
57 R46_PWR1, R46_PWR2 2 20.5 CRCW120620R5FKEA Vishay-Dale 1206
1206
R48_PWR1, R48_PWR2, RES, 953 k, 1%, 0.063 W,
58 4 953k CRCW0402953KFKED Vishay-Dale 0402
R52_PWR1, R52_PWR2 0402

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Table 13. BOM (continued)

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
RES, 931, 1%, 0.063 W,
59 R54_PWR1, R54_PWR2 2 931 CRCW0402931RFKED Vishay-Dale 0402
0402
R55_PWR1, R55_PWR2, RES, 113 k, 1%, 0.063 W,
60 4 113k CRCW0402113KFKED Vishay-Dale 0402
R60_PWR1, R60_PWR2 0402
R57_PWR1, R57_PWR2, RES, 169 k, 1%, 0.063 W,
61 4 169k CRCW0402169KFKED Vishay-Dale 0402
R59_PWR1, R59_PWR2 0402
RES, 1.0, 5%, 0.063 W,
62 R62_PWR1, R62_PWR2 2 1.0 CRCW04021R00JNED Vishay-Dale 0402
0402
RES, 422 k, 1%, 0.063 W,
63 R63_PWR1, R63_PWR2 2 422k CRCW0402422KFKED Vishay-Dale 0402
0402
RES, 54.9 k, 1%, 0.063 W,
64 R65_PWR1, R65_PWR2 2 54.9k CRCW040254K9FKED Vishay-Dale 0402
0402
RES, 73.2 k, 1%, 0.063 W,
65 R66_PWR1, R66_PWR2 2 73.2k CRCW040273K2FKED Vishay-Dale 0402
0402
RES, 8.66 k, 1%, 0.063 W,
66 R67_PWR1, R67_PWR2 2 8.66k CRCW04028K66FKED Vishay-Dale 0402
0402
RES, 7.68 k, 1%, 0.063 W,
67 R68_PWR1, R68_PWR2 2 7.68k CRCW04027K68FKED Vishay-Dale 0402
0402
Switch, SPST, Off-On, 2
68 S1 1 416131160802 Wurth Elektronik 5.6x3.58mm
Pos, SMD
69 T1_PWR1, T1_PWR2 2 120uH 750315856 Wurth Elektronik Transformer, 120 uH, SMT 12.85x12.95mm
4242-VPK Small-Footprint
and Low-Power Quad
70 U1_ADC1, U1_ADC2 2 ISO7141CCDBQR Texas Instruments DBQ0016A
Channels Digital Isolators,
DBQ0016A
71 U2_ADC1, U2_ADC2 2 LM2903PW Texas Instruments Dual Comparator, PW0008A PW0008A
0.5°C Accurate 2-Pin Digital
72 U3_ADC1, U3_ADC2 2 LMT01LPG Texas Instruments NTC or PTC Thermistor LPG0002A
Replacement, LPG0002A
Single Bus Buffer Gate With
73 U4_ADC1, U4_ADC2 2 SN74LVC1G125DCKR Texas Instruments DCK0005A
3-State Output, DCK0005A
8-Bit Shift Register With
74 U5_ADC1, U5_ADC2 2 SN74AHC594PWR Texas Instruments PW0016A
Output Registers, PW0016A
32-Bit, Precision, 38-kSPS,
Analog-to-Digital Converter
(ADC) with Programmable
75 U6_ADC1, U6_ADC2 2 ADS1262IPWR Texas Instruments PW0028A
Gain Amplifier (PGA) and
Voltage Reference,
PW0028A

56 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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www.ti.com Design Files

Table 13. BOM (continued)

PACKAGE
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION
REFERENCE
Dual 2-Input Exclusive-OR
76 U7 1 SN74LVC2G86DCTR Texas Instruments DCT0008A
Gate, DCT0008A
Single 3-Input Positive-OR
77 U8, U9 2 SN74LVC1G332DCKR Texas Instruments DCK0006A
Gate, DCK0006A
LOW INPUT BOOST
CONVERTER WITH
INTEGRATED POWER
78 U10 1 TPS61093DSKR Texas Instruments DSK0010A
DIODE AND
INPUT/OUTPUT
ISOLATION, DSK0010A
256K I2C CMOS Serial
79 U11 1 24LC256-I/ST Microchip TSSOP-8
EEPROM, TSSOP-8
Single Output LDO, 50 mA,
Adjustable 1.175 to 48 V
Output, 7 to 50 V Input, 8-
80 U12_PWR1, U12_PWR2 2 TPS7A4101DGNR Texas Instruments DGN0008B
pin MSOP (DGN), -40 to 125
degC, Green (RoHS & no
Sb/Br)
Single Output LDO, 150 mA,
Fixed 3.3 V Output, 2.5 to 24
V Input, with Ultra-Low IQ,
81 U13_PWR1, U13_PWR2 2 TLV70433DBVT Texas Instruments DBV0005A
5-pin SOT-23 (DBV), -40 to
125 degC, Green (RoHS &
no Sb/Br)
+36V, +150mA, Ultralow-
82 U14_PWR1, U14_PWR2 2 TPS7A4901DRBR Texas Instruments Noise, Positive LINEAR DRB0008A
REGULATOR, DRB0008A
100V, 600mA Constant On-
83 U15_PWR1, U15_PWR2 2 LM5017SDX/NOPB Texas Instruments Time Synchronous Buck NGU0008B
Regulator, NGU0008B
-35-V, -200-mA, Ultralow-
84 U16_PWR1, U16_PWR2 2 TPS7A3001DRBR Texas Instruments Noise, Negative Linear DRB0008A
Regulator, DRB0008A
Crystal, 7.3728MHz, 18pF,
85 Y1_ADC1, Y1_ADC2 2 ECS-73-18-10X ECS Inc. D3.2xL10.5mm
SMD
Fiducial mark. There is
86 FID1, FID2, FID3 0 N/A N/A Fiducial
nothing to buy or mount.
87 R31 0 0 ERJ-3GEY0R00V Panasonic RES, 0, 5%, 0.1 W, 0603 0603

TIDUBI1 – March 2016 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC 57
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Design Files www.ti.com

5.3 Layout Prints

To download the layout prints, see the design files at TIDA-00550.

5.4 Altium Project

To download the Altium project files, see the design files at TIDA-00550.

5.5 Gerber Files

To download the Gerber files, see the design files at TIDA-00550.

5.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-00550.

6 Software Files
To download the software files, see the design files at TIDA-00550.

7 References
1. IXYS Integrated Circuits Division, 60V Normally-Open Single-Pole 4-Pin SOP OptoMOS® Relay,
CPC1017N Datasheet (PDF)
2. Texas Instruments, LaunchPad Product Folder (http://www.ti.com/tool/msp-exp430fr5969)

8 About the Authors

LARS LOTZENBURGER is a Systems Engineer at Texas Instruments where he is responsible for
developing reference design solutions for the industrial segment. Lars brings to this role his extensive
experience in analog and digital circuit development, PCB design, and embedded programming. Lars
earned his diploma in electrical engineering from the University of Applied Science in Mittweida, Saxony,
Germany.
INGOLF FRANK is a Systems Engineer in the Texas Instruments Factory Automation and Control team,
focusing on programmable logic controller I/O modules. Ingolf works across multiple product families and
technologies to leverage the best solutions possible for system level application design. Ingolf earned his
electrical engineering degree (Dipl. Ing. (FH)) in the field of information technology at the University of
Applied Sciences Bielefeld, Germany in 1991.

58 Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC TIDUBI1 – March 2016
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