MICROPROCESSOR EXIT EXAM REVIEWER

1. Based from order, when the instruction PUSHA is applied, which of the following register is
"PUSHED" last?
A. CX
B. AX
C. SI
D. DI ANG CAT DI BA SOBRANG BAHO SIPA DALI

2. The direction flag is set to 0 using this instruction.

A. CLC - clear carry
B. CMC – complement carry
C. CLD – clear direction flag
D. STC – set carry

3. SHLD AX, BX, 4 AX = 1234h BX = 5678h

1 2 3 4 5 6 7 8

Lost
Answer : 2345h

4. SHRD BX, CX, 8 (What’s the result) – Go to Number 11

5. It is an instruction used to preserve the contents of the outer loop counter.
A. LOOP
B. PUSH
C. PUSH and POP MICROPROCESSOR PAGE 126
D. POP
6. It is considered as a system signal used in troubleshooting techniques for 8088 hardware
architecture.
A. DEN
B. INTR
C. HLDA MICROPROCESSOR PAGE 305
D. ALE

System signals – CLK, RESET, READY, HOLD, HLDA, and MN/MX

Signals involved with memory and I/O access – ALE, RD, WR, DEN, DT/R,
IO/M
Signals involved with interrupts - NMI, INTR, INTA
 7. The lower byte of the flag register contains 83h. Which flag registers are cleared as a result of
executing LAHF instruction?
A. PF PARITY, ZERO, AUXILLIARY ARE CLEARED MICRO BOOK PAGE 87
B. SF
C. none of the choices
D. CF

8 3
1 0 0 0 0 0 1 1
S Z - A - P - C

8. It is the standard bus connector agreed upon by the PC business comprising of 62 pins found in
early PC motherboards that allow expansion with the 8088 microprocessor.
A. SATA connector
B. ISA connector MICRO PROCESSOR BOOK PAGE 304
C. RS232C connector
D. SCSI connector

9. Which of the following is a logical instruction?

A. TEST -MICROPROCESSOR BOOK PAGE 113.
B. ADC
C. SHL
D. CMP

Logical Instructions – NOT, AND, OR, XOR, TEST, BSF/BSR, BT/BTC/BTS/BTR, SETcc, SETNZ

10. The lower byte of the flag register contains 83h. Which flag registers are set as a result of
executing LAHF instruction?
A. PF
B. ZF
C. AF
D. SF SIGN, AND CARRY FLAGS ARE SET MICRO BOOK PAGE 87

8 3
1 0 0 0 0 0 1 1
S Z - A - P - C
11. Registers AX, BX and CX contain the following values respectively: 1234h, 5678h and 9ABCh.

What is the result of the instruction SHRD BX, CX, 8?

A. 9A78h
B. 9A56h
C. 2345h
D. BC56h MICROPROCESSOR BOOK PAGE 118

12. Which of the following is a bit manipulation instruction?

A. any of the choices -MICROPROCESSOR BOOK PAGE 32
B. NOT AL
C. SHL DL, 2
D. ROL AX, 1

Bit manipulation instruction – AND, NOT, OR, RCL, RCR, ROL, ROR, SAL, SAR, SHL, SHR, TEST, XOR
Program transfer instructions – JMP, LOOP, LOOPE/LOOPZ, LOOPNE/LOOPNZ, JCXZ/JECXZ
Subroutine and interrupt intructions – CALL, RET, BOUND, ENTER/LEAVE,
Process Control instructions – CLC, STC, CMC, CLD, STD, CLI, STI, HLT, NOP, LOCK

13. The following is true for r/m except for

A. r/m are used for addressing modes
B. r/m refers to registers enclosed in brackets
C. when mod = 11, r/m indicates a register field
D. r/m specifies the addressing mode
14. ARM stands for
A. Advance RISC Machines
B. Advance Response Machines
C. Advance RISC Model
D. Advance Reprogrammable Model

RISC – reduced instruction set computer

CISC – complex instruction set computer

15. The 8088's I/O addressing space contains how many possible input/output ports?
A. 1048576
B. 4096
C. 1024
D. 65536- MICROPROCESSOR BOOK PAGE 296

16. The lower byte of the flag register contains 83h. What is the result of an LAHF instruction?
A. AH = 83h
B. AX = 83h
C. AL = 83h
D. all the flags are set to 83h
 17. Using the signed-2’s complement format, the representation of -7 is __________.
A. 1111 00111 = 7
B. 1001 11000 = 1ST COMPLEMENT
C. 1100 + 1
D. 1000 11001
128 64 32 16 8 4 2 1 To check:
0 0 0 0 0 1 1 1 =7 (-) negative 8 4 2 1
st
1 1 1 1 1 0 0 0 = 1 complement 1 1 1 1 0 0 1 = -7
+ 1 Add 1
1 1 1 1 1 0 0 1 answer - 8 +1 = -7

18. A 2 bit by 2 bit multiplier is simply implemented using which of the following combinational
circuit?
A. 2 Half Adders and 4 AND gates 2X2 = 4 AND
B. 2 Full Adders and an OR gate 2-1 = 1 ADDER = ½ ADDER + ½ ADDER
C. 2 Full Adders and 4 AND gates
D. One 4 bit binary adder, 2 AND gates and 1 OR gate

19. How many basic theorems and postulates are used to prove the expression x + xy = x
A. 6
B. 4 X(1+Y)=X 1
C. 5 1+Y=1 2
D. 3 X∙1 = X 3

Solution:

x y xy x+xy

0 0 0 0

0 1 0 0

1 0 0 1

1 1 1 1
20. If a 2 to 4 line decoder is made of NAND gates, which input would produce an output of 1011
from D0 to D3?
A. 010
B. 011
C. 001
D. 1xx

21. A parity bit is used in error detecting codes, if an ASCII of A is used with odd parity the result is
A. 1100 0001
B. 0101 0100
C. 0100 0001
D. 1101 0100
22. A 3 x 8 decoder contains output from D0 to D7. Which output is activated high if the input
expression x'yz'?
A. D1
B. D2
C. D4
D. D5

23. A 4-input (D0 - D3) priority encoder circuit contain 3 output functions (x, y) pertaining to binary
values. What is the function for the least significant bit y?
A. D2 + D3
B. D1 + D2 + D3
C. D3 + D1 D2'
D. D2 + D1' D3
24. The 74LS83 is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder, you
must
A. use four adders with no interconnections
B. use two adders and connect the sum outputs of one to the bit inputs of the other
C. use eight adders with no interconnections.
D. use two adders with the carry output of one connected to the carry input of the other

25. Reduce the Boolean expression W’X(Z’ + Y’Z) + X(W + W’YZ) to 1 literal
A. X
B. W
C. Z
D. Y

Solution:

W’X(Z’ + Y’Z) + X(W + W’YZ)

XW'Z' + XW'Y'Z + XW + XW'YZ

XW'Z' + XW'Z(Y'+Y) + XW

XW'Z' + XW'Z + XW

XW'(Z'+Z) + XW

XW' + XW

x(W' + W)

X
26. Refer to the behavior of synchronous sequential circuit below. Assume that the states are
identified as the combination ABC. What is the complement of the next state for an input of 1, if
the current state is 001?
A. 010
B. 011
C. 101
D. 110

A B C
A B C X D Q T Q J K Q Q’ Y
0 0 0 0 1 1 1 1 0 1 0 1 1
0 0 0 1 0 0 1 1 0 1 0 1 0
0 0 1 0 0 0 1 1 0 0 1 0 0
0 0 1 1 0 0 1 1 0 1 0 1 0
0 1 0 0 1 1 1 0 0 1 0 1 1
0 1 0 1 0 0 1 0 1 1 1 0 1
0 1 1 0 0 0 0 1 0 0 1 0 1
0 1 1 1 0 0 1 0 1 1 0 1 0
1 0 0 0 1 1 1 1 0 1 0 1 1
1 0 0 1 0 0 1 1 0 1 0 1 0
1 0 1 0 0 0 0 0 1 0 1 0 1
1 0 1 1 0 0 1 1 0 1 0 1 0
1 1 0 0 1 1 1 0 0 1 0 1 1
1 1 0 1 0 0 1 0 1 1 1 0 1
1 1 1 0 0 0 0 1 0 0 1 0 1
1 1 1 1 0 0 1 0 1 1 0 1 0
27. A parity bit is used in error detecting codes, if an ASCII of A is used with even parity the result is
A. 1100 0001
B. 1101 0100
C. 0100 0001
D. 0101 0100

28. A product term where in which all the variables appear once, rather complemented or
uncomplemented is called __________
A. maxterm
B. POS pos maxterm 0
C. SOP sop minterm 1
D. minterm

29. Perform the binary division 1111 0011 ÷ 1001 to obtain the quotient.
A. 10101
B. 10111
C. 11011
D. 11101
30. Digital integrated circuits are classified not only by their complexity or logical operation, but also
by the specific circuit technology to which they belong. The circuit technology is referred to as
____
A. none of the choices
B. CMOS family
C. TTL family
D. digital logic family

31. A parity bit is used in error detecting codes, if an ASCII of T is used with odd parity the result is
A. 0100 0001
B. 0101 0100
C. 1101 0100
D. 1100 0001

32. A decimal parallel adder that adds 5 decimal digits requires how many BCD adder stages.
A. 5
B. 6
C. 3
D. 4
33. Idempotent law

34. How many passes (bubble sort)

 35. What law?
P U -P = U Complement Law

36. Format ( pagkakasunod sunod) (

1 Not
2 And
3 OR
4 Conditional
5 Bi-conditional
37. Premises and Conclusion

38. Premises and Conclusion

39. Shortest path

 40. f = 4MHz, t = 250ns

41. What kind of graph? – eulerian cycle

EDGE PATH ONCE EDGE DIFFERENT VERTEX

2 ODD
E P IE DV
EDGE CIRCUIT ONCE EDGE SAME VERTEX
ALL EVEN
E C IE SV
HAMILTONIAN PATH ONCE VERTEX DIFFERENT VERTEX
H P IV DV
HAMILTONIAN CIRCUIT ONCE VERTEX SAME VERTEX
H C IV SV

42. What kind of graph? EULERIAN PATH - 2 ODD VERTICES

EDGE PATH ONCE EDGE DIFFERENT VERTEX

2 ODD
E P IE DV
EDGE CIRCUIT ONCE EDGE SAME VERTEX
ALL EVEN
E C IE SV
HAMILTONIAN PATH ONCE VERTEX DIFFERENT VERTEX
H P IV DV
HAMILTONIAN CIRCUIT ONCE VERTEX SAME VERTEX
H C IV SV

43. Pendant yung f -1 degree

 44.

45.

128 64 32 16 8 4 2 1

0 0 0 0 1 1 0 0 = 12 To check:
1 1 1 1 0 0 1 1 = 1st complement (-) negative 16 8 4 2 1

+ 1 Add 1 1 1 1 0 1 0 0 = -12
1 1 1 1 0 1 0 0 answer
- 16 +4 = -12

46. 1st Complement subtraction

47. POPA – DI una

48. 00- HIGHEST Privilege level

49. 8 4 -2 -1

8 4 -2 -1 DECIMAL EQUIVALENT
X X X X 0
0 1 1 1 1
0 1 1 0 2
0 1 0 1 3
0 1 0 0 4
1 0 1 1 5
1 0 1 0 6
1 0 0 1 7
1 0 0 0 8
1 1 1 1 9
1 1 1 0 10
1 1 0 1 11
1 1 0 0 12

50. Polynomial – BUBBLE SORT

Tapos anong big O algorithm bubble sort, anong complexity, exponential, lograthmic, linear , or

51. FACTORIAL – HAMILTONIAN

Meron din para sa hamiltonian cycle, if logarithmic, exponential, linear, polynomial

52.

53. 8x8
54. Rol instructions

55.

ANSWER :

56.
57. SETNZ AL
If the zero flag indicates an NZ condition (zero flag is clear), register AL is set to 01H.
Otherwise, AL is set to 00H.

58.

59. LAHF machine code – 9F

60. Levels of integration, number of gates

61. Aralin nyo yung K-map. Madami din un