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    E3-231 Digital Systems Design With Fpgas: Kuruvilla Varghese Dese Dese Indian Institute of Science

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    This document outlines the details of the E3-231 Digital Systems Design with FPGAs course, including: - Course timings, prerequisites, contents, objectives, evaluation, and schedule - The course aims to teach digital system design from specifications to implementation using FPGAs and VHDL - Students will learn advanced digital design, VHDL, and how to design systems meeting timing constraints using FPGAs

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    E3-231 Digital Systems Design With Fpgas: Kuruvilla Varghese Dese Dese Indian Institute of Science

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    abhinav_ruhela
    137 views12 pages
    This document outlines the details of the E3-231 Digital Systems Design with FPGAs course, including: - Course timings, prerequisites, contents, objectives, evaluation, and schedule - The course aims to teach digital system design from specifications to implementation using FPGAs and VHDL - Students will learn advanced digital design, VHDL, and how to design systems meeting timing constraints using FPGAs

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    FPGA Intro

    Original Title

    Kv Dsf Intro

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    This document outlines the details of the E3-231 Digital Systems Design with FPGAs course, including: - Course timings, prerequisites, contents, objectives, evaluation, and schedule - The course aims to teach digital system design from specifications to implementation using FPGAs and VHDL - Students will learn advanced digital design, VHDL, and how to design systems meeting timing constraints using FPGAs

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    137 views12 pages

    E3-231 Digital Systems Design With Fpgas: Kuruvilla Varghese Dese Dese Indian Institute of Science

    Uploaded by

    abhinav_ruhela
    This document outlines the details of the E3-231 Digital Systems Design with FPGAs course, including: - Course timings, prerequisites, contents, objectives, evaluation, and schedule - The course aims to teach digital system design from specifications to implementation using FPGAs and VHDL - Students will learn advanced digital design, VHDL, and how to design systems meeting timing constraints using FPGAs

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 12

    1

    E3-231 Digital Systems Design with


    FPGAs

    Kuruvilla Varghese
    DESE
    Indian Institute of Science

    Kuruvilla Varghese

    Course Timings 2

    • Lectures
    – Tuesdays, Thursdays10.00 to 11.00 AM
    – DESE Auditorium
    • Laboratory
    – Mondays, Wednesdays 2.00 to 5.30 PM
    – Communications Networks Lab,
    Microelectronics Lab
    • Attendance (Lectures, Lab)
    – 75% Attendance is a must, failing which IISc
    may cancel your registration
    Kuruvilla Varghese

    1
    Your Idea or Expectation 3

    • What is your idea of this course?


    • Whyy are you
    y creditingg this course?
    • What do you think should be taught?
    • What have you heard (if at all) about the
    course?

    Kuruvilla Varghese

    Course Objective 4

    • Digital Systems Design


    – Specifications to Implementation
    – Algorithm to Architecture (Front end design)
    – Partitioning, Design of blocks, Timing Analysis
    – Device Technology: FPGA
    – Design entry: VHDL
    – N t about
    Not b t VHDL,
    VHDL NotN t about
    b t FPGA
    – Case studies (Communications, Embedded
    Systems, Computer Architecture)

    Kuruvilla Varghese

    2
    Pre-requisite 5

    • Digital Systems
    – Boolean Algebra, Minimization
    – Combinational Logic
    – Flip-flops, Counters
    – Timing
    – CMOS circuits
    • B
    Basics
    i off Micro-processors
    Mi
    • Basics of Computer Architecture
    • Basics of Communication Networks
    Kuruvilla Varghese

    Course Contents 6

    • Advanced Digital Design


    – Top-down Design, Data path, Controllers,
    Timing, …
    • FPGAs
    – Architecture, Applications, Optimal Design, …
    • VHDL
    – VHDL ffor S
    Synthesis
    h i
    • Case Studies

    Kuruvilla Varghese

    3
    At the end of the course … 7

    System Level
    p
    • Given a set of specifications for a digital
    g
    system, you will be able to design the system
    meeting the specifications.
    • In particular, given an algorithm you will be
    able to design the datapath and the
    controller(s)
    t ll ( ) to
    t implement
    i l t the
    th functionality.
    f ti lit

    Kuruvilla Varghese

    At the end of the course … 8

    Digital Systems
    • You will be able to design the datapath using
    higher level combinational and sequential
    blocks.
    • You will be able to solve the functional and
    timing problems in the datapath.
    • You will be able to resolve various issues
    related to the controller design.
    • You will be able to resolve synchronization
    issues.
    Kuruvilla Varghese

    4
    At the end of the course … 9

    VHDL
    • You will be able to write a VHDL code to
    implement a particular design/block.
    • You will be able to analyze a VHDL code
    and infer what circuit a synthesis tool might
    generate out of a code.
    • You will know how the VHDL simulation
    tool simulates the code.
    • You will be able to write test benches to
    automate the verification process.
    Kuruvilla Varghese

    At the end of the course … 10

    FPGAs
    • You will be able to choose a pparticular FPGA
    for a particular application.
    • You will be able to use FPGAs in your
    design, meeting the area and delay constraints
    and estimate the power consumption.
    • You will be able to design and code to exploit
    the architectural features of FPGA.

    Kuruvilla Varghese

    5
    Course Laboratory 11

    • Two students per batch


    g
    • One regular DESE M Tech / ME + Other
    • Half the number of Batches on Monday, Rest
    on Wednesday
    • Mon/Wed batch DESE students would do
    Lab for E3-266 EMC on Wed/Mon
    • Lab exercises covers various aspects covered
    in course, deal with concepts
    • Mini Project
    Kuruvilla Varghese

    Course Laboratory 12

    • Lab Exercise evaluation


    – Each day exercise is evaluated
    – Show the source files
    – Show the simulations / Working on FPGA board
    – Show various Tool outputs / Reports
    – Individual Feedback / Consolidated feedback
    • Lab Submission
    – Submit source files, Simulation waveforms, Tool
    Outputs, Tool Reports, Your report
    – Use E-learning server; Moodle

    Kuruvilla Varghese

    6
    Course Laboratory 13

    • Tools
    – Xilinx ISE 14.4i, Xilinx EDK 14.4i
    – ModelSim SE
    – Xilinx Spartan 6 FPGA Boards

    Kuruvilla Varghese

    Lab Exercise Submission 14

    • Submission Site
    – Moodle: http://10.114.1.12/moodle/
    http://shukra.cedt.iisc.ernet.in/moodle/
    • Create a folder for each lab exercise with batch
    number and lab exercise number on your system
    – Y:\DSF\B01_Lex2 (Batch 1, Lex2)
    • File naming convention (e.g. lex2a
    – lex2a_1.vhd, lex2a_2.vhd, … (In case of multiple vhdl
    files)
    – lex2a_1.wlf, lex2a_2.wlf, …
    – lex2.rpt
    Kuruvilla Varghese

    7
    Lab Ex Submission Procedure (e.g. Lex2a) 15

    • Copy all sub-problem’s source (vhd) files,


    Simulation waveforms (wlf), to the Lab
    exercise folder (e.g. B01_Lex2)
    • Write a report on each Lab exercise and copy
    to Lab exercise folder (e.g. B01_Lex2)
    • Compress (zip) B01_Lex2 folder and submit
    i Moodle
    in M dl

    Kuruvilla Varghese

    Course Evaluation 16

    Sessional: 50 Marks
    Test 1: 15 Marks
    Test 2: 15 Marks
    Lab: 20 Marks
    Final
    Examination: 40 Marks
    Mini
    i i Project:
    j 10 Marks
    k

    Kuruvilla Varghese

    8
    Course Evaluation 17

    • Tests / Final Examination


    – Open book
    • Grading
    Relative but absolute also

    Kuruvilla Varghese

    Examination Schedule 18

    • Test 1
    – 20 Feb, Wednesday 10.00 – 11.00 AM
    • Test 2
    – 27 March, Wednesday 10.00 – 11.00 AM
    • Final Examination (Mostly)
    – 30 April, Tuesday 9.00 AM – 12.00 Noon

    Kuruvilla Varghese

    9
    References 19

    • John F Wakerly, Digital Design: Principles


    and Practices, Prentice Hall
    • Kevin Skahil, VHDL For Programmable
    Logic, Addison Wesley.
    • Zainalabedin Navabi, VHDL. Analysis and
    Modelling of Digital Systems, McGraw-Hill
    • Neil H E Weste,, David Harris,, Ayan
    y
    Banerjee, CMOS VLSI Design, Pearson
    Education.
    • Papers, FPGA Data sheets
    Kuruvilla Varghese

    Course Materials 20

    • Lecture Slides
    • p
    Papers
    • Tutorials
    • Data Sheets
    • Application Notes
    • Distributed through Moodle Web Server

    Kuruvilla Varghese

    10
    Moodle 21

    • http://10.114.1.12/moodle/
    p
    • http://shukra.cedt.iisc.ernet.in/moodle/
    • Available Courses
    E3 231 Digital Systems Design with FPGAs (click)
    • Login
    – Username:
    – Password:
    • Enrollment key: DSF13

    Kuruvilla Varghese

    Moodle 22

    • Left Pane: Administration


    • Middle Pane: Weekly Outline
    – Resources
    – Activities
    • Right Pane: News, Events

    • Left pane: Change Password


    • Middle Pane: Links to resources (click)
    – Html, pdf files

    Kuruvilla Varghese

    11
    Contact Instructor 23

    • Lecture and Laboratory Hours


    • DESE Room No: 225
    • Email
    – [email protected]
    – Subject: DSF13: (For Mail Filtering)

    Kuruvilla Varghese

    12

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