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CSE 140 Midterm 3 - Solution

This exam document provides instructions for a closed-book exam on computer engineering concepts. It outlines that students should write their name and ID on each page, turn off electronics, and only use one page of notes. The exam has 6 problems worth a total of 100 points. Problem 1 involves true/false and multiple choice questions about circuits and digital design concepts. Problem 2 asks students to design an arithmetic logic unit circuit. Problem 3 asks students to design a 4-bit rotator circuit. Problem 4 involves timing analysis questions. Problem 5 asks students to design a finite state machine sequence detector. Problem 6 involves designing a controller and datapath for given code.

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112 views15 pages

CSE 140 Midterm 3 - Solution

This exam document provides instructions for a closed-book exam on computer engineering concepts. It outlines that students should write their name and ID on each page, turn off electronics, and only use one page of notes. The exam has 6 problems worth a total of 100 points. Problem 1 involves true/false and multiple choice questions about circuits and digital design concepts. Problem 2 asks students to design an arithmetic logic unit circuit. Problem 3 asks students to design a 4-bit rotator circuit. Problem 4 involves timing analysis questions. Problem 5 asks students to design a finite state machine sequence detector. Problem 6 involves designing a controller and datapath for given code.

Uploaded by

yonas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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First Name: Last Name: PID:

CSE 140 Midterm 3 - Solution


Prof. Tajana Simunic Rosing
Spring 2013

z Do not start the exam until you are told.


z Write your name and PID at the top of 1. 15 points
every page. Do not separate the pages. 2. 20 points
z Turn off and put away all your 3. 15 points
electronics. 4. 15 points
z This is a closed-book, closed-notes, no- 5. 20 points
calculator exam. You may only refer to 6. 15 points
one 8 ½ x 11” page of your handwritten
notes.
Total (100 pts.)
z Do not look at anyone else’s exam. Do
not talk to anyone but an exam proctor
during the exam.
z If you have a question, raise your hand
and an exam proctor will come to you.
z You have 80 minutes to finish the exam.
When the time is finished, you must
stop writing.
z Write your answers in the provided
space.
z No credit will be given if you do not
show all steps of your work.
First Name: Last Name: PID:

Problem 1

a) True or False?

1-1. _T_The following two circuits have the same functionality.

1-2. _F_One advantage of ROM over RAM is that ROM is volatile.


1-3. _T_The output of a Mealy state machine changes asynchronously.
1-4. _F_A logic function is shown in the Karnaugh map below. The minimal
SOP implementation of this function, AB+A’C, does not have a static timing
hazard.

1-5. _T_Output Y of the circuit below computes the sum bit of a full adder.

1-6. _T_ The delay of a ripple-carry adder is linearly dependent on the


number of bits.
First Name: Last Name: PID:

1-7. _F_ A ripple-carry adder is never faster than carry-lookahead adder.

b) Multiple Choice

1-8.What sequence does the following circuit detect?

a) 011
b) 100
c) 010
d) 101

1-9.What is the canonical form for Y based on the truth table below?
INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 X
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 X
1 1 0 0
1 1 1 X

a) Σm(0,2,5)+d(1,5)
b) ΠM(0,1,2)*d(1,5)
c) Σm(3,4,5,6)+d(1,7)
d) ΠM(3,4,6)*d(1,5,7)
First Name: Last Name: PID:

1-10. What does the circuit in figure below represent? How many transistors
does it have?
A
C

D
B

a) D-latch with 6 transistors


b) SR-flip-flop with 8 transistors
c) D-flip-flop with 6 transistors
d) SR-latch with 8 transistors

1-11. What is the minimum number of D flip-flops required to design a


counter circuit that outputs the first seven Fibonacci numbers and then wraps
around? Fibonacci numbers are defined by F0=0, F1=1, Fn = Fn-1 + Fn-2.
a) 3
b) 4
c) 5
d) 6
First Name: Last Name: PID:

Problem 2 – ALU
a) Draw the schematic for an ALU with unsigned 3-bit inputs A and B and
two control bits C1 and C0. The ALU implements functionality shown in the
table below. Use a minimum number of 2:1 MUXs, a single 3-bit adder
(with a carry-in input), and a minimum number of inverters.

C1C0 Operation
00 A-B-1
01 A-B
10 B-A-1
11 B-A

with overflow bit without overflow bit


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b) Using the minimum number of 2:1 MUXs, a single 3-bit adder, and as
few gates as possible, implement the ALU functionality shown in the table
below. The logical outputs should be 0-extended, meaning that if A=001&
B=100, then A<B is true and the output is 001, and B<A is false, so that
output is 000.
Hint: Think about how to use the first four arithmetic functions to perform
the four logical operations. Your solution should be an extension of your
solution to part a)

C2C1C0 Operation
000 A-B-1
001 A-B
010 B-A-1
011 B-A
100 A<=B (zero-extended)
101 A<B (zero-extended)
110 B<=A (zero-extended)
111 B<A (zero-extended)

with overflow bit without overflow bit


First Name: Last Name: PID:

Problem 3 - Rotator
Design a 4-bit right rotator with 4-bit input A3:0and 4-bit output B3:0. The
two-bit control signal S1:0is used to determine the number of bits for A3:0 to
be shifted, as shown in the table below. For instance, suppose S1:0=10
&A3:0=1100; after rotate is completed the output B3:0=0011.You may use
eight 2:1 MUXes and a minimum number of gates to implement this
functionality.

S1:0 Rotator’s Function


00 No shift
01 Right shift by 1 bit
10 Right shift by 2 bit
11 Right shift by 3 bit
First Name: Last Name: PID:

Problem 4 - Timing
You are given a sequential circuit design as shown below.

• RpCg = 10 ps, RnCg =5 ps


• D-FF clk-to-q propagation delay tpcq=10ps
• D-FF clk-to-q contamination delay tccq=5ps
• D-FF data setup time ts=10ps
• Clock skew = 0 ps

Delay Tpd (ps) Tcd (ps)


Adder(∑) 50 20
Left shift by 1 bit(<<1) 20 10
Left shift by 2 bits(<<2) 30 20
Inverter 10 5
Mux (2:1) 15 10
First Name: Last Name: PID:

a) Calculate the maximum clock frequency for reliable operation.

period > (DFF_propagation_delay) +


(max_combination_circuit_delay) +
(DFF_setup_time) +
(max_clock_skew)
= 10 + (50+30) + 10 + 0
= 100 ps

frequency < 1 / (100ps)


= 10 GHz

b) How long should the hold time be for safe operation?

hold_time <= DFF_contamination_delay +


min_combinational_circuit_delay –
max_clock_skew

Min combinational circuit delay = transistor_delay + inverter_delay


transistor_delay = (Rp/2)*2Cg = RpCg = 10 ps
inverter_delay = 5 ps

hold_time <= 5 + (10+5) – 0


<= 20 ps
First Name: Last Name: PID:

Problem 5 – Mealy Sequence Detector


Design a sequence detector for ‘11011’ using D flip-flops. Overlap is
allowed between neighboring bit sequences. For instance, let X denote the
input and Z denote the output. Assume X=’11011011011’ and the detector
will output Z=’00001001001’.

a) Draw the Mealy FSM.

b) Fill the state transition table given below using the above FSM. Y2:0 are
state variables.

Present State Input Next State Output


Symbol Y2 Y1 Y0 X Symbol Y2+ Y1+ Y0+ Z
A 0 0 0 0 A 0 0 0 0
A 0 0 0 1 B 0 0 1 0
B 0 0 1 0 A 0 0 0 0
B 0 0 1 1 C 0 1 0 0
C 0 1 0 0 D 0 1 1 0
C 0 1 0 1 C 0 1 0 0
D 0 1 1 0 A 0 0 0 0
D 0 1 1 1 E 1 0 0 0
E 1 0 0 0 A 0 0 0 0
E 1 0 0 1 C 0 1 0 1
First Name: Last Name: PID:

c) Implement the next state logic for Y1+ & Y0+ with the hardware listed
below. Use minimum number of additional gates.
• Y1+ using a 8:1 Mux with (Y2,Y1,Y0) as select lines.
• Y0+ using a 4:1 Mux with (Y2,Y1) as select lines.
First Name: Last Name: PID:

Problem 6 – RTL Design

void main()
{
unsigned int i, start, data, mod4_count, A[128];

while(1) {

while(!start);

i=0;
mod4_count = 0;

while(i<128) {
data = A[i];
if(data%4==0) {
mod4_count++;
}
i++;
}
}
}
First Name: Last Name: PID:

a) Use the code shown above to create the high level FSM

b) Show all components in the datapath for this design.


First Name: Last Name: PID:

c) Draw the interface between the controller and the datapath, show all
inputs and outputs.
First Name: Last Name: PID:

This page is intentionally left blank. Use it as scratch paper or to provide


additional answers.

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