Tomasulo’s Reservation Station Components

Algorithm Op: Operation to perform in the unit (e.g., + or –)

Vj, Vk: Value of Source operands
– Store buffers has V field, result to be stored
Qj, Qk: Reservation stations producing source registers (value to
be written)
Note: reservations
stations do not – Note: Qj,Qk=0 => ready
form a queue! They
all have independent – Store buffers only have Qi for RS producing result
access to FP op unit
Busy: Indicates reservation station or FU is busy
Note: there may be
multiple or pipelined
FP op units – Register result status—Indicates which functional unit will write
conceptually same! each register, if one exists. Blank when no pending instructions
that will write that register.
Basic structure of MIPS floating-point unit based on Tomasulo

Three Stages of Tomasulo Algorithm Example

1. Issue—get instruction from FP Op Queue

If reservation station free (no structural hazard), 1. L.D F6, 34(R2)
control issues instr & sends operands (renames registers).
2. L.D F2, 45(R3)
2. Execute—operate on operands (EX)
When both operands ready then execute; 3. MUL.D F0, F2, F4
if not ready, watch Common Data Bus for result
3. Write result—finish execution (WB) 4. SUB.D F8, F2, F6
Write on Common Data Bus to all awaiting units;
mark reservation station available
5. DIV.D F10, F0, F6
• Normal data bus: data + destination (“go to” bus) 6. ADD.D F6, F8, F2
• Common data bus: data + source (“come from” bus)
– 64 bits of data + 4 bits of Functional Unit source address
– Write if matches expected Functional Unit (produces result)
– Does the broadcast
• Example speed:
3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for /
 Latencies Tomasulo Example
Instruction stream
Instruction status: Exec Write
• Assume operation latencies Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 Load1 No
– load: 2 clock cycles
LD F2 45+ R3 Load2 No
– add/sub: 2 clock cycles MULTD F0 F2 F4 Load3 No
SUBD F8 F6 F2
– multiply: 10 clock cycles
DIVD F10 F0 F6
– divide: 40 clock cycles ADDD F6 F8 F2
3 Load/Buffers

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
FU count Add2 No
3 FP Adder R.S.
down Add3 No
2 FP Mult R.S.
Mult1 No
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
0 FU

Clock cycle
counter

Tomasulo Example Cycle 1 Tomasulo Example Cycle 2

Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 Load1 Yes 34+R2 LD F6 34+ R2 1 Load1 Yes 34+R2
LD F2 45+ R3 Load2 No LD F2 45+ R3 2 Load2 Yes 45+R3
MULTD F0 F2 F4 Load3 No MULTD F0 F2 F4 Load3 No
SUBD F8 F6 F2 SUBD F8 F6 F2
DIVD F10 F0 F6 DIVD F10 F0 F6
ADDD F6 F8 F2 ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
Add2 No Add2 No
Add3 No Add3 No
Mult1 No Mult1 No
Mult2 No Mult2 No

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
1 FU Load1 2 FU Load2 Load1

Note: Can have multiple loads outstanding

 Tomasulo Example Cycle 3 Tomasulo Example Cycle 4
Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 Load1 Yes 34+R2 LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 Load2 Yes 45+R3 LD F2 45+ R3 2 4 Load2 Yes 45+R3
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 SUBD F8 F6 F2 4
DIVD F10 F0 F6 DIVD F10 F0 F6
ADDD F6 F8 F2 ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 Yes SUBD M(A1) Load2
Add2 No Add2 No
Add3 No Add3 No
Mult1 Yes MULTD R(F4) Load2 Mult1 Yes MULTD R(F4) Load2
Mult2 No Mult2 No

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
3 FU Mult1 Load2 Load1 4 FU Mult1 Load2 M(A1) Add1

• Note: registers names are removed (“renamed”) in Reservation

Stations; MULT issued • Load2 completing; what is waiting for Load2?
• Load1 completing; what is waiting for Load1?

Tomasulo Example Cycle 5 Tomasulo Example Cycle 6

Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 SUBD F8 F6 F2 4
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
2 Add1 Yes SUBD M(A1) M(A2) 1 Add1 Yes SUBD M(A1) M(A2)
Add2 No Add2 Yes ADDD M(A2) Add1
Add3 No Add3 No
10 Mult1 Yes MULTD M(A2) R(F4) 9 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1 Mult2 Yes DIVD M(A1) Mult1

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
5 FU Mult1 M(A2) M(A1) Add1 Mult2 6 FU Mult1 M(A2) Add2 Add1 Mult2

• Timer starts down for Add1, Mult1

• Issue ADDD here despite name dependency on F6?
 Tomasulo Example Cycle 7 Tomasulo Example Cycle 8
Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
0 Add1 Yes SUBD M(A1) M(A2) Add1 No
Add2 Yes ADDD M(A2) Add1 2 Add2 Yes ADDD (M-M) M(A2)
Add3 No Add3 No
8 Mult1 Yes MULTD M(A2) R(F4) 7 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1 Mult2 Yes DIVD M(A1) Mult1

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
7 FU Mult1 M(A2) Add2 Add1 Mult2 8 FU Mult1 M(A2) Add2 (M-M) Mult2

• Add1 (SUBD) completing; what is waiting for it?

Tomasulo Example Cycle 9 Tomasulo Example Cycle 10

Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 ADDD F6 F8 F2 6 10

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
1 Add2 Yes ADDD (M-M) M(A2) 0 Add2 Yes ADDD (M-M) M(A2)
Add3 No Add3 No
6 Mult1 Yes MULTD M(A2) R(F4) 5 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1 Mult2 Yes DIVD M(A1) Mult1

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
9 FU Mult1 M(A2) Add2 (M-M) Mult2 10 FU Mult1 M(A2) Add2 (M-M) Mult2

• Add2 (ADDD) completing; what is waiting for it?

 Tomasulo Example Cycle 11 Tomasulo Example Cycle 12
Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11 ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
Add2 No Add2 No
Add3 No Add3 No
4 Mult1 Yes MULTD M(A2) R(F4) 3 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1 Mult2 Yes DIVD M(A1) Mult1

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
11 FU Mult1 M(A2) (M-M+M)(M-M) Mult2 12 FU Mult1 M(A2) (M-M+M)(M-M) Mult2

• Write result of ADDD here?

• All quick instructions complete in this cycle!

Tomasulo Example Cycle 13 Tomasulo Example Cycle 14

Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11 ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
Add2 No Add2 No
Add3 No Add3 No
2 Mult1 Yes MULTD M(A2) R(F4) 1 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1 Mult2 Yes DIVD M(A1) Mult1

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
13 FU Mult1 M(A2) (M-M+M)(M-M) Mult2 14 FU Mult1 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 15 Tomasulo Example Cycle 16
Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 Load3 No MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11 ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
Add2 No Add2 No
Add3 No Add3 No
0 Mult1 Yes MULTD M(A2) R(F4) Mult1 No
Mult2 Yes DIVD M(A1) Mult1 40 Mult2 Yes DIVD M*F4 M(A1)

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
15 FU Mult1 M(A2) (M-M+M)(M-M) Mult2 16 FU M*F4 M(A2) (M-M+M)(M-M) Mult2

• Mult1 (MULTD) completing; what is waiting for it? • Just waiting for Mult2 (DIVD) to complete

Tomasulo Example Cycle 55

Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
skip a couple of cycles ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
1 Mult2 Yes DIVD M*F4 M(A1)

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
55 FU M*F4 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 56 Tomasulo Example Cycle 57
Instruction status: Exec Write Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8 SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 56 DIVD F10 F0 F6 5 56 57
ADDD F6 F8 F2 6 10 11 ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS Reservation Stations: S1 S2 RS RS

Time Name Busy Op Vj Vk Qj Qk Time Name Busy Op Vj Vk Qj Qk
Add1 No Add1 No
Add2 No Add2 No
Add3 No Add3 No
Mult1 No Mult1 No
0 Mult2 Yes DIVD M*F4 M(A1) Mult2 Yes DIVD M*F4 M(A1)

Register result status: Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30 Clock F0 F2 F4 F6 F8 F10 F12 ... F30
56 FU M*F4 M(A2) (M-M+M)(M-M) Mult2 56 FU M*F4 M(A2) (M-M+M)(M-M) Result

• Once again: In-order issue, out-of-order execution and

• Mult2 (DIVD) is completing; what is waiting for it? out-of-order completion.

Tomasulo Drawbacks Tomasulo Loop Example

Loop:LD F0 0 R1
MULTD F4 F0 F2
• Complexity
SD F4 0 R1
• Many associative stores (CDB) at high speed
• Performance limited by Common Data Bus SUBI R1 R1 #8
BNEZ R1 Loop
– Each CDB must go to multiple functional units
high capacitance, high wiring density • This time assume Multiply takes 4 clocks
– Number of functional units that can complete • Assume 1st load takes 8 clocks
per cycle limited to one! (L1 cache miss)
» Multiple CDBs  more FU logic for parallel assoc • Stores take 3 clock cycles
stores • Show 2 iterations
 Loop Example Loop Example Cycle 1
Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 Load1 No 1 LD F0 0 R1 1 Load1 Yes 80
1 MULTD F4 F0 F2 Load2 No Load2 No
1 SD F4 0 R1 Load3 No Load3 No
Iter-
2 LD F0 0 R1 Store1 No Store1 No
ation 2 MULTD F4 F0 F2 Store2 No Store2 No
Count 2 SD F4 0 R1 Store3 No Store3 No
Reservation Stations: S1 S2 RS Added Store Buffers Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 No SUBI R1 R1 #8 Mult1 No SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 No BNEZ R1 Loop
Register result status Instruction Loop Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
0 80 Fu 1 80 Fu Load1

Value of Register used for address, iteration control

Loop Example Cycle 2 Loop Example Cycle 3

Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 Load1 Yes 80 1 LD F0 0 R1 1 Load1 Yes 80
1 MULTD F4 F0 F2 2 Load2 No 1 MULTD F4 F0 F2 2 Load2 No
Load3 No 1 SD F4 0 R1 3 Load3 No
Store1 No Store1 Yes 80 Mult1
Store2 No Store2 No
Store3 No Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 No BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
2 80 Fu Load1 Mult1 3 80 Fu Load1 Mult1

• Implicit renaming sets up data flow graph

 Loop Example Cycle 4 Loop Example Cycle 5
Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 Load1 Yes 80 1 LD F0 0 R1 1 Load1 Yes 80
1 MULTD F4 F0 F2 2 Load2 No 1 MULTD F4 F0 F2 2 Load2 No
1 SD F4 0 R1 3 Load3 No 1 SD F4 0 R1 3 Load3 No
Store1 Yes 80 Mult1 Store1 Yes 80 Mult1
Store2 No Store2 No
Store3 No Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 No BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
4 80 Fu Load1 Mult1 5 72 Fu Load1 Mult1

• Dispatching SUBI Instruction • And, BNEZ instruction

Loop Example Cycle 6 Loop Example Cycle 7

Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 Load1 Yes 80 1 LD F0 0 R1 1 Load1 Yes 80
1 MULTD F4 F0 F2 2 Load2 Yes 72 1 MULTD F4 F0 F2 2 Load2 Yes 72
1 SD F4 0 R1 3 Load3 No 1 SD F4 0 R1 3 Load3 No
2 LD F0 0 R1 6 Store1 Yes 80 Mult1 2 LD F0 0 R1 6 Store1 Yes 80 Mult1
Store2 No 2 MULTD F4 F0 F2 7 Store2 No
Store3 No Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
6 72 Fu Load2 Mult1 7 72 Fu Load2 Mult2
• Register file completely detached from computation
• Notice that F0 never sees Load from location 80 • First and Second iteration completely overlapped
 Loop Example Cycle 8 Loop Example Cycle 9
Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 Load1 Yes 80 1 LD F0 0 R1 1 9 Load1 Yes 80
1 MULTD F4 F0 F2 2 Load2 Yes 72 1 MULTD F4 F0 F2 2 Load2 Yes 72
1 SD F4 0 R1 3 Load3 No 1 SD F4 0 R1 3 Load3 No
2 LD F0 0 R1 6 Store1 Yes 80 Mult1 2 LD F0 0 R1 6 Store1 Yes 80 Mult1
2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2
2 SD F4 0 R1 8 Store3 No 2 SD F4 0 R1 8 Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8
Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
8 72 Fu Load2 Mult2 9 72 Fu Load2 Mult2

• Load1 completing: who is waiting?

• Note: Dispatching SUBI

Loop Example Cycle 10 Loop Example Cycle 11

Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 9 10 Load1 No 1 LD F0 0 R1 1 9 10 Load1 No
1 MULTD F4 F0 F2 2 Load2 Yes 72 1 MULTD F4 F0 F2 2 Load2 No
1 SD F4 0 R1 3 Load3 No 1 SD F4 0 R1 3 Load3 Yes 64
2 LD F0 0 R1 6 10 Store1 Yes 80 Mult1 2 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult1
2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2
2 SD F4 0 R1 8 Store3 No 2 SD F4 0 R1 8 Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
4 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 3 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8
Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop 4 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
10 64 Fu Load2 Mult2 11 64 Fu Load3 Mult2

• Load2 completing: who is waiting? • Next load in sequence

• Note: Dispatching BNEZ
 Loop Example Cycle 12 Loop Example Cycle 13
Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 9 10 Load1 No 1 LD F0 0 R1 1 9 10 Load1 No
1 MULTD F4 F0 F2 2 Load2 No 1 MULTD F4 F0 F2 2 Load2 No
1 SD F4 0 R1 3 Load3 Yes 64 1 SD F4 0 R1 3 Load3 Yes 64
2 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult1 2 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult1
2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2
2 SD F4 0 R1 8 Store3 No 2 SD F4 0 R1 8 Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
2 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 1 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8
3 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop 2 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
12 64 Fu Load3 Mult2 13 64 Fu Load3 Mult2

• Why not issue third multiply? • Why not issue third store?

Loop Example Cycle 14 Loop Example Cycle 15

Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 9 10 Load1 No 1 LD F0 0 R1 1 9 10 Load1 No
1 MULTD F4 F0 F2 2 14 Load2 No 1 MULTD F4 F0 F2 2 14 15 Load2 No
1 SD F4 0 R1 3 Load3 Yes 64 1 SD F4 0 R1 3 Load3 Yes 64
2 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult1 2 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R2
2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 MULTD F4 F0 F2 7 15 Store2 Yes 72 Mult2
2 SD F4 0 R1 8 Store3 No 2 SD F4 0 R1 8 Store3 No
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
0 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 Mult1 No SUBI R1 R1 #8
1 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop 0 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
14 64 Fu Load3 Mult2 15 64 Fu Load3 Mult2

• Mult1 completing. Who is waiting? • Mult2 completing. Who is waiting?

 Loop Example Cycle 16 Loop Example Cycle 17
Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 9 10 Load1 No 1 LD F0 0 R1 1 9 10 Load1 No
1 MULTD F4 F0 F2 2 14 15 Load2 No 1 MULTD F4 F0 F2 2 14 15 Load2 No
1 SD F4 0 R1 3 Load3 Yes 64 1 SD F4 0 R1 3 Load3 Yes 64
2 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R2 2 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R2
2 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R2 2 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R2
2 SD F4 0 R1 8 Store3 No 2 SD F4 0 R1 8 Store3 Yes 64 Mult1
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
4 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 No BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
16 64 Fu Load3 Mult1 17 64 Fu Load3 Mult1

Loop Example Cycle 18 Loop Example Cycle 19

Instruction status: Exec Write Instruction status: Exec Write
ITER Instruction j k Issue CompResult Busy Addr Fu ITER Instruction j k Issue CompResult Busy Addr Fu
1 LD F0 0 R1 1 9 10 Load1 No 1 LD F0 0 R1 1 9 10 Load1 No
1 MULTD F4 F0 F2 2 14 15 Load2 No 1 MULTD F4 F0 F2 2 14 15 Load2 No
1 SD F4 0 R1 3 18 Load3 Yes 64 1 SD F4 0 R1 3 18 19 Load3 Yes 64
2 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R2 2 LD F0 0 R1 6 10 11 Store1 No
2 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R2 2 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R2
2 SD F4 0 R1 8 Store3 Yes 64 Mult1 2 SD F4 0 R1 8 19 Store3 Yes 64 Mult1
Reservation Stations: S1 S2 RS Reservation Stations: S1 S2 RS
Time Name Busy Op Vj Vk Qj Qk Code: Time Name Busy Op Vj Vk Qj Qk Code:
Add1 No LD F0 0 R1 Add1 No LD F0 0 R1
Add2 No MULTD F4 F0 F2 Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1 Add3 No SD F4 0 R1
Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop Mult2 No BNEZ R1 Loop
Register result status Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30 Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
18 64 Fu Load3 Mult1 19 56 Fu Load3 Mult1
 Loop Example Cycle 20 Why can Tomasulo overlap iterations of
Instruction status: Exec Write loops?
ITER Instruction j k Issue CompResult Busy Addr Fu • Register renaming
1 LD F0 0 R1 1 9 10 Load1 Yes 56
1 MULTD F4 F0 F2 2 14 15 Load2 No – Multiple iterations use different physical
1
2
SD
LD
F4
F0
0
0
R1
R1
3
6
18
10
19
11
Load3
Store1
Yes
No
64
destinations for registers (dynamic loop unrolling).
2 MULTD F4 F0 F2 7 15 16 Store2 No • Reservation stations
2 SD F4 0 R1 8 19 20 Store3 Yes 64 Mult1
Reservation Stations: S1 S2 RS
– Also buffer old values of registers - totally avoiding
Time Name Busy Op Vj Vk Qj Qk Code: the WAR stall.
Add1 No LD F0 0 R1 • Other perspective: Tomasulo building data flow dependency
Add2 No MULTD F4 F0 F2
Add3 No SD F4 0 R1
graph on the fly.
Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8
Mult2 No BNEZ R1 Loop
Register result status
Clock R1 F0 F2 F4 F6 F8 F10 F12 ... F30
20 56 Fu Load1 Mult1

• Once again: In-order issue, out-of-order execution and

out-of-order completion.

Tomasulo’s scheme offers 2 major advantages Summary

• Reservations stations: implicit register renaming to larger set of registers +
(1) the distribution of the hazard detection logic buffering source operands
– distributed reservation stations and the CDB – Prevents registers as bottleneck
– Avoids WAR, WAW hazards
– If multiple instructions waiting on single – Allows loop unrolling in HW
result, & each instruction has other operand, • Not limited to basic blocks
then instructions can be released • Today, helps cache misses as well
simultaneously by broadcast on CDB – Don’t stall for L1 Data cache miss
• Lasting Contributions
– If a centralized register file were used, the – Dynamic scheduling
units would have to read their results from – Register renaming
the registers when register buses are • 360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA
8000; Alpha 21264
available.
(2) the elimination of stalls for WAW and WAR hazards