Structure of Assembly language An Assembly language instruction consists of a mnemonic, optionally followed by one or two operands. [label] mnemonic {operands] (; comment) Brackets indicate that a field is optional and not all lines have them. Brackets should not be typed in.EXAMPLE 7PIC Assembly Language Program To Add Some Data. ;store SUM in fileReg location 10H. SUM HERE EQU 10H ORG OH MOVLW 25H ADDLW 0x34 ADDLW 11H ADDLW D'18!' ADDLW 1CH ADDLW B'00000110' MOVWE SUM GOTO HERE END 7RAM loc 10H for SUM ;Start at address 0 ;WREG = 25 jadd 34H to WREG j;add 11H to WREG iW W + 12H = 7CH 7Wo= W + 1CH = 98H 7Wo= Wo + 6 = SEH ;save the SUM in loc 10H stay here forever jend of asm source fileHow to Increase the Processor Power 1. Increase the clock frequency of the chip. One drawback of this method is that the higher the frequency, the more power and heat dissipation. 2. Use Harvard architecture by increasing the number of buses to bring more information ( code and data) into the CPU to be processed. 3. Change the internal architecture of the CPU and use what is called RISC architecture. Microchip used all three methods to increase the processing power of the PIC18 microcontrollers.RISC architecture Features of RISC 1. RISC processors have a fixed instruction size. In a CISC microcontroller such as the 8051, instructions can be I, 2, or even 3 bytes. One of the major characteristics of RISC architecture is a large number of registers. All RISC architectures have at least 32 registers. RISC processors have a small instruction set. RISC processors have only the basic instructions such as ADD, SUB, MUL, LOAD, STORE, AND, OR, EXOR, CALL, JUMP, and so on. This is one reason that RISC is used more commonly in high-level language environments such as the C programming language rather than Assembly language environments.RISC architecture Features of RISC 4. The most important characteristic of the RISC processor is that more than 95% of instructions are executed with only one clock cycle, in contrast to CISC instructions. 5. RISC processors have separate buses for data and code. There are four sets of buses: (1)a set of data buses for carrying data (operands) in and out of the CPU, (2) a set of address buses for accessing the data, (3) a set of buses to carry the opcodes, and ( 4)a set of address buses to access the opcodes.BRANCH, CALL, AND TIME DELAY LOOP Looping in PIC Repeating a sequence of instructions or an operation a certain number of times is called a loop. In the PIC, there are several ways to repeat an operation many times. One way is to repeat the operation over and over until it is finished, as shown below: MOVLW 0 jWREG = 0 ADDLW 3 jadd value 3 to WREG ADDLW 3 jadd value 3 to WREG(W = 6) ADDLW 3 j;add value 3 to WREG(W = 9) ADDLW 3 yadd value 3 to WREG(W = O0Ch) ADDLW 3 ;add value 3 to WREG(W = OFhBRANCH, CALL, AND TIME DELAY LOOP DECFSZ instruction and looping The DECFSZ (decrement fileReg skip zero) instruction is a widely used instruction supported across all PIC families DECFSZ fileReg .d decrement fileReg and skip next instruction if 6 In this instruction, the fileReg is decremented, and if its content is zero, it skips the next instruction.BRANCH, CALL, AND TIME DELAY LOOP DECFSZ instruction and looping ADD 3 TO WREG DEC COUNT, IS IT ZERO? INSTRUCTIONS AGAIN ADDLW 3. DEGFSZ COUNT ‘SKIP THE NEXT INSTRUCTION GOTO AGAIN MOWWF PORTBEXAMPLE Write a program to (a) clear WREG, and (b) add 3 to WREG ten times and place the result in SFR of PORTB. Use the DECFSZ instruction to perform looping. Solution: ;this program adds value 3 to WREG ten times COUNT EQU 0x25 AGAIN MOVLW MOVWF MOVLW ADDLW DECFSZ GOTO MOVWF d'10" COUNT 0 3 COUNT, F AGAIN PORTB use loc 25H for counter ;WREG = 10 (decimal) for counter jload the counter iWREG = 0 add 03 to WREG (WREG = sum ;decrement counter, skip if count = 0 jrepeat until count becomes 0 ;send sum to PORTB SFRBRANCH, CALL, AND TIME DELAY LOOP Using instruction BNZ for looping The BNZ (branch if not zero) instruction is supported by the PIC18 family and not earlier families such as PIC16 or PIC12. It uses the zero flag in the status register. The BNZ instruction is used as follows: ;start of the loop pbody of the loop tibody of the loop ;decrement fileReg, Z = 1 if fileReg = 0 ibranch to BACK if Z = 0 BACKEXAMPLE Write a program to (a) clear WREG, then (b) add 3 to WREG ten times. Use the zero flag and BNZ. Solution: this program adds value 3 to the WREG ten times COUNT EQU 0x25 fuse loc 25H for counter MOVLW d'10' ;WREG = 10 (decimal) for counter MOVWF COUNT load the counter MOVLW 0 :WREG = 0 AGAIN ADDLW 3 zadd 03 to WREG (WREG = sum) BECF COUNT, F idecrement counter BNZ AGAIN repeat until COUNT = 0 MOVWF PORTB send sum to PORTE SFREXAMPLE AGAIN Movoto" Movew 0 ADOLWEXAMPLE What is the maximum number of times that the loop in Example 3-2 can be repeated? Solution: Because location COUNT in fileReg is an 8-bit register, it can hold a maximum of FFH (255 decimal); therefore, the loop can be repeated a maximum of 255 times.BRANCH, CALL, AND TIME DELAY LOOP Loop inside a loop What happens if we want to repeat an action more times than 255? To do that, we use a loop inside a loop, which is called a nested loop. In a nested loop, we use two registers to hold the count. EXAMPLE Write a program to (a) load the PORTB SFR register with the value 55H, and (b) complement Port B 700 times. Solution: Because 700 is larger than 255 (the maximum capacity of any register), we use two registers to hold the count.BRANCH, CALL, AND TIME DELAY LOOP LOP_1 LOP_2 Ri EQU 0x25 R2 EQU 0x26 COUNT_1 EQU d‘10' COUNT_2 EQU d'70' MOVLW MOVWE MOVLW MOVWP MOVLW MOVWP COMPF 0x55 PORTB COUNT_1 R1 COUNT_2 R2 PORTB, F DECF R2, F BNZ LOP_2 DECF R1, F BNZ LOP_1 ;WREG = 5Sh ;PORTB = 5Sh 7WREG = 10, outer loop count value jload 10 into loc 25H (outer loop count) ;WREG = 70, inner loop count value jload 70 into loc 26H icomplement Port B SFR jdec fileReg loc 26 (inner loop) repeat it 70 times dec fileReg loc 25 (outer loop) 7;repeat it 10 timesBRANCH, CALL, AND TIME DELAY LOOP Looping 100,000 times Because two registers give us a maximum value of 65025 (255 x 255 = 65025), we can use three registers to get up to more than 16 million (224) iterations. The following code repeats an action 100,000 times: EXAMPLE Repeat the previous example but for 100000 times Solution:BRANCH, CALL, AND TIME DELAY LOOP Rl EQU 0x1 ;assign RAM loc for the R1-R2 R2 EQU 0x2 R2 EQU 0x3 COUNT_1 EQU D'100! ;fixed value for 100,000 times COUNT 2 EQU D'100" COUNT_3 EQU D110! MOVLW 0x55 MOWWF 2ORTB MOVLW COUNT_3 MOVWF R3 LOP_3 MOVLW COUNT_2 MOVWF R2 LOP_2 MOVLW COUNT_1 MOVWF R1 LOP_1 COMPF PORTB, F DECF Rl ,F BNZ LOP_1 DECF R2, F BNZ OP 2 DECF R3, F BNZ LOP_3BRANCH, CALL, AND TIME DELAY LOOP Other conditional jumps Notice that some of the instructions, such as BZ (Branch if Z = 1) and BC (Branch if C = 1), jump only if a certain condition is met. Next, we examine some conditional branch instructions with examples. Instruction Action BC Branch if C= 1 BNC Branch if C #0 BZ Branch if Z= 1 BNZ Branch if Z #0 BN Branch if N = 1 BNN Branch if N #0 BOV Branch if OV = 1 BNOV Branch ifOV #0BRANCH, CALL, AND TIME DELAY LOOP BZ (Branch if Z = 1) In this instruction, the Z flag is checked. If it is high, it jumps to the target address. For example, look at the following code. OVER MOVF PORTB,W ;read Port B and put it in WREG JZ OVER jump if WREG is zero Notice that the BZ instruction can be used to see whether any fileReg or WREG is zero. Although we can use BNZ along with DECF to perform a loop, it is better to use an instruction such as DCFSNZ, because it combines the decrement and jump into a single instruction.EXAMPLE Write a program to determine if fileReg location Ox30 contains the value 0. If so, put 55H in it. Solution: MYLOC EQU 0x30 MOVE MYLOC, F BNZ ‘NEXT MOVLW 0x55 MOVWF MYLOC NEXT ;eopy MYLOC to itself abranch if MYLOC is not zero gput 0x55 if MYLOC has zero valueBRANCH, CALL, AND TIME DELAY LOOP BNC (branch if no carry, branch if CY = O) In this instruction, the carry flag bit in the Status register is used to make the decision whether to jump. In executing "BNC label", the processor looks at the carry flag to see if it is raised (C = 1 ). If it is not, the CPU starts to fetch and execute instructions from the address of the label. If C = 1, it will not branch but will execute the next instruction below BNC.EXAMPLE Find the sum of the values 79H, FSH, and E2H. Put the sum in fileReg locations 5 (low byte) and 6 (high byte). Solution: L_Byte EQU 0x5 jassign RAM loc 5 to L_byte of sum H_Byte EQU 0x6 jassign RAM loc 6 to H_byte of sum ORG Oh MOVLW Ox0 clear WREG(WREG = 0) MOVWP H_Byte i Byte = 0 ADDLW 0x79 0 + 79H = 79H, C= 0 BNC NLL 0, add next number INCF H_Byte,F Nl ADDLW 0xF5 BNC) N_2 INCF H_Byte,F N_2 ADDLW 0xE2 BNC OVER ifc-o INCF H_Byte,F increment (now H Byte = 2) OVER MOWHF L Byte ynow L_Byte = 50H, and H Byte = 02 END increment (now H_Byte = 0} 194 FB = 6B and C= 1 if cy = 0 increment (now H_Byte = 1) 6B + E2 = 50 and C=1EXAMPLE MEMORY LOCATION 4 s s (3 a WREG = 79H NOs NOaeBRANCH, CALL, AND TIME DELAY LOOP Unconditional branch instruction GOTO and BRA (branch) GOTO and BRA is an unconditional jump that can go to any memory location in the 2M address space of the PIC18.BRANCH, CALL, AND TIME DELAY LOOP CALL/RETURN instruction Another control transfer instruction is the CALL instruction, which is used to call a subroutine. Subroutines are often used to perform tasks that need to be performed frequently, This makes a program more structured in addition to saving memory space.BRANCH, CALL, AND TIME DELAY LOOP Calling many subroutines from the main program In Assembly language programming, it is common to have one main program and many subroutines that are called from the main program. iMAIN program calling subroutines. ORG 9 MAIN CALL SUBR_1 CALL SUBR_2 CALL SUBR_3 HERE BRA HERE istay here SUBR_1 RETURN —end of subroutine 1 SUBR_2 RETURN j———end of subroutine 2 SUBR_3 RETURN —end of subroutine 3 END yend of the asm file