Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves

Generator
Esteban O. Garcia, Rene Cumplido, Miguel Arias
Department of Computer Science, INAOE. Puebla, Mexico
Phone +52 222 2663100 Fax +52 222 2663152 E-mail:{eomargr,rcumplido,ariasm}@inaoep.mx

Reconfigurable computing techniques combine software

Abstract –– Sine and Cosine waves have been used in flexibility with hardware performance. System designers
countless applications; in recent research on Software Defined may use FPGA technologies in different ways. In this work,
Radio (SDR), digital modalities of sine and cosine waves have FPGA is used for quick prototyping and testing. CORDIC
received special attention. SDR involves highly reconfigurable
characteristics and FPGA flexibility are used to implement
resources and uses digital generated waves for modulation and
demodulation of signals. Coordinate Rotation Digital Computer CORDIC in pipeline, so iterative cycles in CORDIC are
(CORDIC) is a well known algorithm used to approximate avoided.
iteratively some transcendental functions. In this work, a
pipelined CORDIC architecture is used for designing a flexible Present work is divided as follows: Section II introduces
and scalable digital sine and cosine waves generator. An CORDIC algorithm; Section III presents architecture and
FPGA-Based architecture is presented and the design has been details of the pipeline and angles sequencer; Section IV is
implemented on a Xilinx Spartan 3 device. Synthesis and dedicated to results and at Section V conclusions are
implementation results are shown and discussed. discussed.
Keywords –– CORDIC, FPGA, SDR.
II. CORDIC ALGORITHM
I. INTRODUCTION
There exist two modalities of CORDIC algorithm,
There are plenty of applications which require digital vectoring and rotation mode. In vectoring mode, coordinates
wave generators. Wireless and mobile systems are among (x0,y0) are rotated until y0 converges to zero. In rotation
the fastest growing application areas; in particular, Software mode, initial vector (x0,y0) starts aligned with the x axis and
Defined Radio (SDR) is currently a focus of research and is rotated by an angle of θi every cycle, so after n iterations,
development. An SDR system allows performing many θn is the obtained angle. For this work, rotation mode is used
functions based on a single hardware platform, thus highly to approximate sine and cosine functions.
reconfigurable resources for signal processing are needed,
mainly for modulation and demodulation of digital signals. The way CORDIC works is related to trigonometric
Fields of development are increasing every day with functions properties. The main idea consists in taking a
applications such as cell phones or military unary vector and applying successive rotations, called
communications. microrotations, until the desired angle is reached. The
rotating vector is unary, so after n iterations it will contain
There are several ways to generate digital sine and sinθn and cosθn in its second and first components
cosine waves, all of them based on trigonometric functions. respectively. In the following paragraphs it will be shown
The use of previously calculated tables is one of the choices, that calculus can be simplified if the starting vector is
but it requires excessive memory usage when good approximated to a constant value K.
quantization level is needed. CORDIC algorithm on the
other hand, offers an excellent alternative, and its best Starting vector is defined as v0=(x0,y0). In order to make
characteristic is flexibility. It allows having as much the vector rotation, a linear transform, which can be
quantization accuracy as permitted by word length. So it is described by a matrix which is multiplied by a vector, is
useful to generate low frequencies without losing definition. used. After n iterations, the vector (xn,yn) is

CORDIC algorithm, also known as Volder algorithm, xn = x0 cos θ - y0 sin θ (1)

had its first application in pocket calculators but nowadays yn = y0 cos θ + x0 sin θ (2)
is used to design coprocessors, build Discrete Fourier and
Cosine transforms, among other mathematical processes In each iteration i, the vector performs a microrotation
[1-6]. For its electronic implementation, CORDIC offers the by θi, so the new vector is calculated with a similar function:
favorable condition of not requiring either multiplication or
division blocks, instead of that, it works only with xi+1 = xi cos θi+1 – yi sin θi+1 (3)
adder-subtractor and shifter. yi+1 = yi cos θi+1 + xi sin θi+1 (4)
 When the term cos θi+1 is factorized, components in the
vector are described by

xi+1 = cosθi+1 (xi – yi tan θi+1 ) (5)

yi+1 = cosθi+1 (yi + xi tan θi+1 ) (6)

tan θi+1 is restricted to ± 2-i, so multiplication is converted in

an arithmetic right shift. It is also useful to use the identity
cos θi+1 = cos ( arctan 2-i ) to define the next variables

Ki = cos ( arctan 2-i ) = 1/√(1+2-2i) (7)

di = ± 1 (8)

Cosine is an even function, therefore cos (α) = cos (-α). Fig. 1. Microrotations with K compensation.
So (5) and (6) can be transformed into
The sum of the rotating angles gives the desired angle
xi+1 = Ki (xi – yi di 2-i ) (9)
yi+1 = Ki (yi + xi di 2-i ) (10) θn = ∑ di arctan 2-i (16)
Multiplication by Ki is avoided by considering it as a Because the first tangent value is 20=1, it is possible to
gain factor for all iterations. If n iterations are performed, rotate angles only in the range [-π/2,π/2], which is the
then K is defined as the multiplication of every Ki . convergence range. Arctan 2-i can be calculated a priori to
avoid the implementation of a arctan function on the FPGA.
K = ∏Ki = ∏ 1/√(1+2-2i) (11)
III. ARCHITECTURE
Ki is retired from (9) and (10), then it is considered at the
starting vector, which must be initialized as v0 = (|K|,0). At As it has been mentioned, a CORDIC implementation
the end of n rotations, the length of vector will be 1, so its does not need to have either sine or cosine values on
components will contain cosine and sine values of the memory, instead, it approximates the results on each step of
desired angle (Fig. 1). As the vector is initialized with the iterative process. The proposed architecture may be
constant K, the vector components for each iteration are extended for a specific resolution without a considerable
simplified to increase in the number of components used.
xi+1 = xi – yi di 2-i (12) Iterative CORDIC implementations take more than a
yi+1 = yi + xi di 2-i (13) clock cycle for each output value. It is useful when no
successive calculi are needed; such is the case of calculators.
On each iteration it is necessary to decide whether di =1 In this work, a generator needs to calculate successive
or di =-1. In order to make that decision, the difference values of sine and cosine. Therefore the proposed digital
between the desired angle and the current angle is used. So a wave generator has a pipelined CORDIC module as nucleus.
new variable known as accumulator is defined as It is composed of three adders-subtractors and two
arithmetic shifters (Fig. 2). Each adder-subtractor is
zi+1 = zi – di arctan 2-i (14) associated to one of the variables of vector component and
accumulator angle, called x, y, z. Each module has three
The value of z0 is the angle for which sine and cosine inputs and outputs of this type, a clock signal and an input to
are to be calculated. To know whether di should be positive manage cosine inversion, which is used to decide whether or
or negative, the following rule is used not to correct the quadrant in cosine function. This is
necessary due to the convergence range of CORDIC
-1 sin zi < 0 explained en section II. Details about cosine inversion will
di = +1 sin zi ≥ 0 (15) be given when angle sequencer is explained. In an iterative
implementation of CORDIC, a step control module is
necessary to adapt the shift amount to the corresponding
iteration. The first iteration there is only one move shift, for
the second there will be two moves and so on.
 created to accomplish this function has been called angle
sequencer. Given than CORDIC only converges within the
first and fourth quadrant, it was needed a sequencer to
generate angles going from 0 to π/2, then from π /2 to -π/2
and finally from π/2 to 0. To solve this, a sawtooth wave
generator was build. It starts at zero and increases its output
value until 2n, where n is the angle depth in bits. As 2’s
complement logic is used, once 2n is reached the signal goes
from the top positive value to the minimum negative value,
then it increases again and repeats the cycle.

Fig. 2. Iterative CORDIC

In order to reduce the number of clock cycles, the proposed

pipelined architecture uses a set of stages, each of them
based on iterative CORDIC module, but shifts are fixed
instead of having a step control to change shift amount.

A. Pipeline

CORDIC pipelined implementation uses the basic

CORDIC module described. If an iterative implementation
of CORDIC were used, the generator would take several
clock cycles to build a single output sample of the wave.
However, using pipeline converts iterations into pipeline
phases. In this way an output is obtained at every clock
cycle, after pipeline stages propagation. Each pipeline stage
takes exactly one clock cycle to complete. In Fig. 3,
registers are implicit between each stage.

One of the most recurrent problems for a CORDIC

implementation is overflow. It is mentioned in some
previous works [1],[6], but not solved. The risk is present Fig. 3. Pipelined CORDIC
when angles π/2 or -π /2 are reached. This is due to the fact
that the difference in binary representation between these
two angles is one bit. When approximation is being made,
an angle could cross from a positive right angle to a negative
one. Overflow is solved by adding an overflow control
which checks for the signs of the operands involved in
additions or substraction and the result of the operation.
When an overflow is produced, the result keeps its last sign;
this method does not affect the final result. For each stage,
the value arctan 2–i is taken from memory. In the overflow
control the sign of zi is used to determine di, so for each
stage di is applied as input to adders-subtractors to decide if
a sum or a subtraction is performed.

B. Angle Sequencer
Fig. 4. Angles Sequencer signal
CORDIC is a module which calculates sine and cosine
given an angle, so it is necessary to give it a sequence of Sawtooth wave is not useful by itself, it needs to be
angles in the range of CORDIC convergence. It is not a transformed into a triangle wave to feed the CORDIC
simple sequence of angles, but it must be able to change module. Triangle must represent the travel made on first and
frequency of the signal created by CORDIC. The module fourth quadrants. Sawtooth wave is transformed into triangle
wave by looking at two most significant bits because they TABLE I
indicate the current quadrant. When the two most significant SPEED OPTIMIZATION RESULTS
bits are 01 or 10, then the sawtooth signal must be
transformed. That is done by mean of inverting every single Parameter Used %
bit, without changing the sign bit (Fig. 4). This scheme had Number of Slices 1104 57
been previously explored by Norbert Lindlbauer [5] in a
Number of Flip Flops 615 16
sound synthesizer, but we have reduced one bit from the
Numer of 4 input LUTs 1748 45
sawtooth wave and applied quadrant correction on the fly.
Number of bonded IOBs 43 24
The speed of the sawtooth wave determines the frequency of Number of GCLKs 1 12
the sine and cosine waves. In fact, sine and cosine waves Maximum Frequency 154.69MHz
will have the same frequency than the triangle wave.

Let us denote with t the time in seconds which takes a TABLE II

AREA OPTIMIZATION RESULTS
cycle in the reference clock. CORDIC algorithm is able to
perform a maximum of 1/t Hz. As stated by Nyquist, the Parameter Used %
higher frequency for the output is (2t)-1 Hz. To establish a
relation between the increase value in sawtooth wave and Number of Slices 1075 55
output frequency, the following formula is used, having n as Number of Flip Flops 570 14
depth in bits. Let w be the increase value for the sawtooth Numer of 4 input LUTs 1737 44
wave; fr the reference clock frequency and fo the frequency Number of bonded IOBs 43 24
of output waves. w is expressed in terms of fr and fo in the Number of GCLKs 1 12
following way: Maximum Frequency 124.67MHz

w= (2n+1fr) / fo (17) Overflow and quadrant correction are CORDIC inherent

issues which had not been detailed in other related work. A
IV. RESULTS solution for them was presented and the implementation
results on a FPGA Xilinx Spartan 3 were presented and
All modules were written in VHDL and tested as discussed.
components, which were simulated on ModelSim. All
critical cases, such as high and low frequencies responses, AKNOWLEDGMENT
were tested. This was accomplished by testing the whole
angle sequencer's dynamic range. The full design was This work has been partially supported by CONACYT,
targeted to a Xilinx Spartan 3 xc3s200-5ft256, using Xilinx under grant number 201562.
ISE 7.1 to synthesize and implement the architecture. Speed
and area optimization were tested. Tables 1 and 2 show the REFERENCES
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