International Journal of Research and Development in Applied Science and Engineering (IJRDASE)

Implementation of N-Bit Divider using VHDL

Raghawendra Sharma Anurag Banoudha
M.Tech. Scholar, Guide,
S. V. U., Merut, U.P., India Electrical Engg.
[email protected] [email protected]

Abstract-Division is the inverse of multiplication, but it differs from therefore able to extrapolate our results to future process
multiplication in many aspects. The major difference is that division is technologies. While the discussion here is devoted to
a shift-and-subtract-divisor operation, while multiplication is a shift division, the theory of square root computation is an
and-add-multiplicand operation. The results of one subtraction
determine the next operation in a division sequence. Thus, division has extension of the theory of division. Accordingly, most of the
an inherent serial dependency. This problem does not occur in analyses presented here can also be applied to the design of
multiplication, because all summands are generated simultaneously. square root units.
Next, division is not a deterministic.
SRT dividers are common in modern floating point units. Higher
division performance is achieved by retiring more quotient bits in each 2 SRT Division:
cycle. Previous research has shown that realistic stages are limited to Performing division requires making a choice of quotient
radix-2 and radix-4. Higher radix dividers are therefore formed by a digits starting with the most significant, and progressing to
combination of low radix stages. In this paper, we present an analysis the least significant digits. The quotient digit decision is
of the n-bit divider and Comparative analysis of different dividers in
case of delays and performance. We show the performance and area made as a part of each iteration which recomputes the partial
results for a wide variety of divider architectures and implementations. remainder based on the last partial remainder and quotient
We conclude that divider performance is only weakly sensitive to digit. The complete quotient is accumulated from the
reasonable choices of architecture but significantly improved by equation:
restoring and non restoring techniques. -i
Q=∑ ir
Keywords-- Divider, Modelsim, SRT Algorithm, Xilinx where
r is the radix
Introduction: N is the number of quotient digits calculated
A simple and widely implemented class of division Q is the accumulated quotient result with a precision of r -(n-l)
algorithm is digit recurrence. The most common qi is the quotient digit determined from stage i
implementation of digit recurrence division in modern Since in binary hardware the full quotient result is easiest to
microprocessors is SRT division, taking its name from the form if it is merely the concatenation of the bits of the
initials of Sweeney, Robertson [1] and Tocher [2], who individual digits, we set the radix r = 2” where m is the
developed the algorithm independently at approximately the number of quotient bits determined at each stage.
same time. SRT division uses subtraction as the fundamental In irredundant division, the quotient digits are in the set (0, .
operator to retire a fixed number of quotient bits in every . . . r- l}, and the full quotient has only a single valid
iteration. Two fundamental works on SRT division are those representation since each digit position in the quotient has
of Atkins [3], the first major analysis of SRT algorithms, only a single correct possibility. Unfortunately, determining
and Tan [4], a derivation of high-radix SRT division and an the correct digit at each position requires comparison of the
analytic method of implementing SRT look-up tables. entire partial remainder, and this means that the entire partial
Ercegovac and Lang [5] provide a comprehensive treatment remainder must be computed before making each quotient
of the theory of SRT division and square root. Although digit selection. This computation requires a complete carry
division is typically an infrequent operation, ignoring its propagation along the length of the partial remainder before
implementation significantly degrades system performance each quotient digit may be selected [10]. These irredundant
for many applications. division schemes are much slower than multiplication
Various techniques have been proposed for increasing because multiplication does not require such a carry
division performance, including staging of simple low-radix propagation in order to compute partial results.
stages, overlapping sections of one stagewith another stage, A complete carry propagation in each iteration can be
and prescaling the input operands. All of these methods avoided by making the set of valid quotient digits redundant
introduce area-performance tradeoffs. Ercegovac and Lang by including both positive and negative integers. In this
[5] analyze the tradeoffs of using several of these method, the divisor and dividend must be normalized to the
optimizations in the context of static CMOS standard-cells. same binary range, and the valid quotient digits for a
Williams [8] presents a self-timed dynamic CMOS divider maximum quotient digit p are in the set {-p, . . . . 0, . . . . p}
comprising a ring of five radix-2 stages that incorporates which is symmetric about, and includes, zero. The quotient
several of these techniques, and he also presents an analysis digit chosen at each stage in the division determines the
of the performance and area effects of the architectural operation computing the next partial remainder according to
components. Prabhu [9] presents the tradeoffs encountered the equation:
when designing the Sun UltraSparc radix-8 divider. Ri+1 =rRi - Dqi
In contrast to previous works, this paper analyzes in detail where
the effects of both circuit style and divider architecture on Ri is the partial remainder output from stage i
the area and performance of divider implementations. We D is the Divisor
present the performance results using the technology and the sequence is initialized with
independent metric of fanout-of-4 inverter delay. We are rR0 = the Dividend
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 International Journal of Research and Development in Applied Science and Engineering (IJRDASE)

The vertical arrow "view" next to the button displays digits

3. Methodology: or bits or moves the decimal point right after the most
To avoid the delay of the carry propagation, the following significant digit of D as with a mantissa or after the least
applet uses a stack of borrow-save "BS" adders/subtractors. significant digit as with an integer.
The "tail" cell, variant of the "SC" and "AS" cells, is A "conditional adder/subtractor" outputs S from one of the
controlled by two bits and executes one of the three three following equations:
following operations:
an addition : Rj-1 = Rj + 2j-1 * D if q = '-1' then S = R + D ;
a subtraction : Rj-1 = Rj – 2j-1 * D if q = '0' then S = R ;
an identity : Rj-1 = Rj if q = '1' then S = R – D ;

This operation is selected according to the sign of the partial Each "tail" cell carries out a one-bit addition/subtraction.
remainders Rj. To always know precisely this sign would The carry is not propagated to the "tail" cell at left but fed
require the examination of all the remainder's digits. It down directly to the "tail" cell below (next row). The delay
suffices to check only three. Moreover, the position of the is independent from the number of digits.
three digits is known: the least significant one is aligned The "conditional adder/subtractor" function is abstracted by
with the most significant non-zero bits of D. To nail down its transfer function called "Robertson's diagram". To
this digit position, D is "normalized", that is the position of converge the division imposes moreover that -2*D R
its first '1' bit is fixed. Let us call this position 0 and 2*D. If - D R 2 then S has two possible values.
accordingly D's first bit d0. Thus d0= '1'. For an n-bit
divider, 2n-2–1 < D < 2n-1.

a a
a d a d a d d
4 3
0 1 0 0 0 0 0 0 0
0 a
0 2
Head Tai Tai Tai 0
a
0
Head Tai Tai Tai 0
a
0
Head Tai Tai Tai 0

0
Head Tai Tai Tai

0 0 0 0 0
Fig. 1. SRT divider

A. SRT division with divider range reduction: final remainder R is also multiplied. For an n-bit divider, 2n-
The previous division is simple because the fist bit d0 of the 1–1 < D < 2n-1 + 2n-2.
divider D is always '1'. It may be even further simplified if Let = r0 + r1* 0.5 be the "head" cell input value.
the two first bits d0 and d1 of the divider D are reduced to if > 0.5 then { s1 = – 1.5 ; q = '+1'; }
"1 0" thanks to the operation. if = 0.5 then { s1 = 0 ; q = '- 0' ; }
if = 0 then { s1 = 0 ; q = '+ 0' ; } or { s0 = - 0.5 ; q = '- 0' ;
if d0 then { D' = D*3/4 ; A' = A*3/4 } else { D' = D ; A' = }
A} if = - 0.5 then { s1 = - 0.5 ; q = '+ 0' ; }
This multiplication of both A and D by the same constant if < - 0.5 then { s1 = + 1 ; q = '-1' ; }
does not affect the quotient Q, but on the other hand the Here the difference between the two 0 representations for q :
'+ 0' and '- 0' matters.
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B. Quotient converter:
The quotient Q is in "BS" redundant notation. The
conversion into a conventional binary representation is
obtained thanks to an adder (in fact a subtractor). For the
subtraction, '0' gives 'P', '1' gives 'G' et '-1' gives 'K'. Since
the digits qj are obtained sequentially, most significant digit
first, the conversion can be carried out in parallel with the
quotient digits selection by the "head" cells.
Let "Ratio" be the "head" cell and "BK" cell delays ratio.
The higher this ratio, the more delay available thus the
simpler the converter. But the higher this ratio, the less delay
is gained by the concurrence of the converter.

4. Result and Discussion:

In case of 16-bit divider we took 16- bit dividend is Fig. 4. Simulation Result for 4 Bit Divider
“0000000010101010” and 16- bit divisor is In case of n-bit divider we took as a example 11- bit
“0000000000000010” then the reminder is
dividend is “01010101010” and 11- bit divisor is
“0000000000000000”. In fig 2 we have shown the
“00000000010” then the reminder is “00000000000”. In fig
simulation result fir 16-bit divider.
5 we have shown the simulation result fir n-bit divider.

Fig 2. Simulation Result for 16 Bit Divider

Fig. 5. Simulation Result for n Bit Divider
In case of 8-bit divider we took 8- bit dividend is
“10101010” and 8- bit divisor is “00000010” then the
reminder is “00000000”. In fig 3 we have shown the Table 1. Result Comparison
simulation result fir 8-bit divider.
Total
Logic Route Delay
Delay
Delay (ns) (ns)
Divider (ns)
4-Bit 7.508
5.753 1.755
Divider
8- Bit 7.085
5.753 1.332
Divider
16- Bit 7.319
5.753 1.566
Divider
n- Bit 8.903
6.302 2.601
Divider

5. Conclusion:
In 4-bit divider the logic delay is 5.753 ns and route delay is
Fig. 3. Simulation Result for 8 Bit Divider 1.755 ns then the total delay for 4-bit divider is 7.508 ns. In
case of 8-bit divider the logic delay is 5.753 ns and route
In case of 4-bit divider we took 4- bit dividend is “1010” delay is 1.332 ns then the total delay for 8-bit divider is
and 4- bit divisor is “0010” then the reminder is “0000”. In 7.085 ns. In case of 16-bit divider the logic delay is 5.753 ns
fig 4 we have shown the simulation result fir 4-bit divider. and route delay is 1.566 ns then the total delay for 16-bit
divider is 7.319 ns. In case of n-bit divider the logic delay is
6.302 ns and route delay is 2.601 ns then the total delay for
n-bit divider is 8.903 ns. If we look simply then we can say
that the total delay of n-bit divider is greater than rest of
Dividers but we can not decide which divider is required is
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 International Journal of Research and Development in Applied Science and Engineering (IJRDASE)

everywhere. So that if we required three different dividers

like 4, 8, 16-bit dividers then total delay will be 21.912 ns.
That is why we use n-bit divider in place of these different
dividers. Then the delay will be just 8.903 ns. This delay is
clearly less then from these all these dividers. Here we are
talking about just three dividers but practically we need
more bit dividers and more dividers.
So if we did not take n-bit divider then we has to design
many more different dividers for different bit. They will
defiantly take more time, area, power and also cost. But in
VLSI we have to save all of these. Then the result is n-bit
divider is taking less power, less area and reduce the cost.

References:
[1] J. E. Robertson, “A new class of digital divisionmethods,” IRE Trans.
Electronic Computers, vol. EC-7, pp. 218–222, Sept. 1958.
[2] K. D. Tocher, “Techniques of multiplication and division for automatic
binary computers,” Quart. J. Mech. Appl. Math., vol. 11, pt. 3, pp. 364–
384, 1958.
[3] D. E. Atkins, “Higher-radix division using estimates of the divisor and
partial remainders,” IEEE Trans. Computers, vol. C-17, no. 10, Oct. 1968.
[4] K. G. Tan, “The theory and implementation of highradix division,” in
Proc. 4th IEEE Symp. Computer Arithmetic, pp. 154–163, June 1978.
[5] M. D. Ercegovac and T. Lang, Division and Square Root: Digit-
Recurrence Algorithms and Implementations, Kluwer Academic Publishers,
1994.
[6] S. F. Oberman and M. J. Flynn, “Design issues in division and other
floating-point operations,” IEEE Trans. Computers, vol. 46, no. 2, pp. 154–
161, Feb. 1997.
[7] S. F. Oberman and M. J. Flynn, “Division algorithms and
implementations,” to appear in IEEE Trans. Computers, 1997.
[8] T. E.Williams and M. A. Horowitz, “A zero-overhead self-timed 160-ns
54-b CMOS divider,” IEEE J. Solid- State Circuits, vol. 26, no. 11, pp.
1651–1661, Nov. 1991.
[9] J. A. Prabhu and G. B. Zyner, “167 MHz radix-8 floating point divide
and square root using overlapped radix-2 stages,” in Proc. 12th IEEE Symp.
Computer Arithmetic, pp. 155–162, July 1995.
[10] Raghawendra Sharma, "Implementation of CORDIC based Processor
using VHDL" International Journal of Research and Development in
Applied Science and Engineering, Volume 2, Issue 1, March 2012.

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