Carnegie Mellon

Multi-cycle MIPS Processor

Design of Digital Circuits 2014

Srdjan Capkun
Frank K. Gürkaynak

http://www.syssec.ethz.ch/education/Digitaltechnik_14

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Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Harris ©2007 Elsevier
 Carnegie Mellon

What Will We Learn?

 What are the problems of Single-cycle Processor

 Multi-cycle Architecture for the MIPS

 Determine the performance of Multi-cycle Processor

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 Carnegie Mellon

Single-cycle MIPS Processor

 Single-cycle microarchitecture:
+ simple
- cycle time limited by longest instruction (lw)
- two adders/ALUs and two memories

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 Carnegie Mellon

Single-cycle Performance
MemtoReg
Control
MemWrite
Unit
Branch 0 0
ALUControl 2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK 1 0
010 1
25:21
WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
1 A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
0
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0 <<2
Sign Extend PCBranch

+
Result

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 Carnegie Mellon

Delay of Individual Components (Example)

Element Parameter Delay (ps)
Register clock-to-Q tpcq_PC 30
Register setup tsetup 20
Multiplexer tmux 25
ALU tALU 200
Memory read tmem 250
Register file read tRFread 150
Register file setup tRFsetup 20

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 Carnegie Mellon

Processor Performance
 How fast is my program?
 Every program consists of a series of instructions
 Each instruction needs to be executed.

 So how fast are my instructions ?

 Instructions are realized on the hardware
 They can take one or more clock cycles to complete
 Cycles per Instruction = CPI

 How much time is one clock cycle?

 The critical path determines how much time one cycle requires =
clock period.
 1/clock period = clock frequency = how many cycles can be done
each second.

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 Carnegie Mellon

Processor Performance
 Now as a general formula
 Our program consists of executing N instructions.
 Our processor needs CPI cycles for each instruction.
 The maximum clock speed of the processor is f,
and the clock period is therefore T=1/f

 Our program will execute in

N x CPI x (1/f) = N x CPI x T seconds

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 Carnegie Mellon

How can I Make the Program Run Faster?

N x CPI x (1/f)
 Reduce the number of instructions
 Make instructions that ‘do’ more (CISC)
 Use better compilers

 Use less cycles to perform the instruction

 Simpler instructions (RISC)
 Use multiple units/ALUs/cores in parallel

 Increase the clock frequency

 Find a ‘newer’ technology to manufacture
 Redesign time critical components
 Adopt pipelining
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 Carnegie Mellon

Multi-cycle MIPS Processor

 Single-cycle microarchitecture:
+ simple
- cycle time limited by longest instruction (lw)
- two adders/ALUs and two memories

 Multi-cycle microarchitecture:
+ higher clock speed
+ simpler instructions run faster
+ reuse expensive hardware on multiple cycles
- sequencing overhead paid many times

 Same design steps: datapath & control

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 Carnegie Mellon

What Do We Want To Optimize

 Single Cycle Architecture uses two memories
 One memory stores instructions, the other data
 We want to use a single memory (Smaller size)

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 Carnegie Mellon

What Do We Want To Optimize

 Single Cycle Architecture uses two memories
 One memory stores instructions, the other data
 We want to use a single memory (Smaller size)

 Single Cycle Architecture needs three adders

 ALU, PC, Branch address calculation
 We want to use the ALU for all operations (smaller size)

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 Carnegie Mellon

What Do We Want To Optimize

 Single Cycle Architecture uses two memories
 One memory stores instructions, the other data
 We want to use a single memory (Smaller size)

 Single Cycle Architecture needs three adders

 ALU, PC, Branch address calculation
 We want to use the ALU for all operations (smaller size)

 In Single Cycle Architecture all instructions take one cycle

 The most complex operation slows down everything!
 Divide all instructions into multiple steps
 Simpler instructions can take fewer cycles (average case may be
faster)

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 Carnegie Mellon

Consider lw instruction
 For an instruction such as: lw $t0, 0x20($t1)

 We need to:
 Read the instruction from memory
 Then read $t1 from register array
 Add the immediate value (0x20) to calculate the memory address
 Read the content of this address
 Write to the register $t0 this content

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 Carnegie Mellon

Multi-cycle Datapath: instruction fetch

 First consider executing lw
 STEP 1: Fetch instruction

IRWrite

CLK CLK
CLK CLK
WE WE3
PC' PC Instr A1 RD1
b A
RD
A2 RD2
EN
Instr / Data
Memory A3
Register
WD
File
WD3

read from the memory location [rs]+imm to location [rt]

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: lw register read

IRWrite

CLK CLK CLK

CLK CLK
WE 25:21 WE3 A
PC' PC Instr A1 RD1
b A
RD
A2 RD2
EN
Instr / Data
Memory A3
Register
WD
File
WD3

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: lw immediate

IRWrite

CLK CLK CLK

CLK CLK
WE 25:21 WE3 A
PC' PC Instr A1 RD1
b A
RD
A2 RD2
EN
Instr / Data
Memory A3
Register
WD
File
WD3

SignImm
15:0
Sign Extend

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: lw address

IRWrite ALUControl2:0

CLK CLK CLK

CLK CLK
WE WE3 A SrcA CLK
25:21
PC' PC Instr A1 RD1
b RD

ALU
A EN A2 RD2 ALUResult ALUOut
Instr / Data SrcB
Memory A3
Register
WD
File
WD3

SignImm
15:0
Sign Extend

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: lw memory read

IorD IRWrite ALUControl2:0

CLK CLK CLK

CLK CLK
WE WE3 A SrcA CLK
25:21
PC' PC Instr A1 RD1
b 0 Adr RD

ALU
A EN A2 RD2 ALUResult ALUOut
1
Instr / Data SrcB
Memory CLK A3
Register
WD
Data File
WD3

SignImm
15:0
Sign Extend

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: lw write register

IorD IRWrite RegWrite ALUControl2:0

CLK CLK CLK

CLK CLK
WE WE3 A SrcA CLK
25:21
PC' PC Instr A1 RD1
b 0 RD

ALU
Adr ALUResult ALUOut
A EN A2 RD2
1
Instr / Data SrcB
Memory 20:16
CLK A3
Register
WD
Data File
WD3

SignImm
15:0
Sign Extend

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
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 Carnegie Mellon

Multi-cycle Datapath: increment PC

PCWrite IorD IRWrite RegWrite ALUSrcA ALUSrcB1:0 ALUControl2:0

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A CLK
25:21
PC' PC Instr A1 RD1 1
b 0 RD

ALU
Adr ALUResult ALUOut
EN A EN A2 RD2 00
1 SrcB
Instr / Data 4 01
Memory 20:16
CLK A3 10
Register
WD 11
Data File
WD3

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Multi-cycle Datapath: sw
 Write data in rt to memory

PCWrite IorD MemWrite IRWrite RegWrite ALUSrcA ALUSrcB1:0 ALUControl2:0

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A CLK
25:21
PC' PC Instr A1 RD1 1
b 0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00
1
Instr / Data 4 01 SrcB
Memory 20:16
CLK A3 10
Register
WD 11
Data File
WD3

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Multi-cycle Datapath: R-type Instructions

 Read from rs and rt
 Write ALUResult to register file
 Write to rd (instead of rt)
PCWrite IorD MemWrite IRWrite RegDst MemtoReg RegWrite ALUSrcA ALUSrcB1:0 ALUControl2:0

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A CLK
25:21
PC' PC Instr A1 RD1 1
b 0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00
1
Instr / Data 20:16 4 01 SrcB
0
Memory 15:11 A3 10
CLK 1 Register
WD 11
0 File
Data WD3
1

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Multi-cycle Datapath: beq

 Determine whether values in rs and rt are equal
 Calculate branch target address:
BTA = (sign-extended immediate << 2) + (PC+4)
PCEn
IorD MemWrite IRWrite RegDst MemtoReg RegWrite ALUSrcA ALUSrcB1:0 ALUControl2:0 Branch PCWrite PCSrc

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A Zero CLK
25:21
PC' PC Instr A1 RD1 1 0
b 0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1
Instr / Data 20:16
4 01 SrcB
0
Memory 15:11
A3 10
CLK 1 Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Complete Multi-cycle Processor

CLK
PCWrite
Branch PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK
CLK CLK
0 SrcA
WE WE3 A Zero CLK
25:21
PC' PC Instr A1 RD1 1 0
0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1
Instr / Data 20:16 4 01 SrcB
0
Memory 15:11 A3 10
CLK 1 Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Control Unit
Control
MemtoReg
Unit
RegDst
IorD Multiplexer
PCSrc Selects
Main ALUSrcB1:0
Controller
Opcode5:0 (FSM) ALUSrcA
IRWrite
MemWrite
Register
PCWrite
Enables
Branch
RegWrite

ALUOp1:0

ALU
Funct5:0 ALUControl2:0
Decoder

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 Carnegie Mellon

Main Controller FSM: Fetch

S0: Fetch

Reset

CLK
PCWrite 1
Branch 0 PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK 0
CLK 0 CLK 0
0 SrcA 010
0 WE WE3 A Zero CLK 0
25:21
PC' PC Instr A1 RD1 1 0
0 RD 01

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1 X
Instr / Data 1 20:16 4 01 SrcB
1 0
Memory 15:11 A3 10
CLK 1 X Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Main Controller FSM: Fetch

S0: Fetch
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

CLK
PCWrite 1
Branch 0 PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK 0
CLK 0 CLK 0
0 SrcA 010
0 WE WE3 A Zero CLK 0
25:21
PC' PC Instr A1 RD1 1 0
0 RD 01

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1 X
Instr / Data 1 20:16 4 01 SrcB
1 0
Memory 15:11 A3 10
CLK 1 X Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Main Controller FSM: Decode

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

CLK
PCWrite 0
Branch 0 PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK X
CLK 0 CLK 0
0 SrcA XXX
X WE WE3 A Zero CLK X
25:21
PC' PC Instr A1 RD1 1 0
0 RD XX

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1 X
Instr / Data 0 20:16 4 01 SrcB
0 0
Memory 15:11 A3 10
CLK 1 X Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Main Controller FSM: Address Calculation

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

Op = LW
or
S2: MemAdr Op = SW CLK
PCWrite 0
Branch 0 PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK 1
CLK 0 CLK 0
0 SrcA 010
X WE WE3 A Zero CLK X
25:21
PC' PC Instr A1 RD1 1 0
0 RD 10

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1 X
Instr / Data 0 20:16 4 01 SrcB
0 0
Memory 15:11 A3 10
CLK 1 X Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Main Controller FSM: Address Calculation

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

Op = LW
or
S2: MemAdr Op = SW CLK
PCWrite 0
Branch 0 PCEn
ALUSrcA = 1 IorD Control PCSrc
ALUSrcB = 10 MemWrite Unit ALUControl2:0
ALUOp = 00 IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK 1
CLK 0 CLK 0
0 SrcA 010
X WE WE3 A Zero CLK X
25:21
PC' PC Instr A1 RD1 1 0
0 RD 10

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1 X
Instr / Data 0 20:16 4 01 SrcB
0 0
Memory 15:11 A3 10
CLK 1 X Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

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 Carnegie Mellon

Main Controller FSM: lw

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

Op = LW
or
S2: MemAdr Op = SW

ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00

Op = LW
S3: MemRead

IorD = 1

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Main Controller FSM: sw

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

Op = LW
or
S2: MemAdr Op = SW

ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00

Op = SW
Op = LW
S5: MemWrite
S3: MemRead

IorD = 1
IorD = 1
MemWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Main Controller FSM: R-Type

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite

Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute

ALUSrcA = 1 ALUSrcA = 1
ALUSrcB = 10 ALUSrcB = 00
ALUOp = 00 ALUOp = 10

Op = SW
Op = LW S7: ALU
S5: MemWrite
Writeback
S3: MemRead

RegDst = 1
IorD = 1
IorD = 1 MemtoReg = 0
MemWrite
RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Main Controller FSM: beq

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
PCSrc = 0 ALUOp = 00
IRWrite
PCWrite
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute
S8: Branch
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
ALUOp = 00 ALUOp = 10 PCSrc = 1
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite
Writeback
S3: MemRead

RegDst = 1
IorD = 1
IorD = 1 MemtoReg = 0
MemWrite
RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Complete Multi-cycle Controller FSM

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
PCSrc = 0 ALUOp = 00
IRWrite
PCWrite
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute
S8: Branch
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
ALUOp = 00 ALUOp = 10 PCSrc = 1
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite
Writeback
S3: MemRead

RegDst = 1
IorD = 1
IorD = 1 MemtoReg = 0
MemWrite
RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Main Controller FSM: addi

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
PCSrc = 0 ALUOp = 00
IRWrite
PCWrite
Op = ADDI
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute S9: ADDI
S8: Branch
Execute
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
ALUOp = 00 ALUOp = 10 PCSrc = 1
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite S10: ADDI
Writeback
S3: MemRead Writeback

RegDst = 1
IorD = 1
IorD = 1 MemtoReg = 0
MemWrite
RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Main Controller FSM: addi

S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
PCSrc = 0 ALUOp = 00
IRWrite
PCWrite
Op = ADDI
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute S9: ADDI
S8: Branch
Execute
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00 ALUSrcA = 1
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01 ALUSrcB = 10
ALUOp = 00 ALUOp = 10 PCSrc = 1 ALUOp = 00
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite S10: ADDI
Writeback
S3: MemRead Writeback

RegDst = 1 RegDst = 0
IorD = 1
IorD = 1 MemtoReg = 0 MemtoReg = 0
MemWrite
RegWrite RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Extended Functionality: j

PCEn
IorD MemWrite IRWrite RegDst MemtoReg RegWrite ALUSrcA ALUSrcB1:0 ALUControl2:0 Branch PCWrite PCSrc1:0

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A 31:28 Zero CLK
25:21
PC' PC Instr A1 RD1 1 00
0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 01
1
Instr / Data 20:16 4 01 SrcB 10
0
Memory 15:11 A3 10
CLK 1 Register PCJump
WD 11
0 File
Data WD3
1
<<2 27:0
<<2

SignImm
15:0
Sign Extend
25:0 (jump)

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 Carnegie Mellon

Control FSM: j
S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0 S11: Jump
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11 Op = J
PCSrc = 00 ALUOp = 00
IRWrite
PCWrite
Op = ADDI
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute S9: ADDI
S8: Branch
Execute
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00 ALUSrcA = 1
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01 ALUSrcB = 10
ALUOp = 00 ALUOp = 10 PCSrc = 01 ALUOp = 00
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite S10: ADDI
Writeback
S3: MemRead Writeback

RegDst = 1 RegDst = 0
IorD = 1
IorD = 1 MemtoReg = 0 MemtoReg = 0
MemWrite
RegWrite RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Control FSM: j
S0: Fetch S1: Decode
IorD = 0
Reset AluSrcA = 0 S11: Jump
ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11 Op = J
PCSrc = 00 ALUOp = 00 PCSrc = 10
IRWrite PCWrite
PCWrite
Op = ADDI
Op = BEQ
Op = LW
or Op = R-type
S2: MemAdr Op = SW
S6: Execute S9: ADDI
S8: Branch
Execute
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00 ALUSrcA = 1
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01 ALUSrcB = 10
ALUOp = 00 ALUOp = 10 PCSrc = 01 ALUOp = 00
Branch

Op = SW
Op = LW S7: ALU
S5: MemWrite S10: ADDI
Writeback
S3: MemRead Writeback

RegDst = 1 RegDst = 0
IorD = 1
IorD = 1 MemtoReg = 0 MemtoReg = 0
MemWrite
RegWrite RegWrite

S4: Mem
Writeback

RegDst = 0
MemtoReg = 1
RegWrite
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 Carnegie Mellon

Multi-cycle Performance
 Instructions take different number of cycles:
 3 cycles: beq, j
 4 cycles: R-Type, sw, addi
 5 cycles: lw

 CPI is weighted average, i.e. SPECINT2000 benchmark:

 25% loads
 10% stores
 11% branches
 2% jumps
 52% R-type

 Average CPI = (0.11 + 0.02) 3 +(0.52 + 0.10) 4 +(0.25) 5

= 4.12
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 Carnegie Mellon

Multi-cycle Performance
 Multi-cycle critical path:

Tc =
CLK
PCWrite
Branch PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct
MemtoReg
RegDst

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A Zero CLK
25:21
PC' PC Instr A1 RD1 1 0
0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1
Instr / Data 20:16 4 01 SrcB
0
Memory 15:11 A3 10
CLK 1 Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

42
 Carnegie Mellon

Multi-cycle Performance
 Multicycle critical path:

Tc = tpcq + tmux + max(tALU + tmux, tmem) + tsetup

CLK
PCWrite
Branch PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct
MemtoReg
RegDst

CLK CLK CLK

CLK CLK
0 SrcA
WE WE3 A Zero CLK
25:21
PC' PC Instr A1 RD1 1 0
0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 1
1
Instr / Data 20:16 4 01 SrcB
0
Memory 15:11 A3 10
CLK 1 Register
WD 11
0 File
Data WD3
1
<<2

SignImm
15:0
Sign Extend

43
 Carnegie Mellon

Multicycle Performance Example

Element Parameter Delay (ps)
Register clock-to-Q tpcq_PC 30
Register setup tsetup 20
Multiplexer tmux 25
ALU tALU 200
Memory read tmem 250
Register file read tRFread 150
Register file setup tRFsetup 20

Tc =

44
 Carnegie Mellon

Multicycle Performance Example

Element Parameter Delay (ps)
Register clock-to-Q tpcq_PC 30
Register setup tsetup 20
Multiplexer tmux 25
ALU tALU 200
Memory read tmem 250
Register file read tRFread 150
Register file setup tRFsetup 20

Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup

= [30 + 25 + 250 + 20] ps
= 325 ps
45
 Carnegie Mellon

Multi-cycle Performance Example

 For a program with 100 billion instructions executing on a
multi-cycle MIPS processor
 CPI = 4.12
 Tc = 325 ps

 Execution Time = (# instructions) × CPI × Tc

= (100 × 109)(4.12)(325 × 10-12)
= 133.9 seconds

 This is slower than the single-cycle processor (92.5 seconds).

Why?

46
 Carnegie Mellon

Multi-cycle Performance Example

 For a program with 100 billion instructions executing on a
multi-cycle MIPS processor
 CPI = 4.12
 Tc = 325 ps

 Execution Time = (# instructions) × CPI × Tc

= (100 × 109)(4.12)(325 × 10-12)
= 133.9 seconds

 This is slower than the single-cycle processor (92.5 seconds).

Why?
 Not all steps the same length
 Sequencing overhead for each step (tpcq + tsetup= 50 ps)

47
 Carnegie Mellon

Review: Single-Cycle MIPS Processor

Jump MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
0 25:21
WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0 Result
1 A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
PCJump 15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
27:0 31:28

25:0
<<2

48
 Carnegie Mellon

Review: Multicycle MIPS Processor

CLK
PCWrite
Branch PCEn
IorD Control PCSrc
MemWrite Unit ALUControl2:0
IRWrite ALUSrcB1:0
31:26 ALUSrcA
Op
5:0 RegWrite
Funct

MemtoReg
RegDst
CLK CLK CLK
CLK CLK
0 SrcA
WE WE3 A 31:28 Zero CLK
25:21
PC' PC Instr A1 RD1 1 00
0 RD

ALU
Adr 20:16 B ALUResult ALUOut
EN A EN A2 RD2 00 01
1
Instr / Data 20:16 4 01 SrcB 10
0
Memory 15:11 A3 10
CLK 1 Register PCJump
WD 11
0 File
Data WD3
1
<<2 27:0
<<2

ImmExt
15:0
Sign Extend
25:0 (Addr)

49
 Carnegie Mellon

What Have We Learned?

 A more ‘realistic’ architecture
 Shared data and program memory
 A single ALU for all operations

 Multi-cycle: Operations take different number of cycles

 Simpler operations take less steps
 More complex operations take more steps
 Average CPI

 Bottom line
 Smaller
 More complex control
 Not necessarily faster (overhead)
50