8051 Architecture Programming

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The 8051 Architecture and Programming

Supratim Gupta
Learning Methodology

 Hardware Information
• Internal architecture of the processor (8085, 8086,
8051 etc.)
• Internal architecture of peripheral interface
controller (viz. 8255, 8251, 8253, 8237, 8259 etc.)
• Circuit connections of the processor & peripheral
devices (like connection among components in a
PCB)

 Software Instructions
• Complex Instruction Set Computer (CISC)
• Reduced Instruction Set Computer (RISC)
Learning Methodology
8085 8051
Internal Architecture Internal Architecture
 Registers  Registers
• PSW, A • PSW, A
• B, C • B
• D, E • Special Function Registers (like
• H, L TMOD, TCON, IP, IE etc.)
• Program Counter, • Program Counter,
• Stack Pointer • Stack Pointer
 Memory: ROM, RAM
External Components
 Peripheral I/O Controller
 Memory: ROM, RAM
• Parallel: Port (P0 – P3)
 Peripheral I/O Controller
• Serial: P3.0, P3.1
• Parallel: 8255
• Interrupt: P3.2, P3.3
• Serial: 8251
• Timer: T0, T1, T2
• Interrupt: 8259
• SPI: P1.4 – P1.7
• Interval Timer: 8253/54
• DMA: 8237 External Components
 Peripheral Devices  Peripheral Devices
• ADC, DAC • ADC, DAC
• Keyboard • Keyboard
• Display: 7-Segment, LCD etc. • Display: 7-Segment, LCD etc.
• …Many more • …Many more
8051 Architecture

Specific Features
1. 8-bit CPU with registers A (accumulator) and B
2. 16-bit program counter (PC) and data pointer (DPTR)
3. 8-bit program status word (PSW)
4. 8-bit stack pointer (SP)
5. Internal ROM or EPROM of 4k (8051)
6. Internal RAM of 128 bytes
• 4 register banks each containing 8 registers of 8-bit
• 16-bytes bit addressable registers
• 80 bytes general purpose data memory
Cntd…
8051 Architecture

Specific Features

7. 32 input-output pins arranged as 4 eight-bit ports (P0 – P3)


8. 3 16 bit timer/counters : T0, T1, & T2
9. Full duplex serial data receiver/transmitter
10. Control registers : TCON, TMOD, SCON, PCON, IP, and IE, T2CON, T2MOD
11. 2 external and 3 timer interrupt and 1 serial interrupt sources
12. Oscillator and clock circuit
8051 Package: AT89S8253
Cntd…
8051 Programming Model
8 D0* 8 E0* 8 F0* 8 98* 8 99 8 C9
0FFF
PSW A B SCON SBUF T2MOD

8 B8* 8 A8* 8 89 8 88* 8 87 8 C8*

………………………………………
IP IE TMOD TCON PCON T2CON

8 8C 8 8A 8 8D 8 8B 8 C8*
7F
General
TH0 TL0 TH1 TL1 T2CON
30 Purpose
2F
Bit Add. Area 8 CD 8 CC 8 CB 8 CA 8 81
20
1F TH2 TL2
18 Bank 3 RCAP2H RCAP2L SP
17
10 Bank 2
0F 8 83 8 82
08 Bank 1 16 No Address
07 R7 DPH DPL
R6 PC
Data Pointer
R5
R4
R3 8 80* 90* 8 A0* 8 B0* 0000
R2
R1 P0 Latch P1 Latch P2 Latch P3 Latch
00 R0 Internal ROM
Internal RAM * => bit addressable
Special Function Registers: AT89S51
Special Function Registers: AT89S8253
Basic Operation Configuration

Power on RESET V = 5V
PC points 0 location
of ROM after
Oscillator is 1 μF
stabilized and
removes the start
up uncertainty

11.059 MHz 33 pF

33 pF
Crystal Oscillator Connection

 Using a quartz crystal oscillator


 We can observe the frequency on the XTAL2 pin.

C2
XTAL2
33pF

33pF
C1
XTAL1

GND

External Clock Drive Configuration


RESET Value of Some 8051 Registers

Register Reset Value


PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero
Port Configuration
A Pin of Port 1

Read latch Vcc


TB2
Load(L1)

Internal CPU D Q P1.X


bus pin
P1.X
Write to latch Clk Q M1

TB1
Read pin P1.x
A Pin of Port 0

Read latch
TB2

Internal CPU D Q P0.X


bus pin
P0.X
Write to latch Clk Q M1

TB1
Read pin P0.x
Interrupts
Interrupt Sources
Interrupt Vector Address

Interrupt Source Vector Address

System Reset RST / Power On Reset 0000H

External Interrupt 0 IE0 0003H

Timer 0 Overflow TF0 000BH

External Interrupt 1 IE1 0013H

Timer 1 Overflow TF1 001BH

Serial Port RI + TI 0023H

Timer 2 Overflow TF2 + EXF2 002BH


Special Function Register: Interrupt Enable
Special Function Register: Interrupt Priority
Special Function Register: Interrupt Priority
Timer Interrupts
Timer Interrupts

 Timer 0 & 1
• 16-bit timers/counters.
• These can be independently configured to operate in a variety of modes as a
timer or as an event counter.
• In timer mode, it runs for a programmed length of time, then
issues an interrupt request.
• In counter mode, it counts negative transitions on an external pin; after a pre-
set number of counts, the counter issues an interrupt request.

 Timer 2

• 16-bit timer/counter which is present in most of the Atmel 8051 microcontrollers.


• The count is maintained by two 8-bit timer registers, TH2 and TL2, that are
cascade connected. Like Timers 0 and 1, it can operate either as a timer or as an
event counter.
TMOD Register

Timer 1 Timer 0

 Gate : When set, timer only runs while INT(0,1) is high.


 C/T : Counter/Timer select bit. 0 to set it in timer mode
 M1 : Mode bit 1.
 M0 : Mode bit 0.
TCON Register

 TF1: Timer 1 overflow flag.


 TR1: Timer 1 run control bit.
 TF0: Timer 0 overflag.
 TR0: Timer 0 run control bit.
 IE1: External interrupt 1 edge flag.
 IT1: External interrupt 1 type flag.
 IE0: External interrupt 0 edge flag.
 IT0: External interrupt 0 type flag.
Timer 0/1 in Mode 0: 13-bit

Timer 1 Timer 0

÷ 12

Internal Architecture for Mode 0 of Timer 0/1


Timer 0/1 in Mode 1:16-bit

Timer 1 Timer 0

÷ 12

Internal Architecture for Mode 1 of Timer 0/1


Timer 0/1 in Mode 2: Auto-Reload

Timer 1 Timer 0

÷ 12

Internal Architecture for Mode 2 of Timer 0/1


Timer 0 in Mode 3: Split

÷ 12

÷ 12

Internal Architecture for Mode 3 of Timer 0

Note:
 Mode 3 is ‘hold count’ mode for Timer 1
 Timer 1 can be used for Baud Rate generation for serial communication
when T0 is in mode 3
Timer Interrupt Generation

Oscillator To
Frequency ÷12 Timer/Counter
(fosc) circuit

Interrupt Interval:
12d
t  Rmax 1 Rmin d 
f osc
Rmax = FFFF (for 16-bit mode)
= FF (for 8-bit mode)
Rmin = User settable
Timer Interrupt Enable

IE register
Timer 2: Control Registers
Timer 2: Control Registers
Timer 2: Operating Modes
Timer 2: Capture Mode
Timer 2: 16-bit Auto-reload Mode

DCEN = 0: Up Counter
Timer 2: 16-bit Auto-reload Mode

DCEN = 1: Up or Down Counter


Timer 2: Baud Rate Generator Mode
Timer 2: Programmable Clock Out
Programming the 8051
Part-1: Instruction Set
by
Dr. Supratim Gupta
Instruction Set: Legends

Notation Description
Rn Register R0-R7 of the currently selected Register bank
Direct 8-bit internal data location’s address. This could be an
Internal Data RAM location (0-127) or a SFR (i.e. I/O port,
control register, status register, etc. (128 -255)
@Ri 8-bit internal data RAM location addressed indirectly through
register R0 & R1
#data 8-bit constant included in the instruction
#data 16 16-bit constant included in the instruction
addr 16 16-bit destination address used by LCAL, LJMP. A branch
can be anywhere within the 64-K byte Program Memory
address space

43
Instruction Set: Legends

Notation Description
addr 11 11-bit destination address used by ACAL, AJMP. A branch
can be within the same 2-K byte page of Program Memory as
the first byte of the following instruction
rel Signed (two’s complement) 8-bit offset byte. Used by SJMP
and all conditional jumps. Range is -128 to +127 bytes
relative to first byte of the following instruction
bit Direct address bit of internal data RAM of SFR

44
Instruction Set: DATA Transfer

Number Oscillator
Mnemonic Description Hex Code Affected flags
of Bytes Period

MOV A, Rn Move Register to Accumulator 1 12 E8 to EF (R0 to R7)

Move content of the address


MOV A, direct given by direct byte to 2 12 E5
Accumulator
Move indirect RAM to
MOV A, @Ri 1 12 E6,E7 (@R0,@R1)
Accumulator
Move immediate data to
MOV A, #data 2 12 74
Accumulator
No flag
MOV Rn, A Move Accumulator to register 1 12 F8 to FF (R0 to R9) affected
Move content of the address
MOV Rn, direct given by direct byte to 2 24 A8 to AF (R0 to R9)
register
Move immediate data to
MOV Rn, #data 2 12 78 to 7F (R0 to R9)
register
Move Accumulator content to
MOV direct, A the address given by direct 2 12 F5
byte
45
Instruction Set: DATA Transfer

Number Oscillator Affected


Mnemonic Description Hex Code
of Bytes Period flags

Move register byte to the


MOV direct, Rn 2 24 88 to 8F (R0 to R9)
address given by direct byte
Move the content of the
MOV direct, direct address given by direct byte to 3 24 85
the direct byte
Move indirect RAM to the No flag
MOV direct, @Ri 2 24 86,87 (@R0,@R1)
address given by direct byte effected
Move immediate data to the
MOV direct, #data address given by the direct 3 24 75
byte
Move Accumulator to indirect
MOV @Ri, A 1 12 F2,F3(@R0,@R1)
RAM
46
MOV B, #data Move immediate data to B 2 12
Instruction Set: DATA Transfer

Mnemonic Number Oscillator


Description Hex Code Affected Flags
of Bytes period
Move content of the
MOV @Ri, direct address given by
2 24 76,77 No Flag
direct byte to indirect
RAM

MOV @Ri, #data Move immediate data 78-7F (depending on No Flag


2 12
to indirect RAM different registers)

MOV DPTR, #data16 Load data pointer with No Flag


3 24 90
a 16 bit constant

Move code byte


MOVC A, @A+DPTR
relative to DPTR to 1 24 93 No Flag
Accumulator

Move code byte


MOVC A, @A+PC No Flag
relative to PC to 1 24 83
Accumulator
47
Instruction Set: DATA Transfer

Mnemonic Oscillator Affected


Description Byte Hex Code
period Flags

MOVX A, @Ri Move external RAM


1 24 E2, E3 No Flag
(8-bit address) to Acc

MOVX A, @DPTR Move external RAM No Flag


1 24 E0
(16-bit address) to Acc

MOVX @Ri, A Move Acc to external No Flag


1 24 F2, F3
RAM (8-bit address)

MOVX @DPTR, A Move Acc to external


48
1 24 F0 No Flag
RAM (16-bit address)
Instruction Set: DATA Transfer

Mnemonic Oscillator Affected


Description Byte Hex Code
period Flags
Push content of the
PUSH direct address given by direct 2 24 C0 No Flag
byte on to stack
Pop content of the address
No Flag
POP direct given by direct byte from 2 24 D0
stack

XCH A, Rn Exchange register with C8-CF (depending on No Flag


1 12
accumulator different registers)

Exchange content of the


XCH A, direct address given by direct 2 12 C5 No Flag
byte with accumulator

Exchange indirect RAM No Flag


XCH A, @Ri 1 12 C6, C7
with accumulator

Exchange low-order digit


XCHD A, @Ri No Flag
indirect RAM with 1 12 D6, D7
accumulator
49
Addressing modes

Immediate: MOV A, #20H (8-bit data); MOV B, #120 (Decimal Data)

Register: MOV A, B; MOV A, Rn; n = 0,1,2,….,7

Direct: MOV A, 2000H ( Content at 2000H address -> A);

Indirect: MOV A, @Ri (Memory → A) ; I = 0, 1

Index Mode: Address of operand in memory is generated by adding base-address and a offset or
displacement

TABLE: MOVC A, @A + PC
RET
DB 06 09 21 23

50
Instruction Set: Arithmetic operations

Number
Oscillator Affected
Mnemonic Description of Bytes Hex Code
Period flags

Add Register to
ADD A, Rn 1 12 28 to 2F (R0 to R9)
Accumulator
Add content of the address
ADD A, direct given by direct byte to 2 12 25
Accumulator C ,OV, AC
Add indirect RAM to
ADD A, @Ri 1 12 26,27(@R0,@R1)
Accumulator
Add immediate data to
ADD A, #data 2 12 24
Accumulator
Add register to
ADDC A, Rn 1 12 38 to 3F (R0 to R9)
Accumulator with carry
Add content of the address
ADDC A, direct given by direct byte to 2 12 35
Accumulator with carry 51
C,OV,AC
Add indirect RAM to
ADDC A, @Ri 1 12 36,37(@R0, @R1)
Accumulator with carry
Add immediate data to
ADDC A, #data 2 12 34
Accumulator with carry
Instruction Set: Arithmetic operations

Oscillator
Mnemonic Description Number of Bytes Hex Code
Period
Subtract register from
SUBB A, Rn 1 12 98 to 9F (R0 to R9)
Accumulator with borrow
Subtract content of the address
SUBB A, direct given by direct byte from 2 12 95
Accumulator with borrow
Subtract indirect RAM from
SUBB A, @Ri 1 12 96, 97(R0,R1)
Accumulator with borrow

Subtract immediate data from


SUBB A, #data 2 12 94
Accumulator with borrow

52
Instruction Set: Arithmetic operations

Number
Oscillator Affected
Mnemonic Description of Bytes Hex Code
Period flags

No flag
INC DPTR Increment Data Pointer 1 24 A3
affected
MUL AB Multiply A & B 1 48 A4 C=0,OV

DIV AB Divide A by B 1 48 84 C=0,OV

Decimal Adjust
DA A 1 12 D4 C
Accumulator

53
Instruction Set: Arithmetic operations

Number of Oscillator
Mnemonic Description Hex Code Flags affected
Bytes Period
INC A Increment Accumulator 1 12 04

INC Rn Increment register 1 12 08 to 0F (R0 to R7)


Increment content of the
INC direct address given by direct 2 12 05
byte
Increment direct RAM 06 , 07 (R0,R1)
INC @Ri 1 12

No flag
DEC A Decrement Accumulator 1 12 14
affected

DEC Rn Decrement Register 1 12 18 to 1F

Decrement content of the


DEC direct address given by direct 2 12 15 54
byte

DEC @Ri Decrement indirect RAM 1 12 16 to 17


Instruction Set: Logical operations

Number Oscillato
Mnemonic Description Hex Code Affected flags
of Bytes r Period
AND Register to 58 to 5F (R0 to
ANL A, Rn 1 12
Accumulator R9)
AND content of the address
ANL A, direct given by direct byte to 2 12 55
Accumulator

AND indirect RAM to 56,57(@R0,@R


ANL A, @Ri 1 12
Accumulator 1)
No flag affected
AND immediate data to
ANL A, #data 2 12 54
Accumulator

AND Accumulator to
ANL direct, A content of the address 2 12 52
given by direct byte
AND immediate data to 55
ANL direct, #data content of the address 3 24 53
given by direct byte
Instruction Set: Logical operations

Number Oscillator
Mnemonic Description Hex Code Affected flags
of Bytes Period

OR Register to
ORL A, Rn 1 12 48 to 4F ( R0 to R9)
Accumulator
OR content of the address
ORL A, direct given by direct byte to 2 12 45
Accumulator

OR indirect RAM to
ORL A, @Ri 1 12 46,47 (@R0,@Ri)
Accumulator
No flag affected
OR immediate data to
ORL A, #data 2 12 44
Accumulator

OR Accumulator to
ORL direct, A content of the address 2 12 42
given by direct byte
OR immediate data to
ORL direct, #data content of the address 3 24 43
given by direct byte
56
Instruction Set: Logical operations

Oscilla
Number of
Mnemonic Description tor Hex Code Affected flags
Bytes
Period
Exclusive-OR Register to 68 to 6F (R0 to
XRL A, Rn 1 12
Accumulator R9)
Exclusive-OR content of
the address given by
XRL A, direct 2 12 65
direct byte to
Accumulator

Exclusive-OR indirect
XRL A, @Ri 1 12 66,67 (@R0,@R1)
RAM to Accumulator
No flag affected
Exclusive-OR immediate
XRL A, #data 2 12 64
data to Accumulator

Exclusive-OR Accumulator
XRL direct, A to content of the address 2 12 62 57
given by direct byte
Exclusive-OR immediate
XRL direct, #data 3 24 63
data to direct byte
Instruction Set: Logical operations

Number of Oscillator
Mnemonic Description Hex Code Affected flags
Bytes Period

CLR A Clear Accumulator 1 12 E4 No flag affected

CPL A Complement Accumulator 1 12 F4 No flag affected

RL A Rotate Accumulator Left 1 12 23 No flag affected

Rotate Accumulator Left


RLC A 1 12 33 C
through carry

RR A Rotate Accumulator Right 1 12 03 No flag affected

Rotate Accumulator Right


RRC A 1 12 13 C
through carry
Swap nibbles within the 58
SWAP A 1 12 C4 No flag affected
Accumulator
Instruction Set: Boolean variable
manipulation

Opcode Operand Description Byte Oscillator period Hex Code Affected Flags

CLR C C bit is cleared 1 12 C3 Only C

CLR bit Bit is cleared 2 12 C2 No Flag

SETB C C bit is set 1 12 D3 Only C

SETB bit Bit is set 2 12 D2 No Flag


C bit is complemented /
CPL C 1 12 B3 Only C
toggled
Bit is complemented /
CPL bit 2 12 B2 No Flag
toggled
Only C
ANL C, bit AND direct bit to carry 2 24 82

AND complement of Only C


ANL C, /bit 2 24 B0
direct bit to carry
Instruction Set: Boolean variable manipulation

Oscillator Hex
Opcode Operand Description Byte Affected Flags
period Code

ORL C, bit OR direct bit to carry 2 24 72 Only C

OR complement of Only C
ORL C, /bit 2 24 A0
direct bit to carry

Move direct bit to Only C


MOV C, bit 2 12 A2
carry

Move carry to direct


MOV Bit, C 2 24 92 Only C
bit
Instruction Set: jumping to memory location

Oscillator Hex Affected


Opcode Operand Description Byte
period Code Flags
The 11-bit address written in
AJMP 11-bit address PC unconditionally /PC points 2 24 01 No Flag
to the given 11-bit address.
The 16-bit address written in
No Flag
LJMP 16-bit address PC unconditionally /PC points 3 24 02
to the given 16-bit address.
The relative address written
in PC unconditionally /PC No Flag
SJMP rel 2 24 80
points to the given relative
address.
The indirect relative address
of DPTR written in PC
No Flag
JMP @A+DPTR unconditionally /PC points to 1 24 73
the given relative address of
DPTR .
PC points to the given relative
No Flag
CJNE A, direct, rel address if given direct byte 3 24 B5
and Acc value are not equal.
Instruction Set: Jumping to Memory Location

Oscillator
Opcode Operand Description Byte Hex Code Affected Flags
period
PC points to the given relative
address if given immediate
CJNE A, #data, rel 3 24 B4 No Flag
data and Acc value are not
equal.
PC points to the given relative
B8-BF (depending
address if given immediate No Flag
CJNE Rn, #data, rel 3 24 on different
data and register value are not
register)
equal.
PC points to the given relative
address if given immediate No Flag
CJNE @Ri, #data, rel 3 24 B6,B7
data and indirect value are not
equal.
PC points to the given relative
D8-DF (depending
address if given register value No Flag
DJNZ Rn, rel 2 24 on different
is decremented and it is not
register)
zero.
PC points to the given relative
address if given content of the No Flag
DJNZ direct, rel 3 24 D5
address given by direct byte is
decremented and it is not zero.

No flag62
Gives 1 clock period delay /No
NOP - 1 12 00
operation
Instruction Set: Jumping to Memory Location

Oscillator Hex Affected


Opcode Operand Description Byte
period Code Flags

PC points to the given relative


JZ rel 24 60 No Flag
address if Acc is zero
PC points to the given relative No Flag
JNZ rel 24 70
address if Acc is not zero
2
PC points to the given relative
JC rel 40
address if C = 1
PC points to the given relative
JNC rel 50
address if C = 0
PC points to the given relative
JB bit, rel 20 No Flag
address if Bit is set 24
PC points to the given relative
JNB bit, rel 30
address if Bit is not set 3
PC points to the given relative
JBC bit, rel address if Bit is set and clear bit 10 63
Instruction Set: Call subroutine

Oscillator Affecte
Opcode Operand Description Byte Hex Code
period d Flags
PC points to the given 11-bit
address location after pushing its
ACALL 11-bit address 2 24 11 No Flag
current content –address of next
instruction –on stack.
PC points to the given 16-bit
address location after pushing its
LCALL 16-bit address 3 24 12 No Flag
current content –address of next
instruction –on stack.

64
Instruction Set: return from subroutine

Oscillator
Opcode Operand Description Byte Hex Code Affected Flags
period
Program sequence is
RET - transferred from subroutine 1 24 22 No Flag
to call program
Program sequence is
RETI - transferred from interrupt to 1 24 32 No Flag
call program

65
Part 2: Real-time Operating System
Programming the 8051

Modules:
 Initialization module
• Data Initializations (for RAM or SFRs)
• Configuration of Control registers
• Address Vectoring
 Run Module
• Main program for performing a specific
task or group of tasks
Programming the 8051

Problem Statement:
State and Explain an algorithm for square
wave generation
Programming the 8051

One Simple Solution:


Step 1: Make a port pin low
Step 2: Give necessary delay
Step 3: Toggle the port pin
Step 4: Go to Step 2.

Note: Multi-task is not possible with this algorithm


RTOS in the 8051

Concept:
All the tasks are time-multiplexed
Requirements:

 Specified Time interval generation


 Overall tasks divided into two broad categories
• Background tasks (Time critical job)
• Foreground tasks (Non time critical job)
Interrupt

PROGRAM EXECUTION WITHOUT INTERRUPT


Time

PROGRAM EXECUTION WITH INTERRUPT

Time
ISR: Interrupt Service Routine
RTOS in the 8051

INITIALIZATION MODULE

Resource for time interval generation:


Timer0 or Timer1

Design Issues:
 Mode of timer (16 or 8-
bit) tim_mod .equal 02h
mov TMOD, #tim_mod

 Computation of content to be used for initialization of timer


RTOS in the 8051

Time Slot Generation using single timer interrupt by multiplying factor with basic
timer interrupt interval
TM0: push ACC
push PSW
;----------Basic time interval------------------
tm_0: mov A,tickN
cjne A,#1,tm_1
;----------Basic time interval*tickN------------
sjmp back

tm_1: dec ACC


mov tick10,A
back: pop PSW
pop ACC
reti
RTOS in the 8051

 Configuration of ports as input or output


mov P0, #FFh ; Set port0 as input port
mov P1, #00h ; Set port1 as output

 Address Vectoring
.org 0
ajmp main
.org 000bh
ajmp TM0 ;jump to timer0 routine
RTOS in the 8051

RUN MODULE

Consists of infinite loop

main: acall level1 ;jump to service routine for foreground task


sjmp main

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