8051 Architecture Programming
8051 Architecture Programming
8051 Architecture Programming
Supratim Gupta
Learning Methodology
Hardware Information
• Internal architecture of the processor (8085, 8086,
8051 etc.)
• Internal architecture of peripheral interface
controller (viz. 8255, 8251, 8253, 8237, 8259 etc.)
• Circuit connections of the processor & peripheral
devices (like connection among components in a
PCB)
Software Instructions
• Complex Instruction Set Computer (CISC)
• Reduced Instruction Set Computer (RISC)
Learning Methodology
8085 8051
Internal Architecture Internal Architecture
Registers Registers
• PSW, A • PSW, A
• B, C • B
• D, E • Special Function Registers (like
• H, L TMOD, TCON, IP, IE etc.)
• Program Counter, • Program Counter,
• Stack Pointer • Stack Pointer
Memory: ROM, RAM
External Components
Peripheral I/O Controller
Memory: ROM, RAM
• Parallel: Port (P0 – P3)
Peripheral I/O Controller
• Serial: P3.0, P3.1
• Parallel: 8255
• Interrupt: P3.2, P3.3
• Serial: 8251
• Timer: T0, T1, T2
• Interrupt: 8259
• SPI: P1.4 – P1.7
• Interval Timer: 8253/54
• DMA: 8237 External Components
Peripheral Devices Peripheral Devices
• ADC, DAC • ADC, DAC
• Keyboard • Keyboard
• Display: 7-Segment, LCD etc. • Display: 7-Segment, LCD etc.
• …Many more • …Many more
8051 Architecture
Specific Features
1. 8-bit CPU with registers A (accumulator) and B
2. 16-bit program counter (PC) and data pointer (DPTR)
3. 8-bit program status word (PSW)
4. 8-bit stack pointer (SP)
5. Internal ROM or EPROM of 4k (8051)
6. Internal RAM of 128 bytes
• 4 register banks each containing 8 registers of 8-bit
• 16-bytes bit addressable registers
• 80 bytes general purpose data memory
Cntd…
8051 Architecture
Specific Features
………………………………………
IP IE TMOD TCON PCON T2CON
8 8C 8 8A 8 8D 8 8B 8 C8*
7F
General
TH0 TL0 TH1 TL1 T2CON
30 Purpose
2F
Bit Add. Area 8 CD 8 CC 8 CB 8 CA 8 81
20
1F TH2 TL2
18 Bank 3 RCAP2H RCAP2L SP
17
10 Bank 2
0F 8 83 8 82
08 Bank 1 16 No Address
07 R7 DPH DPL
R6 PC
Data Pointer
R5
R4
R3 8 80* 90* 8 A0* 8 B0* 0000
R2
R1 P0 Latch P1 Latch P2 Latch P3 Latch
00 R0 Internal ROM
Internal RAM * => bit addressable
Special Function Registers: AT89S51
Special Function Registers: AT89S8253
Basic Operation Configuration
Power on RESET V = 5V
PC points 0 location
of ROM after
Oscillator is 1 μF
stabilized and
removes the start
up uncertainty
11.059 MHz 33 pF
33 pF
Crystal Oscillator Connection
C2
XTAL2
33pF
33pF
C1
XTAL1
GND
TB1
Read pin P1.x
A Pin of Port 0
Read latch
TB2
TB1
Read pin P0.x
Interrupts
Interrupt Sources
Interrupt Vector Address
Timer 0 & 1
• 16-bit timers/counters.
• These can be independently configured to operate in a variety of modes as a
timer or as an event counter.
• In timer mode, it runs for a programmed length of time, then
issues an interrupt request.
• In counter mode, it counts negative transitions on an external pin; after a pre-
set number of counts, the counter issues an interrupt request.
Timer 2
Timer 1 Timer 0
Timer 1 Timer 0
÷ 12
Timer 1 Timer 0
÷ 12
Timer 1 Timer 0
÷ 12
÷ 12
÷ 12
Note:
Mode 3 is ‘hold count’ mode for Timer 1
Timer 1 can be used for Baud Rate generation for serial communication
when T0 is in mode 3
Timer Interrupt Generation
Oscillator To
Frequency ÷12 Timer/Counter
(fosc) circuit
Interrupt Interval:
12d
t Rmax 1 Rmin d
f osc
Rmax = FFFF (for 16-bit mode)
= FF (for 8-bit mode)
Rmin = User settable
Timer Interrupt Enable
IE register
Timer 2: Control Registers
Timer 2: Control Registers
Timer 2: Operating Modes
Timer 2: Capture Mode
Timer 2: 16-bit Auto-reload Mode
DCEN = 0: Up Counter
Timer 2: 16-bit Auto-reload Mode
Notation Description
Rn Register R0-R7 of the currently selected Register bank
Direct 8-bit internal data location’s address. This could be an
Internal Data RAM location (0-127) or a SFR (i.e. I/O port,
control register, status register, etc. (128 -255)
@Ri 8-bit internal data RAM location addressed indirectly through
register R0 & R1
#data 8-bit constant included in the instruction
#data 16 16-bit constant included in the instruction
addr 16 16-bit destination address used by LCAL, LJMP. A branch
can be anywhere within the 64-K byte Program Memory
address space
43
Instruction Set: Legends
Notation Description
addr 11 11-bit destination address used by ACAL, AJMP. A branch
can be within the same 2-K byte page of Program Memory as
the first byte of the following instruction
rel Signed (two’s complement) 8-bit offset byte. Used by SJMP
and all conditional jumps. Range is -128 to +127 bytes
relative to first byte of the following instruction
bit Direct address bit of internal data RAM of SFR
44
Instruction Set: DATA Transfer
Number Oscillator
Mnemonic Description Hex Code Affected flags
of Bytes Period
Index Mode: Address of operand in memory is generated by adding base-address and a offset or
displacement
TABLE: MOVC A, @A + PC
RET
DB 06 09 21 23
50
Instruction Set: Arithmetic operations
Number
Oscillator Affected
Mnemonic Description of Bytes Hex Code
Period flags
Add Register to
ADD A, Rn 1 12 28 to 2F (R0 to R9)
Accumulator
Add content of the address
ADD A, direct given by direct byte to 2 12 25
Accumulator C ,OV, AC
Add indirect RAM to
ADD A, @Ri 1 12 26,27(@R0,@R1)
Accumulator
Add immediate data to
ADD A, #data 2 12 24
Accumulator
Add register to
ADDC A, Rn 1 12 38 to 3F (R0 to R9)
Accumulator with carry
Add content of the address
ADDC A, direct given by direct byte to 2 12 35
Accumulator with carry 51
C,OV,AC
Add indirect RAM to
ADDC A, @Ri 1 12 36,37(@R0, @R1)
Accumulator with carry
Add immediate data to
ADDC A, #data 2 12 34
Accumulator with carry
Instruction Set: Arithmetic operations
Oscillator
Mnemonic Description Number of Bytes Hex Code
Period
Subtract register from
SUBB A, Rn 1 12 98 to 9F (R0 to R9)
Accumulator with borrow
Subtract content of the address
SUBB A, direct given by direct byte from 2 12 95
Accumulator with borrow
Subtract indirect RAM from
SUBB A, @Ri 1 12 96, 97(R0,R1)
Accumulator with borrow
52
Instruction Set: Arithmetic operations
Number
Oscillator Affected
Mnemonic Description of Bytes Hex Code
Period flags
No flag
INC DPTR Increment Data Pointer 1 24 A3
affected
MUL AB Multiply A & B 1 48 A4 C=0,OV
Decimal Adjust
DA A 1 12 D4 C
Accumulator
53
Instruction Set: Arithmetic operations
Number of Oscillator
Mnemonic Description Hex Code Flags affected
Bytes Period
INC A Increment Accumulator 1 12 04
No flag
DEC A Decrement Accumulator 1 12 14
affected
Number Oscillato
Mnemonic Description Hex Code Affected flags
of Bytes r Period
AND Register to 58 to 5F (R0 to
ANL A, Rn 1 12
Accumulator R9)
AND content of the address
ANL A, direct given by direct byte to 2 12 55
Accumulator
AND Accumulator to
ANL direct, A content of the address 2 12 52
given by direct byte
AND immediate data to 55
ANL direct, #data content of the address 3 24 53
given by direct byte
Instruction Set: Logical operations
Number Oscillator
Mnemonic Description Hex Code Affected flags
of Bytes Period
OR Register to
ORL A, Rn 1 12 48 to 4F ( R0 to R9)
Accumulator
OR content of the address
ORL A, direct given by direct byte to 2 12 45
Accumulator
OR indirect RAM to
ORL A, @Ri 1 12 46,47 (@R0,@Ri)
Accumulator
No flag affected
OR immediate data to
ORL A, #data 2 12 44
Accumulator
OR Accumulator to
ORL direct, A content of the address 2 12 42
given by direct byte
OR immediate data to
ORL direct, #data content of the address 3 24 43
given by direct byte
56
Instruction Set: Logical operations
Oscilla
Number of
Mnemonic Description tor Hex Code Affected flags
Bytes
Period
Exclusive-OR Register to 68 to 6F (R0 to
XRL A, Rn 1 12
Accumulator R9)
Exclusive-OR content of
the address given by
XRL A, direct 2 12 65
direct byte to
Accumulator
Exclusive-OR indirect
XRL A, @Ri 1 12 66,67 (@R0,@R1)
RAM to Accumulator
No flag affected
Exclusive-OR immediate
XRL A, #data 2 12 64
data to Accumulator
Exclusive-OR Accumulator
XRL direct, A to content of the address 2 12 62 57
given by direct byte
Exclusive-OR immediate
XRL direct, #data 3 24 63
data to direct byte
Instruction Set: Logical operations
Number of Oscillator
Mnemonic Description Hex Code Affected flags
Bytes Period
Opcode Operand Description Byte Oscillator period Hex Code Affected Flags
Oscillator Hex
Opcode Operand Description Byte Affected Flags
period Code
OR complement of Only C
ORL C, /bit 2 24 A0
direct bit to carry
Oscillator
Opcode Operand Description Byte Hex Code Affected Flags
period
PC points to the given relative
address if given immediate
CJNE A, #data, rel 3 24 B4 No Flag
data and Acc value are not
equal.
PC points to the given relative
B8-BF (depending
address if given immediate No Flag
CJNE Rn, #data, rel 3 24 on different
data and register value are not
register)
equal.
PC points to the given relative
address if given immediate No Flag
CJNE @Ri, #data, rel 3 24 B6,B7
data and indirect value are not
equal.
PC points to the given relative
D8-DF (depending
address if given register value No Flag
DJNZ Rn, rel 2 24 on different
is decremented and it is not
register)
zero.
PC points to the given relative
address if given content of the No Flag
DJNZ direct, rel 3 24 D5
address given by direct byte is
decremented and it is not zero.
No flag62
Gives 1 clock period delay /No
NOP - 1 12 00
operation
Instruction Set: Jumping to Memory Location
Oscillator Affecte
Opcode Operand Description Byte Hex Code
period d Flags
PC points to the given 11-bit
address location after pushing its
ACALL 11-bit address 2 24 11 No Flag
current content –address of next
instruction –on stack.
PC points to the given 16-bit
address location after pushing its
LCALL 16-bit address 3 24 12 No Flag
current content –address of next
instruction –on stack.
64
Instruction Set: return from subroutine
Oscillator
Opcode Operand Description Byte Hex Code Affected Flags
period
Program sequence is
RET - transferred from subroutine 1 24 22 No Flag
to call program
Program sequence is
RETI - transferred from interrupt to 1 24 32 No Flag
call program
65
Part 2: Real-time Operating System
Programming the 8051
Modules:
Initialization module
• Data Initializations (for RAM or SFRs)
• Configuration of Control registers
• Address Vectoring
Run Module
• Main program for performing a specific
task or group of tasks
Programming the 8051
Problem Statement:
State and Explain an algorithm for square
wave generation
Programming the 8051
Concept:
All the tasks are time-multiplexed
Requirements:
Time
ISR: Interrupt Service Routine
RTOS in the 8051
INITIALIZATION MODULE
Design Issues:
Mode of timer (16 or 8-
bit) tim_mod .equal 02h
mov TMOD, #tim_mod
Time Slot Generation using single timer interrupt by multiplying factor with basic
timer interrupt interval
TM0: push ACC
push PSW
;----------Basic time interval------------------
tm_0: mov A,tickN
cjne A,#1,tm_1
;----------Basic time interval*tickN------------
sjmp back
Address Vectoring
.org 0
ajmp main
.org 000bh
ajmp TM0 ;jump to timer0 routine
RTOS in the 8051
RUN MODULE