Advanced Computer Architechture Lab Assignment 2 PDF
Advanced Computer Architechture Lab Assignment 2 PDF
Block Diagram:
Verilog Code:
Truth Table:
Inputs Outputs
E Sel0 Sel1 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
2. Design and test Even Parity checker using verilog.
Verilog Code:
Truth Table:
Inputs Output
A B C Ep
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
3. Design and test 1 bit comparator using verilog.
Block Diagram:
Verilog Code:
a b L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
Verilog Code:
xor x3(t3,B[0],In);
xor x4(t4,B[1],In);
xor x5(t5,B[2],In);
xor x6(t6,B[3],In);
fadder f5(A[0],t3,In,Res[0],t1);
fadder f6(A[1],t4,t1,Res[1],t2);
fadder f7(A[2],t5,t2,Res[2],t3);
fadder f8(A[3],t6,t3,Res[3],Out);
endmodule
Truth Table:
A3 B3 S3 C3 C4 V
0 0 1 1 0 1
1 1 0 0 1 1
0 1 1 0 0 0
0 1 0 1 1 0