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Advanced Computer Architechture Lab Assignment 2 PDF

The document discusses the design and testing of four digital logic circuits using Verilog: 1) a 2:4 decoder, 2) an even parity checker, 3) a 1-bit comparator, and 4) an adder/subtractor. Block diagrams and truth tables are provided for each circuit.

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48 views5 pages

Advanced Computer Architechture Lab Assignment 2 PDF

The document discusses the design and testing of four digital logic circuits using Verilog: 1) a 2:4 decoder, 2) an even parity checker, 3) a 1-bit comparator, and 4) an adder/subtractor. Block diagrams and truth tables are provided for each circuit.

Uploaded by

Abhishem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ADVANCED COMPUTER ARCHITECHTURE LAB ASSIGNMENT 2

1. Design and test of a 2:4 Decoder using verilog.

2:4 Decoder Logic Design:

Block Diagram:

Verilog Code:

module dec2_4 (a,b,en,y0,y1,y2,y3)


input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
endmodule

Truth Table:
Inputs Outputs
E Sel0 Sel1 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
2. Design and test Even Parity checker using verilog.

Even Parity checker Logic Design:

Verilog Code:

module Evenparity(Ep, A, B, C);


input A, B, C;
output Ep;
wire W1,W2;
xor G1 (W1, A, B);
xor G2 (Ep, W1, C);
endmodule

Truth Table:

Inputs Output
A B C Ep
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
3. Design and test 1 bit comparator using verilog.

1 bit comparator Logic Design:

Block Diagram:

Verilog Code:

module b_comp1 (a, b, L, E,G);


input a, b; output L, E, G;
wire s1, s2;
not X1(s1, a);
not X2 (s2, b);
and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);
end module
Truth Table:

a b L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

4. Design and test Adder cum Subtractor using verilog.

Adder cum Subtractor Block Diagram:

Verilog Code:

module fadder (A, B, Cin, Sum, Cout);


input A, B;
input Cin;
output Sum;
output Cout;
wire t1,t2,t3,t4;
xor x1(t1,A,B);
xor x2(Sum,t1,Cin);
and g1(t2,A,B);
and g2(t3,B,Cin);
and g3(t4,Cin,A);
or g4(Cout,t2,t3,t4);
endmodule

module add_sub_4 (A, B, In, Res, Out);


input [3:0] A, B;
input In;
output [3:0] Res;
output Out;
wire t1,t2,t3,t4,t5,t6,t7;

xor x3(t3,B[0],In);
xor x4(t4,B[1],In);
xor x5(t5,B[2],In);
xor x6(t6,B[3],In);
fadder f5(A[0],t3,In,Res[0],t1);
fadder f6(A[1],t4,t1,Res[1],t2);
fadder f7(A[2],t5,t2,Res[2],t3);
fadder f8(A[3],t6,t3,Res[3],Out);
endmodule

Truth Table:

A3 B3 S3 C3 C4 V
0 0 1 1 0 1
1 1 0 0 1 1
0 1 1 0 0 0
0 1 0 1 1 0

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