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Differentiate Organization and Architecture.: Advanced Computer Architechture Assignment 1

The document discusses computer architecture assignment 1 which includes: 1. Differentiating between computer architecture and organization, with architecture dealing with high-level design and organization with low-level physical components. 2. Methods for increasing processor speed such as decreasing clock cycles per instruction, decreasing clock time, and improving the instruction set architecture. 3. The main hardware units required for instruction execution: memory address registers, memory buffer register, program counter, and instruction register. 4. How pipeline speedup is proportional to the number of independent pipeline stages, with more stages allowing more parallel instruction processing. 5. The concept of pipeline chaining, where results from one instruction can be directly forwarded to dependent instructions in

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45 views4 pages

Differentiate Organization and Architecture.: Advanced Computer Architechture Assignment 1

The document discusses computer architecture assignment 1 which includes: 1. Differentiating between computer architecture and organization, with architecture dealing with high-level design and organization with low-level physical components. 2. Methods for increasing processor speed such as decreasing clock cycles per instruction, decreasing clock time, and improving the instruction set architecture. 3. The main hardware units required for instruction execution: memory address registers, memory buffer register, program counter, and instruction register. 4. How pipeline speedup is proportional to the number of independent pipeline stages, with more stages allowing more parallel instruction processing. 5. The concept of pipeline chaining, where results from one instruction can be directly forwarded to dependent instructions in

Uploaded by

Abhishem
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ADVANCED COMPUTER ARCHITECHTURE ASSIGNMENT 1

1. Differentiate Organization and Architecture.

Computer Architecture Computer Organization


Computer Architecture is concerned with the Computer Organization is concerned with the
way hardware components are connected structure and behavior of a computer system as
together to form a computer system. seen by the user.
It acts as the interface between hardware It deals with the components of a connection
and software. a
in
Computer Architecture helps us to understand syste
Computer Organization tells us how exactly
all the functionalities of a system the units in the system are arranged
and
A programmer can view architecture in terms of Whereas Organization expresses the realization
instructions, addressing modes and registers of architecture.
While designing a computer system architecture An organization is done on the basis of
is considered first. architecture
Computer Architecture deals with high-level Computer Organization deals with low-level
design issues. design issues.

Architecture involves Logic (Instruction sets,OrganizationinvolvesPhysicalComponents


Addressingmodes, Data types,Cache(Circuit design, Adders, Signals, Peripherals)
optimization)

2. How can you increase the speed of a Processor?


To increasing the speed of a computer processor, or CPU you can either:
 Decrease the CPI (clock cycles per instruction) by using new Hardware.
 Decrease the clock time or Increase clock rate by reducing propagation delays or by use
pipelining.
 Decrease the number of required cycles or improve ISA or Compiler.

3. To execute an instruction what are the different independent hardware


required. Describe their function?
Hardware Involved In Each Instruction Cycle:
 Memory address registers (MAR): It is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.
 Memory Buffer Register (MBR): It is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value read from the memory.
 Program Counter (PC): Holds the address of the next instruction to be fetched.
 Instruction Register (IR): Holds the last instruction fetched.
4. “Speed up of a pipeline is proportional to the number of independent
stage”. Prove it.
Pipeline Stages

RISC processor has 5 stage instruction pipelines to execute all the instructions in the RISC
instruction set. Following are the 5 stages of RISC pipeline with their respective operations:

Stage 1 (Instruction Fetch)


In this stage the CPU reads instructions from the address in the memory whose value is present
in the program counter.
Stage 2 (Instruction Decode)
In this stage, instruction is decoded and the register file is accessed to get the values from the
registers used in the instruction.
Stage 3 (Instruction Execute)
In this stage, ALU operations are performed.
Stage 4 (Memory Access)
In this stage, memory operands are read and written from/to the memory that is present in the
instruction.
Stage 5 (Write Back)
In this stage, computed/fetched value is written back to the register present in the instructions.

Performance of a pipelined processor:

Consider a ‘k’ segment pipeline with clock cycle time as ‘Tp’. Let there be ‘n’ tasks to be
completed in the pipelined processor. Now, the first instruction is going to take ‘k’ cycles to
come out of the pipeline but the other ‘n – 1’ instructions will take only ‘1’ cycle each, i.e., a total
of ‘n – 1’ cycles. So, time taken to execute ‘n’ instructions in a pipelined processor:
ETpipeline = k + n – 1 cycles
= (k + n – 1) Tp
In the same case, for a non-pipelined processor, execution time of ‘n’ instructions will be:
ETnon-pipeline = n * k * Tp
So, speedup (S) of the pipelined processor over non-pipelined processor, when ‘n’ tasks are
executed on the same processor is:
S = Performance of pipelined processor /Performance of Non-pipelined processor
As the performance of a processor is inversely proportional to the execution time, we have,
S = ETnon-pipeline / ETpipeline
=> S = [n * k * Tp] / [(k + n – 1) *
Tp] S = [n * k] / [k + n – 1]
When the number of tasks ‘n’ are significantly larger than k, that is, n >> k
S=n*k/n
S=k
Where ‘k’ are the number of stages in the pipeline.

5. What is pipeline chaining? Explain with example.

Chaining starts when a match occurs between one of the V register operand designators of an
instruction awaiting issue in CIP, and the V register result designator of a previously issued
instruction which has not yet returned its first result element. When this element becomes
available for delivery to the result register, the instruction in CIP is issued (provided there are no
other hold-ups) and the result element is forwarded with this instruction to the appropriate
functional unit. Successive elements follow until the whole vector has been both written into its
result register and forwarded to the second functional unit. The results of this second vector
operation may themselves be chained into a third operation, and so on, as shown in the example
in diagram (a).
Diagram (a) shows a schematic representation of the execution of the instruction sequence

V0 <- Memory
V1 <- V0 * S1
V3 <- V1 + V2

The first instruction causes 64 operands from a designated area in memory to be read out and
copied in sequence into the 64 element positions in V0. Store requests are pipelined in such a
way that the store appears to the processor as a pseudo functional unit. Thus after a start-up
delay of seven clock periods, the first element of the vector from store becomes available for
delivery to V0, and successive elements follow in successive clock periods.

In the clock period following the issue of the first instruction, the second instruction in the
sequence is copied into CIP, but the reservation on V0 prevents it from being issued
immediately. This reservation is lifted, however, allowing the instruction to issue, during the
clock period in which the first vector element arrives from store ready for delivery to V0. This
clock period is known as chain slot time. Chaining allows the vector elements being copied into
V0 to flow directly from the memory read pipeline into the Floating-point Multiply Unit pipeline,
where each element is multiplied by the value taken from S1 at the start of the operation, to
produce the vector V1.

The third instruction in the sequence becomes ready for issue in the clock period following issue
of the second instruction, and it too is held up by a reservation on one of its input operands, this
time V1. When the first element of V1 appears from the Floating-point Multiply Unit, the
reservation on V1 is lifted, allowing this third instruction to issue. Now the elements emanating
from the Floating-point Multiply Unit can flow directly into the Floating-point Add Unit pipeline
as well as into the result register V1. Thus the memory read pipeline, and the Floating-point
Multiply and Floating-point Add Unit pipelines are all chained together to produce the elements
of V3, and the need for all pipelines to have the same segment time now becomes very
apparent; pipelines such as those in the CDC 7600, which have different segment times, could
not be chained together in this way.

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