CHAPTER

DC Biasing—BJTs
4
4.1 INTRODUCTION
The analysis or design of a transistor amplifier requires a knowledge of both the dc
and ac response of the system. Too often it is assumed that the transistor is a magi-
cal device that can raise the level of the applied ac input without the assistance of an
external energy source. In actuality, the improved output ac power level is the result
of a transfer of energy from the applied dc supplies. The analysis or design of any
electronic amplifier therefore has two components: the dc portion and the ac portion.
Fortunately, the superposition theorem is applicable and the investigation of the dc
conditions can be totally separated from the ac response. However, one must keep in
mind that during the design or synthesis stage the choice of parameters for the re-
quired dc levels will affect the ac response, and vice versa.
The dc level of operation of a transistor is controlled by a number of factors, in-
cluding the range of possible operating points on the device characteristics. In Sec-
tion 4.2 we specify the range for the BJT amplifier. Once the desired dc current and
voltage levels have been defined, a network must be constructed that will establish
the desired operating point—a number of these networks are analyzed in this chap-
ter. Each design will also determine the stability of the system, that is, how sensitive
the system is to temperature variations—another topic to be investigated in a later
section of this chapter.
Although a number of networks are analyzed in this chapter, there is an underly-
ing similarity between the analysis of each configuration due to the recurring use of
the following important basic relationships for a transistor:

VBE  0.7 V (4.1)

IE  (  1)IB  IC (4.2)

IC  IB (4.3)

In fact, once the analysis of the first few networks is clearly understood, the path
toward the solution of the networks to follow will begin to become quite apparent. In
most instances the base current IB is the first quantity to be determined. Once IB is
known, the relationships of Eqs. (4.1) through (4.3) can be applied to find the re-
maining quantities of interest. The similarities in analysis will be immediately obvi-
ous as we progress through the chapter. The equations for IB are so similar for a num-

143

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 ber of configurations that one equation can be derived from another simply by drop-
ping or adding a term or two. The primary function of this chapter is to develop a
level of familiarity with the BJT transistor that would permit a dc analysis of any sys-
tem that might employ the BJT amplifier.

4.2 OPERATING POINT

The term biasing appearing in the title of this chapter is an all-inclusive term for the
application of dc voltages to establish a fixed level of current and voltage. For tran-
sistor amplifiers the resulting dc current and voltage establish an operating point on
the characteristics that define the region that will be employed for amplification of
the applied signal. Since the operating point is a fixed point on the characteristics, it
is also called the quiescent point (abbreviated Q-point). By definition, quiescent means
quiet, still, inactive. Figure 4.1 shows a general output device characteristic with four
operating points indicated. The biasing circuit can be designed to set the device op-
eration at any of these points or others within the active region. The maximum rat-
ings are indicated on the characteristics of Fig. 4.1 by a horizontal line for the max-
imum collector current ICmax and a vertical line at the maximum collector-to-emitter
voltage VCEmax. The maximum power constraint is defined by the curve PCmax in the
same figure. At the lower end of the scales are the cutoff region, defined by IB 
0 , and the saturation region, defined by VCE  VCEsat.
The BJT device could be biased to operate outside these maximum limits, but the
result of such operation would be either a considerable shortening of the lifetime of
the device or destruction of the device. Confining ourselves to the active region, one
can select many different operating areas or points. The chosen Q-point often depends
on the intended use of the circuit. Still, we can consider some differences among the

IC (mA)
80 µA

70 µA
IC max 25
60 µA

20 50 µA

PC max 40 µA

15
30 µA
Saturation B
10
20 µA
D

10 µA
5 C

I B = 0 µA
A
0 5 10 15 20 VCE (V)
VCE sat Cutoff
VCE max
Figure 4.1 Various operating points within the limits of operation of a transistor.

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various points shown in Fig. 4.1 to present some basic ideas about the operating point
and, thereby, the bias circuit.
If no bias were used, the device would initially be completely off, resulting in a
Q-point at A—namely, zero current through the device (and zero voltage across it).
Since it is necessary to bias a device so that it can respond to the entire range of an
input signal, point A would not be suitable. For point B, if a signal is applied to the
circuit, the device will vary in current and voltage from operating point, allowing the
device to react to (and possibly amplify) both the positive and negative excursions of
the input signal. If the input signal is properly chosen, the voltage and current of the
device will vary but not enough to drive the device into cutoff or saturation. Point C
would allow some positive and negative variation of the output signal, but the peak-
to-peak value would be limited by the proximity of VCE  0V/IC  0 mA. Operating
at point C also raises some concern about the nonlinearities introduced by the fact
that the spacing between IB curves is rapidly changing in this region. In general, it is
preferable to operate where the gain of the device is fairly constant (or linear) to en-
sure that the amplification over the entire swing of input signal is the same. Point B
is a region of more linear spacing and therefore more linear operation, as shown in
Fig. 4.1. Point D sets the device operating point near the maximum voltage and power
level. The output voltage swing in the positive direction is thus limited if the maxi-
mum voltage is not to be exceeded. Point B therefore seems the best operating point
in terms of linear gain and largest possible voltage and current swing. This is usually
the desired condition for small-signal amplifiers (Chapter 8) but not the case neces-
sarily for power amplifiers, which will be considered in Chapter 16. In this discus-
sion, we will be concentrating primarily on biasing the transistor for small-signal am-
plification operation.
One other very important biasing factor must be considered. Having selected and
biased the BJT at a desired operating point, the effect of temperature must also be
taken into account. Temperature causes the device parameters such as the transistor
current gain (ac) and the transistor leakage current (ICEO) to change. Higher tem-
peratures result in increased leakage currents in the device, thereby changing the op-
erating condition set by the biasing network. The result is that the network design
must also provide a degree of temperature stability so that temperature changes re-
sult in minimum changes in the operating point. This maintenance of the operating
point can be specified by a stability factor, S, which indicates the degree of change
in operating point due to a temperature variation. A highly stable circuit is desirable,
and the stability of a few basic bias circuits will be compared.
For the BJT to be biased in its linear or active operating region the following must
be true:

1. The base–emitter junction must be forward-biased (p-region voltage more posi-

tive), with a resulting forward-bias voltage of about 0.6 to 0.7 V.
2. The base–collector junction must be reverse-biased (n-region more positive), with
the reverse-bias voltage being any value within the maximum limits of the device.

[Note that for forward bias the voltage across the p-n junction is p-positive, while for
reverse bias it is opposite (reverse) with n-positive. This emphasis on the initial let-
ter should provide a means of helping memorize the necessary voltage polarity.]
Operation in the cutoff, saturation, and linear regions of the BJT characteristic are
provided as follows:

1. Linear-region operation:
Base–emitter junction forward biased
Base–collector junction reverse biased

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 2. Cutoff-region operation:
Base–emitter junction reverse biased
3. Saturation-region operation:
Base–emitter junction forward biased
Base–collector junction forward biased

4.3 FIXED-BIAS CIRCUIT

The fixed-bias circuit of Fig. 4.2 provides a relatively straightforward and simple in-
troduction to transistor dc bias analysis. Even though the network employs an npn
transistor, the equations and calculations apply equally well to a pnp transistor con-
figuration merely by changing all current directions and voltage polarities. The cur-
rent directions of Fig. 4.2 are the actual current directions, and the voltages are de-
fined by the standard double-subscript notation. For the dc analysis the network can
be isolated from the indicated ac levels by replacing the capacitors with an open-
circuit equivalent. In addition, the dc supply VCC can be separated into two supplies
(for analysis purposes only) as shown in Fig. 4.3 to permit a separation of input and
output circuits. It also reduces the linkage between the two to the base current IB. The
separation is certainly valid, as we note in Fig. 4.3 that VCC is connected directly to
RB and RC just as in Fig. 4.2.

VCC

RC IC

RB ac
output
C C2 signal
ac IB +
input VCE
signal B
C1 + –
VBE – E

Figure 4.3 dc equivalent of

Figure 4.2 Fixed-bias circuit.
Fig. 4.2.

Forward Bias of Base–Emitter

Consider first the base–emitter circuit loop of Fig. 4.4. Writing Kirchhoff’s voltage
equation in the clockwise direction for the loop, we obtain
VCC  IBRB  VBE  0
Note the polarity of the voltage drop across RB as established by the indicated direc-
tion of IB. Solving the equation for the current IB will result in the following:
VCC  VBE
IB  (4.4)
RB
Equation (4.4) is certainly not a difficult one to remember if one simply keeps in
mind that the base current is the current through RB and by Ohm’s law that current
is the voltage across RB divided by the resistance RB. The voltage across RB is the ap-
Figure 4.4 Base–emitter loop. plied voltage VCC at one end less the drop across the base-to-emitter junction (VBE).

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In addition, since the supply voltage VCC and the base–emitter voltage VBE are con-
stants, the selection of a base resistor, RB, sets the level of base current for the oper-
ating point.

Collector–Emitter Loop
The collector–emitter section of the network appears in Fig. 4.5 with the indicated
direction of current IC and the resulting polarity across RC. The magnitude of the col-
lector current is related directly to IB through

IC  IB (4.5)

It is interesting to note that since the base current is controlled by the level of RB
and IC is related to IB by a constant , the magnitude of IC is not a function of the Figure 4.5 Collector–emitter
resistance RC. Change RC to any level and it will not affect the level of IB or IC as loop.
long as we remain in the active region of the device. However, as we shall see, the
level of RC will determine the magnitude of VCE, which is an important parameter.
Applying Kirchhoff’s voltage law in the clockwise direction around the indicated
closed loop of Fig. 4.5 will result in the following:
VCE  ICRC  VCC  0

and VCE  VCC  ICRC (4.6)

which states in words that the voltage across the collector–emitter region of a tran-
sistor in the fixed-bias configuration is the supply voltage less the drop across RC.
As a brief review of single- and double-subscript notation recall that

VCE  VC  VE (4.7)

where VCE is the voltage from collector to emitter and VC and VE are the voltages
from collector and emitter to ground respectively. But in this case, since VE  0 V,
we have

VCE  VC (4.8)
In addition, since

VBE  VB  VE (4.9)

and VE  0 V, then

VBE  VB (4.10)

Keep in mind that voltage levels such as VCE are determined by placing the red Figure 4.6 Measuring VCE and
VC.
(positive) lead of the voltmeter at the collector terminal with the black (negative) lead
at the emitter terminal as shown in Fig. 4.6. VC is the voltage from collector to ground
and is measured as shown in the same figure. In this case the two readings are iden-
tical, but in the networks to follow the two can be quite different. Clearly under-
standing the difference between the two measurements can prove to be quite impor-
tant in the troubleshooting of transistor networks.

Determine the following for the fixed-bias configuration of Fig. 4.7. EXAMPLE 4.1
(a) IBQ and ICQ.
(b) VCEQ.
(c) VB and VC.
(d) VBC.

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 Figure 4.7 dc fixed-bias cir-
cuit for Example 4.1.

Solution
VCC  VBE 12 V  0.7 V
(a) Eq. (4.4): IBQ    47.08 A
RB 240 k

Eq. (4.5): ICQ  IBQ  (50)(47.08 A)  2.35 mA

(b) Eq. (4.6): VCEQ  VCC  ICRC
 12 V  (2.35 mA)(2.2 k
)
 6.83 V
(c) VB  VBE  0.7 V
VC  VCE  6.83 V
(d) Using double-subscript notation yields
VBC  VB  VC  0.7 V  6.83 V
 6.13 V
with the negative sign revealing that the junction is reversed-biased, as it should be
for linear amplification.

Transistor Saturation
The term saturation is applied to any system where levels have reached their maxi-
mum values. A saturated sponge is one that cannot hold another drop of liquid. For
a transistor operating in the saturation region, the current is a maximum value for the
particular design. Change the design and the corresponding saturation level may rise
or drop. Of course, the highest saturation level is defined by the maximum collector
current as provided by the specification sheet.
Saturation conditions are normally avoided because the base–collector junction is
no longer reverse-biased and the output amplified signal will be distorted. An oper-
ating point in the saturation region is depicted in Fig. 4.8a. Note that it is in a region
where the characteristic curves join and the collector-to-emitter voltage is at or be-
low VCEsat. In addition, the collector current is relatively high on the characteristics.
If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick,
direct method for determining the saturation level becomes apparent. In Fig. 4.8b, the
current is relatively high and the voltage VCE is assumed to be zero volts. Applying
Ohm’s law the resistance between collector and emitter terminals can be determined
as follows:
V E 0V
RCE  C   0

IC ICsat

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 IC IC

I C sat – Q-point
I C sat – Q-point

0 VCE sat VCE 0 VCE

(a) (b)

Figure 4.8 Saturation regions: (a) actual; (b) approximate.

Applying the results to the network schematic would result in the configuration of
Fig. 4.9.
For the future, therefore, if there were an immediate need to know the approxi-
mate maximum collector current (saturation level) for a particular design, simply in-
sert a short-circuit equivalent between collector and emitter of the transistor and cal-
culate the resulting collector current. In short, set VCE  0 V. For the fixed-bias
configuration of Fig. 4.10, the short circuit has been applied, causing the voltage across
RC to be the applied voltage VCC. The resulting saturation current for the fixed-bias Figure 4.9 Determining ICsat.
configuration is
V C
ICsat  C (4.11)
RC

Figure 4.10 Determining ICsat

for the fixed-bias configuration.

Once ICsat is known, we have some idea of the maximum possible collector current
for the chosen design and the level to stay below if we expect linear amplification.

Determine the saturation level for the network of Fig. 4.7. EXAMPLE 4.2

Solution
V C 12 V
ICsat  C   5.45 mA
RC 2.2 k

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 The design of Example 4.1 resulted in ICQ  2.35 mA, which is far from the sat-
uration level and about one-half the maximum value for the design.

Load-Line Analysis
The analysis thus far has been performed using a level of  corresponding with the
resulting Q-point. We will now investigate how the network parameters define the
possible range of Q-points and how the actual Q-point is determined. The network of
Fig. 4.11a establishes an output equation that relates the variables IC and VCE in the
following manner:

VCE  VCC  ICRC (4.12)

The output characteristics of the transistor also relate the same two variables IC and
VCE as shown in Fig. 4.11b.
In essence, therefore, we have a network equation and a set of characteristics that
employ the same variables. The common solution of the two occurs where the con-
straints established by each are satisfied simultaneously. In other words, this is simi-
lar to finding the solution of two simultaneous equations: one established by the net-
work and the other by the device characteristics.
The device characteristics of IC versus VCE are provided in Fig. 4.11b. We must
now superimpose the straight line defined by Eq. (4.12) on the characteristics. The
most direct method of plotting Eq. (4.12) on the output characteristics is to use the
fact that a straight line is defined by two points. If we choose IC to be 0 mA, we are
specifying the horizontal axis as the line on which one point is located. By substitut-
ing IC  0 mA into Eq. (4.12), we find that
VCE  VCC  (0)RC

and VCE  VCC  IC0 mA (4.13)

defining one point for the straight line as shown in Fig. 4.12.

IC (mA)

8 50 µA

7 40 µA

6
30 µA
5

V CC 4
IC 20 µA
+
RC 3
RB – 10 µA
2
+
VCE 1 I B = 0 µA
IB
– 0 5 10 15 VCE (V)
ICEO

(a) (b)

Figure 4.11 Load-line analysis: (a) the network; (b) the device characteristics.

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 IC

VCC
RC

Q-point IB
Q
VCE = 0 V

Load line

0 VCC VCE
Figure 4.12 Fixed-bias
IC = 0 mA load line.

If we now choose VCE to be 0 V, which establishes the vertical axis as the line on
which the second point will be defined, we find that IC is determined by the follow-
ing equation:
0  VCC  ICRC


V C
and IC  C (4.14)
RC VCE  0 V

as appearing on Fig. 4.12.

By joining the two points defined by Eqs. (4.13) and (4.14), the straight line es-
tablished by Eq. (4.12) can be drawn. The resulting line on the graph of Fig. 4.12 is
called the load line since it is defined by the load resistor RC. By solving for the re-
sulting level of IB, the actual Q-point can be established as shown in Fig. 4.12.
If the level of IB is changed by varying the value of RB the Q-point moves up or
down the load line as shown in Fig. 4.13. If VCC is held fixed and RC changed, the
load line will shift as shown in Fig. 4.14. If IB is held fixed, the Q-point will move
as shown in the same figure. If RC is fixed and VCC varied, the load line shifts as
shown in Fig. 4.15.

Figure 4.14 Effect of increasing levels of RC on the load

Figure 4.13 Movement of Q-point with increasing levels of IB. line and Q-point.

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 Figure 4.15 Effect of lower
values of VCC on the load line
and Q-point.

EXAMPLE 4.3 Given the load line of Fig. 4.16 and the defined Q-point, determine the required val-
ues of VCC, RC, and RB for a fixed-bias configuration.

I C (mA)
60 µA

12
50 µA
10
40 µA
8
30 µA
6 Q-point
20 µA
4
10 µA
2 I B = 0 µA

0 5 10 15 20 VCE Figure 4.16 Example 4.3

Solution
From Fig. 4.16,
VCE  VCC  20 V at IC  0 mA
V C
IC  C at VCE  0 V
RC
V C 20 V
and RC  C   2 k
IC 10 mA
VCC  VBE
IB 
RB
VCC  VBE 20 V  0.7 V
and RB    772 k
IB 25 A

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4.4 EMITTER-STABILIZED BIAS CIRCUIT
The dc bias network of Fig. 4.17 contains an emitter resistor to improve the stability
level over that of the fixed-bias configuration. The improved stability will be demon-
strated through a numerical example later in the section. The analysis will be per-
formed by first examining the base–emitter loop and then using the results to inves-
tigate the collector–emitter loop.

Figure 4.17 BJT bias circuit

with emitter resistor.

Base–Emitter Loop
The base–emitter loop of the network of Fig. 4.17 can be redrawn as shown in Fig.
4.18. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise di-
rection will result in the following equation:
VCC  IBRB  VBE  IERE  0 (4.15)
Recall from Chapter 3 that
IE  (  1)IB (4.16)
Substituting for IE in Eq. (4.15) will result in
VCC  IBRB  VBE  (  I)IBRE  0
Grouping terms will then provide the following:
IB(RB  (  1)RE)  VCC  VBE  0
Multiplying through by (1) we have
IB(RB  (  1)RE)VCC  VBE  0
with IB(RB  (  1)RE)  VCC  VBE
and solving for IB gives
VCC  VBE
IB  (4.17)
RB  (  1)RE
Note that the only difference between this equation for IB and that obtained for the
fixed-bias configuration is the term (  1)RE.
There is an interesting result that can be derived from Eq. (4.17) if the equation
is used to sketch a series network that would result in the same equation. Such is Figure 4.18 Base–emitter loop.

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 Figure 4.19 Network derived Figure 4.20 Reflected impedance
from Eq. (4.17). level of RE.

the case for the network of Fig. 4.19. Solving for the current IB will result in the same
equation obtained above. Note that aside from the base-to-emitter voltage VBE, the
resistor RE is reflected back to the input base circuit by a factor (  1). In other
words, the emitter resistor, which is part of the collector–emitter loop, “appears as”
(  1)RE in the base–emitter loop. Since  is typically 50 or more, the emitter re-
sistor appears to be a great deal larger in the base circuit. In general, therefore, for
the configuration of Fig. 4.20,

Ri  (  1)RE (4.18)

Equation (4.18) is one that will prove useful in the analysis to follow. In fact, it
provides a fairly easy way to remember Eq. (4.17). Using Ohm’s law, we know that
the current through a system is the voltage divided by the resistance of the circuit.
For the base–emitter circuit the net voltage is VCC  VBE. The resistance levels are
RB plus RE reflected by (  1). The result is Eq. (4.17).

Collector–Emitter Loop
The collector–emitter loop is redrawn in Fig. 4.21. Writing Kirchhoff’s voltage law
for the indicated loop in the clockwise direction will result in
IERE  VCE  ICRC  VCC  0
Substituting IE  IC and grouping terms gives
VCE  VCC  IC (RC  RE)  0

and VCE  VCC  IC (RC  RE) (4.19)

The single-subscript voltage VE is the voltage from emitter to ground and is de-
termined by

VE  IERE (4.20)
Figure 4.21 Collector–emitter
loop. while the voltage from collector to ground can be determined from
VCE  VC  VE

and VC  VCE  VE (4.21)

or VC  VCC  ICRC (4.22)

The voltage at the base with respect to ground can be determined from

VB  VCC  IBRB (4.23)

or VB  VBE  VE (4.24)

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For the emitter bias network of Fig. 4.22, determine: EXAMPLE 4.4
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.

Figure 4.22 Emitter-stabilized

bias circuit for Example 4.4.

Solution
VCC  VBE 20 V  0.7 V
(a) Eq. (4.17): IB  
RB  (  1)RE 430 k
 (51)(1 k
)
19.3 V
  40.1 A
481 k

(b) IC  IB
 (50)(40.1 A)
 2.01 mA
(c) Eq. (4.19): VCE  VCC  IC (RC  RE)
 20 V  (2.01 mA)(2 k
 1 k
)  20 V  6.03 V
 13.97 V
(d) VC  VCC  ICRC
 20 V  (2.01 mA)(2 k
)  20 V  4.02 V
 15.98 V
(e) VE  VC  VCE
 15.98 V  13.97 V
 2.01 V
or VE  IERE  ICRE
 (2.01 mA)(1 k
)
 2.01 V
(f) VB  VBE  VE
 0.7 V  2.01 V
 2.71 V
(g) VBC  VB  VC
 2.71 V  15.98 V
 13.27 V (reverse-biased as required)

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 Improved Bias Stability
The addition of the emitter resistor to the dc bias of the BJT provides improved sta-
bility, that is, the dc bias currents and voltages remain closer to where they were set
by the circuit when outside conditions, such as temperature, and transistor beta,
change. While a mathematical analysis is provided in Section 4.12, some comparison
of the improvement can be obtained as demonstrated by Example 4.5.

EXAMPLE 4.5 Prepare a table and compare the bias voltage and currents of the circuits of Figs. 4.7
and Fig. 4.22 for the given value of   50 and for a new value of   100. Com-
pare the changes in IC and VCE for the same increase in .

Solution
Using the results calculated in Example 4.1 and then repeating for a value of   100
yields the following:

 IB (A) IC (mA) VCE (V)

50 47.08 2.35 6.83

100 47.08 4.71 1.64

The BJT collector current is seen to change by 100% due to the 100% change in the
value of . IB is the same and VCE decreased by 76%.
Using the results calculated in Example 4.4 and then repeating for a value of
  100, we have the following:

 IB (A) IC (mA) VCE (V)

50 40.1 2.01 13.97

100 36.3 3.63 9.11

Now the BJT collector current increases by about 81% due to the 100% increase in .
Notice that IB decreased, helping maintain the value of IC —or at least reducing the
overall change in IC due to the change in . The change in VCE has dropped to about
35%. The network of Fig. 4.22 is therefore more stable than that of Fig. 4.7 for the
same change in .

Saturation Level
The collector saturation level or maximum collector current for an emitter-bias de-
sign can be determined using the same approach applied to the fixed-bias configura-
tion: Apply a short circuit between the collector–emitter terminals as shown in Fig.
4.23 and calculate the resulting collector current. For Fig. 4.23:
V
ICsat  CC (4.25)
RC  RE

Figure 4.23 Determining ICsat for The addition of the emitter resistor reduces the collector saturation level below that
the emitter-stabilized bias circuit. obtained with a fixed-bias configuration using the same collector resistor.

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Determine the saturation current for the network of Example 4.4. EXAMPLE 4.6

Solution V
ICsat  CC
RC  RE
20 V 20 V
 
2 k
 1 k
3 k

 6.67 mA
which is about twice the level of ICQ for Example 4.4.

Load-Line Analysis
The load-line analysis of the emitter-bias network is only slightly different from that
encountered for the fixed-bias configuration. The level of IB as determined by Eq.
(4.17) defines the level of IB on the characteristics of Fig. 4.24 (denoted IBQ).

Figure 4.24 Load line for the

emitter-bias configuration.

The collector–emitter loop equation that defines the load line is the following:
VCE  VCC  IC (RC  RE)
Choosing IC  0 mA gives

VCE  VCCIC0 mA (4.26)

as obtained for the fixed-bias configuration. Choosing VCE  0 V gives


V
IC  CC (4.27)
RC  RE VCE0 V

as shown in Fig. 4.24. Different levels of IBQ will, of course, move the Q-point up or
down the load line.

4.5 VOLTAGE-DIVIDER BIAS

In the previous bias configurations the bias current ICQ and voltage VCEQ were a func-
tion of the current gain () of the transistor. However, since  is temperature sensi-
tive, especially for silicon transistors, and the actual value of beta is usually not well
defined, it would be desirable to develop a bias circuit that is less dependent, or in

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 Figure 4.25 Voltage-divider bias configuration. Figure 4.26 Defining the Q-point for the voltage-divider
bias configuration.

fact, independent of the transistor beta. The voltage-divider bias configuration of Fig.
4.25 is such a network. If analyzed on an exact basis the sensitivity to changes in beta
is quite small. If the circuit parameters are properly chosen, the resulting levels of ICQ
and VCEQ can be almost totally independent of beta. Recall from previous discussions
that a Q-point is defined by a fixed level of ICQ and VCEQ as shown in Fig. 4.26. The
level of IBQ will change with the change in beta, but the operating point on the char-
acteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters
are employed.
As noted above, there are two methods that can be applied to analyze the voltage-
divider configuration. The reason for the choice of names for this configuration will
become obvious in the analysis to follow. The first to be demonstrated is the exact
method that can be applied to any voltage-divider configuration. The second is re-
ferred to as the approximate method and can be applied only if specific conditions
are satisfied. The approximate approach permits a more direct analysis with a savings
in time and energy. It is also particularly helpful in the design mode to be described
in a later section. All in all, the approximate approach can be applied to the majority
of situations and therefore should be examined with the same interest as the exact
method.

Exact Analysis
The input side of the network of Fig. 4.25 can be redrawn as shown in Fig. 4.27 for
the dc analysis. The Thévenin equivalent network for the network to the left of the
base terminal can then be found in the following manner:

B
R1

VCC R2
RE

Figure 4.27 Redrawing the

input side of the network of
Thévenin Fig. 4.25.

158 Chapter 4 DC Biasing—BJTs

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 RTh: The voltage source is replaced by a short-circuit equivalent as shown in
Fig. 4.28. R1

R2
RTh  R1R2 (4.28) R Th

ETh: The voltage source VCC is returned to the network and the open-circuit
Thévenin voltage of Fig. 4.29 determined as follows:
Figure 4.28 Determining RTh.
Applying the voltage-divider rule:
R2VCC
ETh  VR2  (4.29)
R1  R2
R1 + +
The Thévenin network is then redrawn as shown in Fig. 4.30, and IBQ can be de- VCC R2 VR E Th
2
termined by first applying Kirchhoff’s voltage law in the clockwise direction for the
loop indicated: – –
ETh  IBRTh  VBE  IERE  0
Substituting IE  (  1)IB and solving for IB yields
Figure 4.29 Determining ETh.
ETh  VBE
IB  (4.30)
RTh  (  1)RE

Although Eq. (4.30) initially appears different from those developed earlier, note
that the numerator is again a difference of two voltage levels and the denominator is
RTh
the base resistance plus the emitter resistor reflected by (  1)—certainly very sim- B
ilar to Eq. (4.17). +
Once IB is known, the remaining quantities of the network can be found in the IB VBE – E
ETh
same manner as developed for the emitter-bias configuration. That is, RE
VCE  VCC  IC (RC  RE) (4.31)

which is exactly the same as Eq. (4.19). The remaining equations for VE, VC, and VB Figure 4.30 Inserting the
are also the same as obtained for the emitter-bias configuration. Thévenin equivalent circuit.

Determine the dc bias voltage VCE and the current IC for the voltage-divider config- EXAMPLE 4.7
uration of Fig. 4.31.

Figure 4.31 Beta-stabilized

circuit for Example 4.7.

4.5 Voltage-Divider Bias 159

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 Solution

Eq. (4.28): RTh  R1R2

(39 k
)(3.9 k
)
  3.55 k

39 k
 3.9 k

R2VCC
Eq. (4.29): ETh 
R1  R2
(3.9 k
)(22 V)
  2 V
39 k
 3.9 k

ETh  VBE
Eq. (4.30): IB 
RTh  (  1)RE
2 V  0.7 V 1.3 V
 
3.55 k
 (141)(1.5 k
) 3.55 k
 211.5 k

 6.05 A
IC  IB
 (140)(6.05 A)
 0.85 mA
Eq. (4.31): VCE  VCC  IC (RC  RE)
 22 V  (0.85 mA)(10 k
 1.5 k
)
 22 V  9.78 V
 12.22 V

Approximate Analysis
The input section of the voltage-divider configuration can be represented by the net-
work of Fig. 4.32. The resistance Ri is the equivalent resistance between base and
ground for the transistor with an emitter resistor RE. Recall from Section 4.4 [Eq.
(4.18)] that the reflected resistance between base and emitter is defined by Ri 
(  1)RE. If Ri is much larger than the resistance R2, the current IB will be much
smaller than I2 (current always seeks the path of least resistance) and I2 will be ap-
proximately equal to I1. If we accept the approximation that IB is essentially zero am-
peres compared to I1 or I2, then I1  I2 and R1 and R2 can be considered series ele-

Figure 4.32 Partial-bias circuit

for calculating the approximate
base voltage VB.

160 Chapter 4 DC Biasing—BJTs

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ments. The voltage across R2, which is actually the base voltage, can be determined
using the voltage-divider rule (hence the name for the configuration). That is,
R2VCC
VB  (4.32)
R1  R2

Since Ri  (  1)RE  RE the condition that will define whether the approxi-
mate approach can be applied will be the following:

RE  10R2 (4.33)

In other words, if  times the value of RE is at least 10 times the value of R2, the ap-
proximate approach can be applied with a high degree of accuracy.
Once VB is determined, the level of VE can be calculated from

VE  VB  VBE (4.34)

and the emitter current can be determined from

VE
IE  (4.35)
RE

and ICQ  IE (4.36)

The collector-to-emitter voltage is determined by

VCE  VCC  ICRC  IERE
but since IE  IC,

VCEQ  VCC  IC (RC  RE) (4.37)

Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that 
does not appear and IB was not calculated. The Q-point (as determined by ICQ and
VCEQ) is therefore independent of the value of .

Repeat the analysis of Fig. 4.31 using the approximate technique, and compare solu- EXAMPLE 4.8
tions for ICQ and VCEQ.

Solution
Testing:
RE  10R2
(140)(1.5 k
)  10(3.9 k
)
210 k
 39 k
(satisfied)
R2VCC
Eq. (4.32): VB 
R1  R2
(3.9 k
)(22 V)

39 k
 3.9 k

2V

4.5 Voltage-Divider Bias 161

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 Note that the level of VB is the same as ETh determined in Example 4.7. Essen-
tially, therefore, the primary difference between the exact and approximate techniques
is the effect of RTh in the exact analysis that separates ETh and VB.
Eq. (4.34): VE  VB  VBE
 2 V  0.7 V
 1.3 V
VE 1.3 V
ICQ  IE    0.867 mA
RE 1.5 k

compared to 0.85 mA with the exact analysis. Finally,

VCEQ  VCC  IC(RC  RE)
 22 V  (0.867 mA)(10 kV  1.5 k
)
 22 V  9.97 V
 12.03 V
versus 12.22 V obtained in Example 4.7.
The results for ICQ and VCEQ are certainly close, and considering the actual vari-
ation in parameter values one can certainly be considered as accurate as the other.
The larger the level of Ri compared to R2, the closer the approximate to the exact so-
lution. Example 4.10 will compare solutions at a level well below the condition es-
tablished by Eq. (4.33).

EXAMPLE 4.9 Repeat the exact analysis of Example 4.7 if  is reduced to 70, and compare solu-
tions for ICQ and VCEQ.

Solution
This example is not a comparison of exact versus approximate methods but a testing
of how much the Q-point will move if the level of  is cut in half. RTh and ETh are
the same:
RTh  3.55 k
, ETh  2 V
ETh  VBE
IB 
RTh  (  1)RE
2 V  0.7 V 1.3 V
 
3.55 k
 (71)(1.5 k
) 3.55 k
 106.5 k

 11.81 A
ICQ  IB
 (70)(11.81 A)
 0.83 mA
VCEQ  VCC  IC(RC  RE)
 22 V  (0.83 mA)(10 k
 1.5 k
)
 12.46 V

162 Chapter 4 DC Biasing—BJTs

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Tabulating the results, we have:

 ICQ (mA) VCEQ (V)

140 0.85 12.22

70 0.83 12.46

The results clearly show the relative insensitivity of the circuit to the change in .
Even though  is drastically cut in half, from 140 to 70, the levels of ICQ and VCEQ
are essentially the same.

Determine the levels of ICQ and VCEQ for the voltage-divider configuration of Fig. 4.33 EXAMPLE 4.10
using the exact and approximate techniques and compare solutions. In this case, the
conditions of Eq. (4.33) will not be satisfied but the results will reveal the difference
in solution if the criterion of Eq. (4.33) is ignored.

Figure 4.33 Voltage-divider

configuration for Example 4.10.

Solution
Exact Analysis
Eq. (4.33): RE  10R2
(50)(1.2 k
)  10(22 k
)
60 k
 220 k
(not satisfied)
RTh  R1R2  82 k
22 k
 17.35 k

R2VCC 22 k
(18 V)
ETh    3.81 V
R1  R2 82 k
 22 k

ETh  VBE 3.81 V  0.7 V 3.11 V

IB   
RTh  (  1)RE 17.35 k
 (51)(1.2 k
) 78.55 k

 39.6 A
ICQ  IB  (50)(39.6 A)  1.98 mA
VCEQ  VCC  IC(RC  RE)
 18 V  (1.98 mA)(5.6 k
 1.2 k
)
 4.54 V

4.5 Voltage-Divider Bias 163

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 Approximate Analysis

VB  ETh  3.81 V
VE  VB  VBE  3.81 V  0.7 V  3.11 V
VE 3.11 V
ICQ  IE    2.59 mA
RE 1.2 k

VCEQ  VCC  IC (RC  RE)

 18 V  (2.59 mA)(5.6 k
 1.2 k
)
 3.88 V
Tabulating the results, we have:

ICQ (mA) VCEQ (V)

Exact 1.98 4.54

Approximate 2.59 3.88

The results reveal the difference between exact and approximate solutions. ICQ is about
30% greater with the approximate solution, while VCEQ is about 10% less. The results
are notably different in magnitude, but even though RE is only about three times
larger than R2, the results are still relatively close to each other. For the future, how-
ever, our analysis will be dictated by Eq. (4.33) to ensure a close similarity between
exact and approximate solutions.

Transistor Saturation
The output collector–emitter circuit for the voltage-divider configuration has the same
appearance as the emitter-biased circuit analyzed in Section 4.4. The resulting equa-
tion for the saturation current (when VCE is set to zero volts on the schematic) is there-
fore the same as obtained for the emitter-biased configuration. That is,

V
ICsat  ICmax  CC (4.38)
RC  RE

Load-Line Analysis
The similarities with the output circuit of the emitter-biased configuration result in
the same intersections for the load line of the voltage-divider configuration. The load
line will therefore have the same appearance as that of Fig. 4.24, with


V
IC  CC (4.39)
RC  RE VCE0 V

and VCE  VCCIC0 mA (4.40)

The level of IB is of course determined by a different equation for the voltage-divider
bias and the emitter-bias configurations.

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4.6 DC BIAS WITH VOLTAGE FEEDBACK
An improved level of stability can also be obtained by introducing a feedback path
from collector to base as shown in Fig. 4.34. Although the Q-point is not totally in-
dependent of beta (even under approximate conditions), the sensitivity to changes in
beta or temperature variations is normally less than encountered for the fixed-bias or
emitter-biased configurations. The analysis will again be performed by first analyz-
ing the base–emitter loop with the results applied to the collector–emitter loop.

Base–Emitter Loop
Figure 4.35 shows the base–emitter loop for the voltage feedback configuration. Writ-
ing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will
result in
VCC  I CRC  IBRB  VBE  IERE  0
VCC
+
RC RC
I C'
I C' – +–
vo
RB IC
RB IC C2
IB VCC IB
+
vi VCE +
C1 – VBE
– IE
IE +
RE
RE
–

Figure 4.35 Base–emitter loop for the

Figure 4.34 dc bias circuit with voltage feedback. network of Fig. 4.34.
It is important to note that the current through RC is not IC but I C (where I C 
IC  IB). However, the level of IC and I C far exceeds the usual level of IB and the ap-
proximation I C  IC is normally employed. Substituting I C  IC  IB and IE  IC
will result in
VCC  IBRC  IBRB  VBE  IBRE  0
Gathering terms, we have
VCC  VBE  IB(RC  RE)  IBRB  0
and solving for IB yields
VCC  VBE
IB  (4.41)
RB  (RC  RE)

The result is quite interesting in that the format is very similar to equations for IB
obtained for earlier configurations. The numerator is again the difference of available
voltage levels, while the denominator is the base resistance plus the collector and emit-
ter resistors reflected by beta. In general, therefore, the feedback path results in a re-
flection of the resistance RC back to the input circuit, much like the reflection of RE.
In general, the equation for IB has had the following format:
V
IB 
RB  R

4.6 DC Bias with Voltage Feedback 165

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 with the absence of R for the fixed-bias configuration, R  RE for the emitter-bias
setup (with (  1)  ), and R  RC  RE for the collector-feedback arrangement.
The voltage V is the difference between two voltage levels.
Since IC  IB,
V
ICQ 
RB  R
In general, the larger R is compared to RB, the less the sensitivity of ICQ to varia-
tions in beta. Obviously, if R  RB and RB  R  R , then
V V V
ICQ   
RB  R R R
and ICQ is independent of the value of beta. Since R is typically larger for the voltage-
feedback configuration than for the emitter-bias configuration, the sensitivity to vari-
ations in beta is less. Of course, R is zero ohms for the fixed-bias configuration and
I'C is therefore quite sensitive to variations in beta.
+
RC
Collector–Emitter Loop
–
The collector–emitter loop for the network of Fig. 4.34 is provided in Fig. 4.36. Ap-
IC
plying Kirchhoff’s voltage law around the indicated loop in the clockwise direction
+ VCC will result in
VCE IERE  VCE  I C RC  VCC  0
–
IE + Since I C  IC and IE  IC, we have
RE IC (RC  RE)  VCE  VCC  0
–
and VCE  VCC  IC (RC  RE) (4.42)

Figure 4.36 Collector–emitter which is exactly as obtained for the emitter-bias and voltage-divider bias configura-
loop for the network of Fig. 4.34. tions.

EXAMPLE 4.11 Determine the quiescent levels of ICQ and VCEQ for the network of Fig. 4.37.

Solution
VCC  VBE
Eq. (4.41): IB 
RB  (RC  RE)
10 V  0.7 V
10 V 
250 k
 (90)(4.7 k
 1.2 k
)
9.3 V 9.3 V
4.7 kΩ  
250 k
 531 k
781 k

250 kΩ
vo  11.91 A
10 µF
ICQ  IB  (90)(11.91 A)
vi β = 90
10 µF  1.07 mA
VCEQ  VCC  IC (RC  RE)
1.2 kΩ
 10 V  (1.07 mA)(4.7 k
 1.2 k
)
 10 V  6.31 V
Figure 4.37 Network for Example 4.11.  3.69 V

166 Chapter 4 DC Biasing—BJTs

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Repeat Example 4.11 using a beta of 135 (50% more than Example 4.11). EXAMPLE 4.12

Solution
It is important to note in the solution for IB in Example 4.11 that the second term in
the denominator of the equation is larger than the first. Recall in a recent discussion
that the larger this second term is compared to the first, the less the sensitivity to
changes in beta. In this example the level of beta is increased by 50%, which will in-
crease the magnitude of this second term even more compared to the first. It is more
important to note in these examples, however, that once the second term is relatively
large compared to the first, the sensitivity to changes in beta is significantly less.
Solving for IB gives
VCC  VBE
IB  
RB  (RC  RE)
10 V  0.7 V

250 k
 (135)(4.7 k
 1.2 k
)
9.3 V 9.3 V
 
250 k
 796.5 k
1046.5 k

 8.89 A
and ICQ  IB
 (135)(8.89 A)
 1.2 mA
and VCEQ  VCC  IC (RC  RE)
 10 V  (1.2 mA)(4.7 k
 1.2 k
)
 10 V  7.08 V
 2.92 V
Even though the level of  increased 50%, the level of ICQ only increased 12.1%
while the level of VCEQ decreased about 20.9%. If the network were a fixed-bias de-
sign, a 50% increase in  would have resulted in a 50% increase in ICQ and a dra-
matic change in the location of the Q-point.

Determine the dc level of IB and VC for the network of Fig. 4.38. EXAMPLE 4.13
18 V

3.3 kΩ
91 kΩ 110 kΩ 10 µF
vo
R1 R2
10 µF
10 µF
vi β = 75

510 Ω 50 µF

Figure 4.38 Network for

Example 4.13.

4.6 DC Bias with Voltage Feedback 167

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 Solution
In this case, the base resistance for the dc analysis is composed of two resistors with
a capacitor connected from their junction to ground. For the dc mode, the capacitor
assumes the open-circuit equivalence and RB  R1  R2.
Solving for IB gives
VCC  VBE
IB 
RB  (RC  RE)
18 V  0.7 V

(91 k
 110 k
)  (75)(3.3 k
 0.51 k
)
17.3 V 17.3 V
 
201 k
 285.75 k
486.75 k

 35.5 A
IC  IB
 (75)(35.5 A)
 2.66 mA
VC  VCC  I CRC  VCC  ICRC
 18 V  (2.66 mA)(3.3 k
)
 18 V  8.78 V
 9.22 V

Saturation Conditions
Using the approximation I C  IC , the equation for the saturation current is the same
as obtained for the voltage-divider and emitter-bias configurations. That is,

V
ICsat  ICmax  CC (4.43)
RC  RE

Load-Line Analysis
Continuing with the approximation I C  IC will result in the same load line defined
for the voltage-divider and emitter-biased configurations. The level of IBQ will be de-
fined by the chosen bias configuration.

4.7 MISCELLANEOUS BIAS

CONFIGURATIONS
There are a number of BJT bias configurations that do not match the basic mold of
those analyzed in the previous sections. In fact, there are variations in design that
would require many more pages than is possible in a book of this type. However, the
primary purpose here is to emphasize those characteristics of the device that permit
a dc analysis of the configuration and to establish a general procedure toward the de-
sired solution. For each configuration discussed thus far, the first step has been the
derivation of an expression for the base current. Once the base current is known, the
collector current and voltage levels of the output circuit can be determined quite di-

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