A HIGH SPEED COMPACT PRIORITY ENCODER

Reza Hashemian

Northern Illinois University

Department of Electrical Engineering
DeKalb, Illinois 60115-2854

Abstract: A high speed compact priority

encoder is developed for high density Some of the important features and
parallel operations. A simple and highly criteria in the presented technique are as
efficient CMOS technique is implemented for follows:
the construction of the priority resolution
(PR) modules . The technique in based on a 1) The growth of the circuit for high
staircase array structure, and it is shown density codes is almost proportional to the
that, the use of such an array reduces the growth of the data size (i.e., the numbers
hardware, and causes parallel operations in of digits in a word). This, theoretically,
the modules within the same level. This in removes any limit on the size of each
turn reduces the overall time delay in the structural module within the device.
device by a large amount. A selective use of However, there are some speed-performance
Pre-charge/Pre-discharge scheme also considerations which must be observed in
provides a considerable reduction in the regards to the size of each module, as will
time response of the PR inodules. be described later.

I- Introduction 2) There is no sequential relationship

between the modules in the same level: This
Unlike encoders, priority encoders can indicates that the modules are operationally
have input codes with more than one non-zero independent and can operate simultaneously.
digits, and the output identifies the Therefore, the signal response is limited to
position of the highest priority (the most the delay in one module, which clearly
significant) bit in the input code. There results in a substantial reduction in
are quite a few applications for the overall signal delay through the device.
priority encoders. It can be used to select This property combined with property 1)
one of many events, or operations, which remove any specific boundaries on the size
occur simultaneously with an assigned of each module in the structural level, and
priority. In computer arithmetic, for in fact, we may use other design criteria to
instance, it may be applied as a "first bit select the optimum size of each module.
1 finder"[ll, which is in fact the position
of the most significant bit in the input 3) Another major step in reducing the
data. This provides a considerable time circuit hardware results from the fact that
saving in operations which involve bit the priority resolution section is both
manipulations, such as, shifting and bit- functionally and structurally separated from
wise logic and arithmetic operations. the encoder unit, and as will be discussed
later, the priority resolution circuit is
In conventional priority encoders the the only part of the device which is being
devices are normally implemented in modular modularized. It is shown that only one
form and in multi-level network structure encoder unit is assigned to each level in
for high density ( 8 or 16 bit, and higher) the structure, and that unit is being
codes[2]. This is almost inevitable because, shared by all of the priority resolution
like the carry lookahead adder, the modules in that level. This clearly removes
combinational logic circuit grows any possible redundancies in the hardware
substantially fast for high density operands and provides a substantial saving in chip
(about O(n2 ) , where n is the number of area, as well as faster response.
bits). On the other hand, the signal delay
through the modular network becomes very 11- CMOS Staircase Technique
high for high bit codes. This is because the
enable signal has to propagate through all A s a fundamental and structural block
encoder modules in each level[3]. in this design we first introduce the CMOS
Staircase array. Consider a CMOS inverter,
A new structure and design is presented as shown in Fig. l(a). If we replace the
here for priority encoders. The structure is supply voltage Vdd (strong logic "1") by a
basically constructed of CMOS staircase given signal y, , and apply an input signal
arrays for the priority resolution section x n to the inverter we get an output
followed by an encoder which is partitioned,
in the case of high bit operands. There are
quite clear distinctions, both in term of
structure and technique, and device Now, if we replace Vdd in a second CMOS
operation, between the conventional unit and inverter by yfi-,,provided by the first cell
the priority encoder circuit presented in unit, and apply an input xn-, we obtain
this article., We first specify the major
features of this design, and then describe
the basic structure, and hardware
implemented in this development in the later as shown in Fig. l(b). Similarly, if we
sections. continue adding CMOS inverter units in a
0
' 1990 IEEE
89CH2785-4/90/oooo-ol97$01.CN3
staircase structure for n input signals w e -
get 14

and for y,
ut
- 1 it b e c o m e s

as s h o w n in Fig. l(c). N o w if w e let

“7‘ -
wi = y6. .x; we obtain
w; = xi . 17 x4 . (5)
9: i to
Equation ( 5 ) indicates that the only time
wi = 1 i s w h e n xi = 1 , a n d a l l o t h e r
preceding inputs (xk ) are z e r o , w h i c h is
exactly what a priority resolution function
represents (see Fig. l(c)).

3
-
1 14

aa+J Priority Resolution &+J

au+t
Module (PR- 4) &+r
IPL I arc

.
Fig. 2- Modified Priority Resolution.
O xo r - 111- Priority Encoder sircrlit

* Figure 3 is a schematic representation

of a 32-bit priority encoder implemented in
a t w o level structure. As s h o w n , a total o f
Fig. 1- CMOS Staircase Array. eight 4 - b i t priority resolution modules ( P R -
4) are used in the first level w i t h the
There i s , h o w e v e r , a n inherent signal input signals a4lF3 to a4; , and w i t h the
delay associated w i t h this staircase
s t r u c t u r e , as w i l l be discussed later i n
o u t p u t s i g n a l s b4ir3 t o b4; , for i
J , 6 , . . . , 1 , O . T h e corresponding output pins
-
Section IV. To reduce the delay and i m p r o v e of all eight m o d u l e s are connected to f o u r
the speed-performance of the CMOS Staircase input pins o f a 4 to 2 encoder u n i t ( E N -
circuit w e i m p l e m e n t the following t w o 4/2), and the t w o output signals of the
circuit techniques: i) the pull u p P M O S e n c o d e r , c, and c4 , are in f a c t , the t w o
transistors in the array are replaced by l o w bits o f the final b i t c L u n t , as s h o w n in
transmission g a t e s , as s h o w n in Fig. 2(a). Fig. 3 . A n enable signal 1; controls the
This removes the signal deficiency output of each P R - 4 module; and these
associated w i t h zero pass in each unit. ii) coritrol signals are designed such that only
A p r e - c h a r g e / p r e - d i s c h a r g e (PCPD) technique
one module is enabled at a given t i m e , as
is a d o p t e d f o r a f a s t d i s t r i b u t i o n o f will be described shortly. There is also one
charges through out the circuit nodes (see extra output s i g n a l k; from each module.
Section IV). Figure 2(a) illustrates a n These signals ( k 7 to k, ) form the inputs to
improved design of a 4 -bit priority the 8 - b i t priority resolution u n i t , in the
resolution circuit (the clocking and the second level (PR-8), as illustrated in Fig.
inverted inputs are not shown), and Fig 2(b) 3 . It is i m p o r t a n t to-note that the output
shows the symbolic representation of a 4 - b i t signals f r o m P R - 8 (1, to 1, ) serve t w o
prior ity resolution module . purposes: 1) they provide input signals t o

198
the second 8 to 3 encoder unit (EN-8/3), and first cell to the last one through the pull-
2) they provide the enable signals to the up transmission gates. In PR-4 thera are
eight first level priority resolution three transmission gates to propagate
modules (PR-4). Note a l s o that since only through and in PR-8 we have seven
one output signal, say, 1; = 0 and the rest transmission gates conducting the charges
are all equal to oiie therefore only one PR-4 through the nodes. If the nodes are all pre-
module, in the first level, is engaged in charged we have to discharge the entire
the operation, and the rest seven PR modules eight nodes (in case of PR-8, for example)
are not selected. This control signal, which if the input entry 10000000 is applied, and
acts as a feedback signal, is the key to the if we select not to pre-charge, then we need
reduction of the encoder section to a single to charge all eight nodes for the case when
unit per level, as well as removing the the input entry is 00000000. Clearly, in
sequential dependency of the eight PR-4 both cases the signal delay is quite high.
units in the first level. Fii.ally the output To reduce the propagation delay a
signals from the second enco-ter (EN-8/3), combination of pre-charge and pre-discharge
i.e., c+ ,c3 ,and c2 , decignk-ste the upper scheme is adopted in this design. This
three bits of the final bit ceunt. It is scheme calls for a balance distribution of
a-lso important to observe that the signal charges in the output nodes prior to any
CE, assigned to PR-8, serves as a chip actual data entry. The ideal case is to half
enable signal, and the o u t p i i t signal p from charge (Vdd/2) the output nodes during the
PR-8 acts as a stakiis flag for the input off clock period. In this case any slight
data: that is, p is zero if arid o n l y if the charges being propagated through the output
input data bits are all zero. nodes caused by the input signals, being
applied during the second half clock period,
determines the status of the output signals.
Therefore, the propagation delay, being
directly proportional to the amount of
charge being transferred, is minimized. In
practical situation, however, it is only
possible to selectively pre-charge or pre-
discharge the nodes in the off clock period.
This evidently will cause an even
distribution of charges throughout the
output nodes, once the "on" half clock
period is resumed. Then, apparently, any
extra flow of charge following this initial
charge distribution will p u t each node at
logical " 1 " or "0"state. depending on the
direction of charge flo:4.

In our specific design a pre-setting of

input signals are assigned to each priority
encoder (PR-4 or PR-8) module during the off
clock period. These input signals provide
the desirable pre-charge or pre-discharge
conditions for the circuit nodes. One
selection of pre-setting inputs for PR-4 is
0011 code. This will charge the first two
nodes to logic "1" and discharge the next
two to logic "0".Similar pattern has been
adopted for PR-8 nodule.
V- Si.mulation Results
Fig. 3- A 32-bit Priority Encoder.
The priority encoder circuit is
IV- P r e - c h a r g e / p r ____
e - d i s c ~ ~Tcchiiique
~r~~ developed for.2.5 micron CMOS technology and
it is simulated. The results from simulation
Consider the CMOS staircase structure for two environments, one with pre-
for a four bit priority encoder, shown in charge/pre-discharge (PCBD) scheme and one
Fig. 2(a). For any input "1" assigned to a without, are compared. A s expected, the
unit cell in the staircase structure we get results with PCPD scheme are quite faster,
an output "0" and the time delay through and encouraging. For 4-bit PR-4 module the
the cell is equivalent to the time delay in average time delay is about 2.1 nSec and the
an inverter gate. However, if the input worst case is shown to be 3.2 nSec for b
signal is "0" the situation is different. In ,and 4.1 nSec for k ,output signal (see Fig
this case the pull-up transmission gate 3 ) . In the second level module PR-8 the
conducts, and it causes the signal to average time delay is about 3.7 nSec and 7.8
propagate from the preceding cell, in the .nSec for the worst case. With two more gate
staircase, into the output node (except for delays associated with the overall data path
the top cell which is directly connected to in the circuit, the total time response for
Vdd). There are two cases which the a 32-bit priority resolution is about 15.4
propagation delay is the maximum: first, for nSec. We have to add the time delay
the input signal 0000 and the second for the associated with the 4 to 2 encoder to get
input signal 1000. In both situations the the final time response of a 32-bit priority
signal has to propagate all the way from the encoder.

199
 VI- Conclusion References
A new, fast, and compact priority 113 G.R.L. Sohie, and K.L. Kloker, "A
encoder circuit is developed for 32-bit data Digital Signal Processor with IEEE
words. A technique using CMOS Staircase Floating-point Arithmetic," IEEE Micro,
Array is implemented for constructing the vo1.8, no.6, pp 49-67, 1989.
priority resolution modules (PR-4, and PR- [2] "High-speed CMOS Logic Data Book,"
8). The technique is shown to be very Texas Instrument, Dallas, Texas, 1 9 8 7 .
essential in reducing the hardware [3] M.D. Ercegovac, and T. Lang, "Digital
requirement as well as allowing parallel Systems and Hardware/Software
operation of the modules within the same Algorithms," John Wilev & S o n s . 1985
level. As demonstrated, the later property
substantially reduces the overall time delay ch. 2 & 4.
in the circuit. Finally, a pre-charge/pre- [4] J. Yuan, and C. Svensson, "High-speed
discharge scheme is implemented which CMOS Circuit Technique," IEEE J. Solid-
further reduces the time delay within each State Circuits, vol. S C 2 4 , no. 1, pp
PR module. The design is simulated for 2.5 62-70, January 1 9 8 9 .
micron CMOS Technology, and the results are [5] N. West, and K. Eshraghian, "Principles
reported. of CMOS VLSI Design," Reading, MA:
Addison-Wesley, 1985, ch. 5.