2-Level Page Tables

Virtual Address (VA): 32 bits Virtual Address Space: 232 bytes

Offset or Displacement field in VA: 12 bits Page Size: 212 bytes = 4KB

Virtual Page Number field in VA: 32 - 12 = 20 bits Number of Virtual Pages: 232 / 212 = 220

VA:

VPN OFFSET
20 bits
VPN 12 bits

0 Page of 212 bytes

1

Virtual Address
Space of 220 pages

220 -1
 2-Level Page Tables

PA:

Physical Address (PA): 38 bits Physical Address Space: 238 bytes

Offset or Displacement field in PA: 12 bits Page Size: 212 bytes = 4KB

Page Frame Number field in PA: 38 - 12 = 26 bits Number of Physical Pages: 238 / 212 = 226

PFN OFFSET
26 bits 12 bits

Page Frame of size 212 bytes

0

Physical Address Space

of 226 pages

226 -1
 1 BYTE

0
1 BYTE

1
0
0
1

220 -1
220 -1

Page Table: 220 descriptors

1 descriptor for each Virtual Page 226 -1

VPN can be used as an index into Page Table to find

the descriptor for that page

Single Level Page Table

• Descriptor holds the Page Frame Number (PFN) of the virtual page if
it is in memory

• A presence bit (P) indicates if it is in memory or on the backing device

• Descriptor also contains other administrative and protection bits
– e.g. D (Dirty), U (Used), R (Read), W (Write), E(Execute) etc.

In the example: PFN requires 26 bits

Assume exactly the 6 administrative bits mentioned above

Descriptor is 26+6 = 32 bits or 4 bytes wide.

Size of Page Table = Number of descriptors x Size of descriptor

= 220 x 4 bytes = 4MB
 Two-Level Page Tables

• Break up Page Table into fixed-size blocks of the same size as a page

• In example: Each page is 4KB and Page Table is 4MB

• So we will have 4MB/4KB = 210 = 1024 such blocks

– This collection of blocks that make up the Page Table will be
called the 2nd-level Page Table
– The 1st-Level Page Table will have entries pointing to each block
of the 2nd level Page Table.
– In example: 1024 entries in the 1st-level Page Table

• How many descriptors in each block?

– Each block (or page of the Page Table) will hold:
4KB/4bytes = 1024 descriptors
210 entries: one for each 2nd-Level Page Table
block of 2nd level page table 0
1

210 Descriptors per block

(page) of the Page Table

210 such blocks (pages)

1st-Level Page Table 220 -1 of the Page Table

Page Table: 220 descriptors

1 descriptor for each Virtual Page
Blocked into 210 blocks of 210 descriptors each
210 entries: one for each 2nd-Level Page Table
block of 2nd level page table 0
1

210 Descriptors per block

(page) of the Page Table

210 such blocks (pages)

1st-Level Page Table 220 -1 of the Page Table

Do not need to store the entire 2nd level Page Table as a contiguous array

Do not allocate blocks that have no descriptors

Keep blocks on secondary store and bring in when needed
(mini virtual memory system for the Page Table management)
 210 entries: one for each 2nd-Level Page Table
block of 2nd level page table 0

210 Descriptors per block

(page) of the Page Table

1st-Level Page Table 220 -1

Do not need to store the entire 2nd level Page Table as a contiguous array

Do not allocate blocks that have no descriptors

Keep blocks on secondary store and bring in when needed
(mini virtual memory system for the Page Table management)

Q: What is the actual size of virtual address space being used by the above process?
Each descriptor represents to a 212 = 4KB portion of the address space
2 blocks = 2 x 1024 descriptors imply : 2 x 1024 x 4KB = 8MB address space
 Virtual Memory: 2-level Page Table
10 MSBs (bits 22..31) of the virtual address (PTN) are used to index into the Page Table Directory

Next 10 bits (12 ..21) are used to index the chosen Page Table.

0
PTN (10) PN(10) PD(12)
1
2

Page
1023 Offset
(PD)
PTR 0
1

0 2

1
2 1023 4KB Page

0
1

1022 2
1023 Page Tables
1st-Level Page Table 1023
(Page Table Directory)
 More Details on Page Table Lookup
26 bits

PTN (10) PN(10) PD(12)

PTR

PTR PTN 00

26 10 2

38 bit physical address of desired1st-level Page Table entry

1st Level Page Table and all blocks of the 2nd-level Page Table are
stored at Page Aligned Boundaries i.e. 12 LSBs are zero
 More Details on Page Table Lookup
26 bits

PTN (10) PN(10) PD(12)

Base Address

From selected entry in

1st-level PT

Base Address PN 00

26 10 2

38 bit physical address of desired 2nd-level Page Table entry

 More Details on Page Table Lookup
26 bits

PTN (10) PN(10) PD(12)

PFN

From selected entry in

2nd-level PT

PFN PD

26 12

38 bit physical address of desired memory byte

 Virtual Memory and Caches
Physical cache

Cache locations addressed using

Accessed using translated physical address physical memory addresses
Cache access only after TLB translation
Common case (cache hit) slowed down Physical Address (PA)

BYTE
TAG C ACHE INDEX OFFSET

VA PA
CPU PHYSICAL
TLB
CACHE

VPN PAGE OFFSET PFN PAGE OFFSET

Virtual Address (VA) Physical Address (PA)

Can we avoid latency of translation every memory access?

 Virtual Memory and Caches
Virtual cache
Accessed using the virtual address directly

VPN PAGE OFFSET

Virtual Address (VA)

PA
TLB

VA
CPU

PFN PAGE OFFSET

VIRTUAL
Virtual Address (VA) CACHE Physical Address (PA)
Cache locations addressed using
TAG C ACHE INDEX
BYTE
OFFSET
virtual memory addresses
 Virtual Memory and Caches
Virtual Cache

Accessed using virtual addresses

(+) Address translation (TLB lookup) in parallel with cache lookup
Access TLB for protection information unless information replicated in cache

(-) Context switch must invalidate all cache entries

Every process has the same virtual address space 0 … 2n -1
How do you distinguish a virtual address of some process from the
same virtual address of a different process ?

Use processor identifiers (PIDs) as additional field to tag cache blocks

 Virtual Memory and Caches
Virtual Cache
VA = 011 0100 PA = 00 0100
VPN Physical
0
PFN
Memory
1
VA = 011 1110 PA = 00 1110
2
TAG 4
3 0
0
16
4 01101 14
5 3 10101
6 01111
7 10111
1
Page Table Process 0
Virtual Cache
Direct Mapped size 4 Blocks

2
Assumes cache block VA = 101 0101 PA = 11 0101
size of w bytes
5
3
VA = 101 1111 PA = 11 1111 15

w BYTES
 Virtual Memory and Caches
Virtual Cache
VA = 011 0100
VPN Physical
0
PFN
Memory
1
VA = 011 1110
2
TAG 4
3 0
0
16
4 01101 14
5 3 10101
6 01111
7 10111 4
1
Page Table Process 0
Virtual Cache 14

0 5
1 2
2 15
1
VA = 101 0101
3
4 5
2
5 3
6 VA = 101 1111 15
7
Page Table Process 1
Process 1 will access cached data of Process 0
 Virtual Memory and Caches
Virtual Cache

VPN Physical
0
PFN
Memory
1
2
V TAG 4
3 0
0
16
4 I 01101 14
5 3 I 10101
6 I 01111
7 I 10111 4
1
Page Table Process 0
Virtual Cache 14

0 Solution 1: Invalidate all cache 5

1 blocks on a context switch 2
2 15
3 1 Cache blocks that may have
4 survived (i.e were not evicted) by 5
2
5 swapped-in process are wastefully 3
6
invalidated. 15
7
Page Table Process 1
Cold cache on resumption
 Virtual Memory and Caches
Virtual Cache

VPN Physical
0
PFN
Memory
1
2
TAG 4
3 0
PROCESS ID
0
16
4 0 01101 14
5 3 0 10101
6 0 01111
7 0 10111 4
1
Page Table Process 0
Virtual Cache 14

0 Solution 2: Add a process id field 5

1 as a part of the tag to identify the 2
2 process whose blocks are in cache 15
3 1
4 5
2
5 3
6 15
7
Page Table Process 1
 Virtual Memory and Caches

Virtual Cache : Accessed using virtual addresses

(-) Aliases:Different names for the same physical object

Different virtual address but same physical address
May result in multiple inconsistent copies of the data in the cache

:
 Virtual Memory and Caches
Virtual Cache

VPN Virtual Cache Physical

0 TAG
PFN
Memory
1 000
2 001 11 0 1 4
3 010
0
4 011
1
5 100
6 0 101 01
7
2
110
Page Table Process 0 111

VA: 011 01 PA: 00 01

VA: 110 01 PA: 00 01
Note: This can only happen if the number of
blocks in any way of the cache is greater 2 cached copies of same physical
than the number of blocks in a virtual page. location (in different cache locations)
For aliasing to occur: The cache page size must exceed the virtual page size