1.

Half adder

module halfadder(a,b,cout,sum);
input [1:0]a,b;
output [1:0]sum;
output cout;
assign cout = a & b;
assign sum = a ^ b;
endmodule

module halfadder_tb;

reg [1:0]a_t,b_t;
wire [1:0]sum_t;
wire cout_t;

halfadder h1(.a(a_t), .b(b_t), .cout(cout_t), .sum(sum_t));

initial begin
a_t=2'b00;b_t=2'b00;
#50 a_t=2'b00;b_t=2'b01;
#50 a_t=2'b01;b_t=2'b11;
#50 a_t=2'b11;b_t=2'b10;
$finish;
end

endmodule
2.2:1 Mux
module mux21(a,b,s,out);
input wire [2:0]a,b;
input wire s;
output reg [2:0]out;

always @(a or b or s)
begin

if(s==1'b1)
out=b;
else
out=a;

end

endmodule
module mux21_tb;
reg [2:0]a_t,b_t;
wire [2:0]out_t;
reg s_t;
mux21 m1(.a(a_t), .b(b_t), .s(s_t), .out(out_t));
initial begin
a_t=3'b000;b_t=3'b000;s_t=1'b0;
#50 a_t=3'b001;b_t=3'b010;s_t=1'b0;
#50 a_t=3'b100;b_t=3'b011;s_t=1'b1;
#50;
$finish;
end
endmodule

3.Full Adder
module fulladder(input wire [2:0] a, b, cin, output reg [2:0]s, output reg cout);

always @(a or b or cin)

begin

case (a | b | cin)
3'b000: begin s = 0; cout = 0; end
3'b001: begin s = 1; cout = 0; end
3'b010: begin s = 1; cout = 0; end
 3'b011: begin s = 0; cout = 1; end
3'b100: begin s = 1; cout = 0; end
3'b101: begin s = 0; cout = 1; end
3'b110: begin s = 0; cout = 1; end
3'b111: begin s = 1; cout = 1; end
endcase

end

endmodule
module fulladder_tb;

reg [2:0]a_t,b_t,cin_t;
wire [2:0]s_t;
wire cout_t;

fulladder f1(.a(a_t), .b(b_t), .cin(cin_t), .s(s_t), .cout(cout_t));

initial begin
a_t=3'b000;b_t=3'b000;cin_t=3'b000;
#50 a_t=3'b000;b_t=3'b010;cin_t=3'b100;
#50 a_t=3'b010;b_t=3'b110;cin_t=3'b111;
#50 a_t=3'b011;b_t=3'b110;cin_t=3'b101;
#50;
$finish;
end

endmodule
4.Half Subtractor
module halfsubtractor(a,b,diff,bor);
input [1:0]a,b;
output [1:0]diff;
output bor;
assign diff=a ^ b;
assign bor= (~a & b);
endmodule

module halfsubtractor_tb;
reg [1:0]a_t,b_t;
wire [1:0]diff_t;
wire bor_t;
halfsubtractor hs1(.a(a_t), .b(b_t), .diff(diff_t), .bor(bor_t));

initial begin
a_t=2'b00;b_t=2'b00;
#50 a_t=2'b00;b_t=2'b01;
#50 a_t=2'b11;b_t=2'b01;
#50 a_t=2'b11;b_t=2'b10;
#50
$finish;
end

endmodule

5.Full adder cum Subtractor

module fullcsub(a,b,c0,s0,co);
input [2:0]a,b;
input c0;
output [2:0]s0;
output co;
wire [2:0]b1;

assign b1= b ^ c0;

assign s0 = c0 ^ (a ^ b1);
assign co = (a & b1) | (b1 & c0) | (a & c0);
endmodule
module fullcsub_tb;

reg [2:0]a_t,b_t;
reg c0_t;
wire [2:0]s0_t;
wire co_t;

fullcsub f1(.a(a_t), .b(b_t), .c0(c0_t), .s0(s0_t), .co(co_t));

initial begin
a_t=3'b000;b_t=3'b000;c0_t=1'b0;
#50 a_t=3'b000;b_t=3'b010;c0_t=1'b0;
#50 a_t=3'b010;b_t=3'b110;c0_t=1'b1;
#50 a_t=3'b011;b_t=3'b110;c0_t=1'b1;
#50;
$finish;
end

endmodule
6.Binary to Gray Code Convertor
module btg(b,g);
input [3:0]b;
output [3:0]g;
assign g[3]=b[3];
assign g[2]=b[3] ^ b[2];
assign g[1]=b[2] ^ b[1];
assign g[0]=b[1] ^ b[0];
endmodule

module btg_tb;
reg [3:0]b_t;
wire [3:0]g_t;
btg bg1(.b(b_t), .g(g_t));
initial begin
b_t=4'b0000;
#50 b_t=4'b0100;
#50 b_t=4'b0110;
#50 b_t=4'b1100;
#50 b_t=4'b0111;
#50 b_t=4'b1111;
#50 b_t=4'b1101;
#50;
$finish;
end

endmodule
7.Gray to Binary Code Convertor
module gtb(g,b);
input [3:0]g;
output [3:0]b;
assign b[3]=g[3];
assign b[2]=g[3] ^ g[2];
assign b[1]=b[2] ^ g[1];
assign b[0]=b[1] ^ g[0];
endmodule

module gtb_tb;
reg [3:0]g_t;
wire [3:0]b_t;
gtb gb1(.g(g_t), .b(b_t));

initial begin
g_t=4'b0000;
#50 g_t=4'b0100;
#50 g_t=4'b0110;
#50 g_t=4'b1100;
#50 g_t=4'b0111;
#50 g_t=4'b1111;
#50 g_t=4'b1101;
#50;
$finish;
end

endmodule
8.2:4 Decoder
module dec24(a,en,out);
input [1:0]a;
input en;
output reg [3:0]out;
always @(a,en)
begin
if(en==1'b1)begin
case(a)
2'b00:out=4'b0001;
2'b01:out=4'b0010;
2'b10:out=4'b0100;
2'b11:out=4'b1000;
endcase
end
else begin
out=4'b0000;
end
end
endmodule
module dec24_tb;
reg [1:0]a_t;
reg en_t;
wire [3:0]out_t;
dec24 dec1(.a(a_t), .en(en_t), .out(out_t));
initial begin
a_t=2'b00;
#50 a_t=2'b01;en_t=1'b0;
#50 a_t=2'b11;en_t=1'b1;
#50 a_t=2'b10;en_t=1'b1;
#50;
$finish;
end

endmodule
9.3:8 Decoder
module dec38(a,en,out);
input [2:0] a;
input en;
output reg [7:0] out;
always @(a,en)
begin
if(en==1'b1)begin
case (a)
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
 default : out = 8'b00000000;
endcase
end
else begin
out=8'b00000000;
end
end

endmodule
module dec38_tb;
reg [2:0]a_t;
reg en_t;
wire [7:0]out_t;
dec38 de31(.a(a_t), .en(en_t), .out(out_t));
initial begin
a_t=3'b000;en_t=1'b0;
#50 a_t=3'b001;en_t=1'b0;
#50 a_t=3'b110;en_t=1'b1;
#50 a_t=3'b111;en_t=1'b1;
#50;
$finish;
end

endmodule
10.Full Adder using Conditional operator
module fullacon(a,b,c,sum,carry);
input a,b,c;
output sum;
output carry;
wire b1;
assign b1= b ^ 1;
assign sum= c?(a?b:b1):(a?b1:b);
assign carry= a?(b?1:c):(b?c:0);
endmodule
module fullacon_tb;
reg a_t,b_t,c_t;
wire sum_t;
wire carry_t;
fullacon f2(.a(a_t), .b(b_t), .c(c_t), .sum(sum_t), .carry(carry_t));

initial begin
a_t=1'b0;b_t=1'b0;c_t=1'b0;
#50 a_t=1'b0;b_t=1'b1;c_t=1'b1;
#50 a_t=1'b1;b_t=1'b1;c_t=1'b1;
#50 a_t=1'b1;b_t=1'b0;c_t=1'b1;
#50;
$finish;
end

endmodule

11.Full Adder using the truth table of Full adder (Structural Model)
module fullstruct(a,b,cin,sum,cout);
input a,b,cin;
output wire sum,cout;
wire s1,c1,c2,c3;
xor(s1,a,b);
xor(sum,s1,cin);
and(c1,a,b);
and(c2,b,cin);
and(c3,a,cin);
or(cout,c1,c2,c3);
endmodule
module fullstruct_tb;
reg a_t,b_t,cin_t;
wire sum_t;
wire cout_t;
fullstruct f2(.a(a_t), .b(b_t), .cin(cin_t), .sum(sum_t), .cout(cout_t));

initial begin
a_t=1'b0;b_t=1'b0;cin_t=1'b0;
#50 a_t=1'b0;b_t=1'b1;cin_t=1'b1;
#50 a_t=1'b1;b_t=1'b1;cin_t=1'b1;
#50 a_t=1'b1;b_t=1'b0;cin_t=1'b1;
#50;
$finish;
end

endmodule
12.2:1 Mux using Conditional Operator
module mux21(a,b,s,out);
input [2:0]a,b;
output[2:0]out;
input s;
assign out= s?b:a;
endmodule

module mux21_tb;
reg [2:0]a_t,b_t;
wire [2:0]out_t;
reg s_t;
mux21 m1(.a(a_t), .b(b_t), .s(s_t), .out(out_t));
initial begin
a_t=3'b000;b_t=3'b000;s_t=1'b0;
#50 a_t=3'b001;b_t=3'b010;s_t=1'b0;
#50 a_t=3'b100;b_t=3'b011;s_t=1'b1;
#50;
$finish;
end
endmodule

13.4:1 Mux using Conditional Operator

module mux4cond(a,b,c,d,s0,s1,out);
input [2:0]a,b,c,d;
input s0,s1;
output [2:0]out;
assign out=s1?(s0?d:c):(s0?b:a);
endmodule

module mux4cond_tb;
reg [2:0] a_t,b_t,c_t,d_t;
reg s0_t,s1_t;
wire [2:0]out_t;
mux4cond m1(.a(a_t), .b(b_t), .c(c_t), .s0(s0_t), .s1(s1_t), .out(out_t));
initial begin
a_t=3'b000;b_t=3'b000;c_t=3'b000;d_t=3'b000;s0_t=1'b0;s1_t=1'b0;
#50 a_t=3'b011;b_t=3'b000;c_t=3'b000;d_t=3'b000;s0_t=1'b0;s1_t=1'b1;
#50 a_t=3'b010;b_t=3'b001;c_t=3'b010;d_t=3'b100;s0_t=1'b1;s1_t=1'b0;
#50 a_t=3'b000;b_t=3'b011;c_t=3'b010;d_t=3'b101;s0_t=1'b0;s1_t=1'b1;
#50 a_t=3'b010;b_t=3'b001;c_t=3'b110;d_t=3'b001;s0_t=1'b0;s1_t=1'b0;
#50;
$finish;
end

endmodule

14.4:1 Mux using Truth Table

module mux4c( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

reg q;
wire[1:0] select;
wire[3:0] d;

always @( select or d)
begin
q= ( ~select[0] & ~select[1] & d[0] )
| ( select[0] & ~select[1] & d[1] )
| ( ~select[0] & select[1] & d[2] )
| ( select[0] & select[1] & d[3] );
end

endmodule
15.4Bit Full Adder using Concatenation
module fulladder4conc(a,b,cin,sum,cout);
input [3:0]a,b,cin;
output [3:0]sum;
output cout;
assign {cout, sum} = a + b + cin;
endmodule

module fulladder4conc_tb;

reg [3:0]a_t,b_t,cin_t;
wire [3:0]sum_t;
wire cout_t;

fulladder4conc f1(.a(a_t), .b(b_t), .cin(cin_t), .sum(sum_t), .cout(cout_t));

initial begin
a_t=4'b0000;b_t=4'b0000;cin_t=4'b0000;
#50 a_t=4'b1000;b_t=4'b0110;cin_t=4'b1010;
#50 a_t=4'b0110;b_t=4'b1101;cin_t=4'b1111;
#50 a_t=4'b0111;b_t=4'b1100;cin_t=4'b0101;
#50;
$finish;
end
endmodule
16.1:4 DEMUX in Structural Model
module demux4struct(in,d0,d1,d2,d3,s0,s1);
input in,s0,s1;
output d0,d1,d2,d3;
and a1(d0,in,s0,s1);
and a2(d1,in,(~s0),s1);
and a3(d2,in,s0,(~s1));
and a4(d3,in,(~s0),(~s1));
endmodule
module demucstruct_tb;
reg in_t,s0_t,s1_t;
wire d0_t,d1_t,d2_t,d3_t;
demux4struct dem(.in(in_t), .d0(d0_t), .d1(d1_t), .d2(d2_t), .d3(d3_t), .s0(s0_t), .s1(s1_t));

initial begin
in_t=1'b0;s0_t=1'b0;s1_t=1'b0;

#50 in_t=1'b1;s0_t=1'b1;s1_t=1'b0;
#50 in_t=1'b1;s0_t=1'b0;s1_t=1'b0;
#50 in_t=1'b0;s0_t=1'b0;s1_t=1'b1;
#50 in_t=1'b1;s0_t=1'b1;s1_t=1'b1;
#50;
$finish;
end

endmodule

17.4BitFull Adder using Named Association

module fulladder(X, Y, Ci, S, Co);
input X, Y, Ci;
output S, Co;
wire w1,w2,w3;
xor G1(w1, X, Y);
xor G2(S, w1, Ci);
and G3(w2, w1, Ci);
 and G4(w3, X, Y);
or G5(Co, w2, w3);
endmodule
module rippe_adder(X_r, Y_r, S_r, Co_r);
input [3:0] X_r, Y_r;
output [3:0] S_r;
output Co_r;
wire w1, w2, w3;

fulladder u1(.X(X_r[0]), .Y(Y_r[0]), .Ci(1'b0), .S(S_r[0]), .Co(w1));

fulladder u2(.X(X_r[1]), .Y(Y_r[1]), .Ci(w1), .S(S_r[1]), .Co(w2));
fulladder u3(.X(X_r[2]), .Y(Y_r[2]), .Ci(w2), .S(S_r[2]), .Co(w3));
fulladder u4(.X(X_r[3]), .Y(Y_r[3]), .Ci(w3), .S(S_r[3]), .Co(Co_r));
endmodule
18.8:1 MUX using 2:1 MUX
module mux(y,d0,d1,s);
output [2:0]y;
input [2:0]d0,d1;
input s;
assign y=s?d1:d0;
endmodule
module mux8using2(out,a,b,c,d,e,f,g,h,s0,s1,s2);
output [2:0]out;
input [2:0]a,b,c,d,e,f,g,h;
input s0,s1,s2;
wire [2:0] w,x,y,z,i,j;
mux m1(w,a,b,s0);
mux m2(x,c,d,s0);
mux m3(y,e,f,s0);
mux m4(z,g,h,s1);
mux m5(i,w,x,s1);
mux m6(j,y,z,s1);
mux m7(out,i,j,s2);
endmodule

module mux8using2_tb;
reg [2:0] a_t,b_t,c_t,d_t,e_t,f_t,g_t,h_t;
reg s0_t,s1_t,s2_t;
wire [2:0] out_t;
mux8using2 mm1(.out(out_t), .a(a_t), .b(b_t), .c(c_t), .d(d_t), .e(e_t), .f(f_t), .g(g_t),
.h(h_t), .s0(s0_t), .s1(s1_t), .s2(s2_t));
initial begin
a_t=3'b000;b_t=3'b000;c_t=3'b000;d_t=3'b000;e_t=3'b000;f_t=3'b000;g_t=3'b000;h_t=3'b0
00;s0_t=1'b0;s1_t=1'b0;s2_t=1'b0;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b0;s1_t=1'b0;s2_t=1'b1;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b0;s1_t=1'b1;s2_t=1'b0;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b0;s1_t=1'b1;s2_t=1'b1;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b1;s1_t=1'b0;s2_t=1'b0;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b1;s1_t=1'b0;s2_t=1'b1;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b1;s1_t=1'b1;s2_t=1'b0;
#50
a_t=3'b000;b_t=3'b001;c_t=3'b010;d_t=3'b100;e_t=3'b100;f_t=3'b110;g_t=3'b110;h_t=3'b1
11;s0_t=1'b1;s1_t=1'b1;s2_t=1'b1;
#50;
$finish;
end

endmodule
19.4Bit Comparator
module comparator(a,b,eq,lt,gt);

input [3:0] a,b;

output reg eq,lt,gt;

always @(a,b)
begin
if (a==b)
begin
eq = 1'b1;
lt = 1'b0;
gt = 1'b0;
end
else if (a>b)
begin
eq = 1'b0;
lt = 1'b0;
gt = 1'b1;
end
else
begin
eq = 1'b0;
lt = 1'b1;
gt = 1'b0;
end
end
endmodule

module comparator_tb;
reg [3:0] a_t,b_t;
wire eq_t,lt_t,gt_t;
comparator c1(.a(a_t),.b(b_t),.eq(eq_t),.lt(lt_t),.gt(gt_t));
initial
begin
a_t = 4'b1100;
b_t = 4'b1100;
#50;

a_t = 4'b0100;
b_t = 4'b1100;
 #50;

a_t = 4'b1111;
b_t = 4'b1100;
#50;

a_t = 4'b0000;
b_t = 4'b0000;
#50;
$finish;
end
endmodule
20.4Bit Full Adder using Only NAND gates
module fa_nand( input a,input b,input cin,output sum,output carry);
wire w1,w2,w3,w4,w5,w6,w7;
nand n1(w1,a,b);
nand n2(w3,a,w1);
nand n3(w2,w1,b);
nand n4(w4,w3,w2);
nand n5(w5,w4,cin);
nand n6(w6,w4,w5);
nand n7(w7,w5,cin);
nand n8(carry,w5,w1);
nand n9(sum,w6,w7);
endmodule
module adder4nand(a,b,sum,carry);
input [3:0]a,b;

output [3:0]sum;
output carry;
wire c1,c2,c3;
fa_nand f1(a[0],b[0],1'b0,sum[0],c1);
fa_nand f2(a[1],b[1],c1,sum[1],c2);
fa_nand f3(a[2],b[2],c2,sum[2],c3);
fa_nand f4(a[3],b[3],c3,sum[3],carry);
endmodule

module adder4nand_tb;
reg [3:0]a_t,b_t;

wire [3:0]sum_t;
wire carry_t;
adder4nand ad1(.a(a_t), .b(b_t), .sum(sum_t), .carry(carry_t));
initial
begin
a_t=4'b0001;b_t=4'b1001;
#50 a_t=4'b0001;b_t=4'b1001;
#50 a_t=4'b1101;b_t=4'b1111;
#50 a_t=4'b0101;b_t=4'b1011;
#50 a_t=4'b1001;b_t=4'b1111;
#50;
$finish;
end
endmodule

21.8:1 MUX in Behavioral Modeling

module mux8behav(out, D0, D1, D2, D3, D4, D5, D6, D7, S);
input wire [2:0]D0, D1, D2, D3, D4, D5, D6, D7;
input wire [2:0] S;
output reg [2:0]out;
always@(*)
begin
case(S)
3'b000: out=D0;
3'b001: out=D1;
3'b010: out=D2;
3'b011: out=D3;
3'b100: out=D4;
3'b101: out=D5;
3'b110: out=D6;
3'b111: out=D7;
default: out=3'b000;
endcase
end
endmodule

module mux8behav_tb;
reg [2:0]D0_t, D1_t, D2_t, D3_t, D4_t, D5_t, D6_t, D7_t;
wire [2:0]out_t;
reg [2:0]S_t;
mux8behav mm(.out(out_t),.D0(D0_t), .D1(D1_t), .D2(D2_t), .D3(D3_t), .D4(D4_t), .D5(D5_t),
.D6(D6_t), .D7(D7_t), .S(S_t));
initial
begin
D0_t=3'b000; D1_t=3'b011; D2_t=3'b111; D3_t=3'b101; D4_t=3'b110; D5_t=3'b001; D6_t=3'b011;
D7_t=3'b100;S_t=3'b100;
#50 D0_t=3'b000; D1_t=3'b011; D2_t=3'b111; D3_t=3'b101; D4_t=3'b110; D5_t=3'b001; D6_t=3'b011;
D7_t=3'b100;S_t=3'b110;
#50 D0_t=3'b000; D1_t=3'b011; D2_t=3'b111; D3_t=3'b101; D4_t=3'b110; D5_t=3'b001; D6_t=3'b011;
D7_t=3'b100;S_t=3'b101;
#50 D0_t=3'b000; D1_t=3'b011; D2_t=3'b111; D3_t=3'b101; D4_t=3'b110; D5_t=3'b001; D6_t=3'b011;
D7_t=3'b100;S_t=3'b111;
#50 D0_t=3'b000; D1_t=3'b011; D2_t=3'b111; D3_t=3'b101; D4_t=3'b110; D5_t=3'b001; D6_t=3'b011;
D7_t=3'b100;S_t=3'b010;
#50;
$finish;
end
endmodule

22.4:1 MUX using Case

module mux41tt( a, b, c, d, s, out);

input wire [2:0]a, b, c, d;

input wire [1:0]s;
output reg [2:0]out;

always @ (a or b or c or d or s)
begin

case (s)
0 : out <= a;
1 : out <= b;
2 : out <= c;
3 : out <= d;
endcase

end

endmodule
module mux4tt_tb;
reg [2:0] a_t,b_t,c_t,d_t;
reg [1:0]s_t;
wire [2:0]out_t;
mux41tt m1(.a(a_t), .b(b_t), .c(c_t),.d(d_t), .s(s_t), .out(out_t));
initial begin
a_t=3'b000;b_t=3'b000;c_t=3'b000;d_t=3'b000;s_t=2'b00;
#50 a_t=3'b011;b_t=3'b000;c_t=3'b000;d_t=3'b000;s_t=2'b00;
#50 a_t=3'b010;b_t=3'b001;c_t=3'b010;d_t=3'b100;s_t=2'b11;
#50 a_t=3'b000;b_t=3'b011;c_t=3'b010;d_t=3'b101;s_t=2'b10;
#50 a_t=3'b010;b_t=3'b001;c_t=3'b110;d_t=3'b001;s_t=2'b01;
#50;
$finish;
end
23.BCD to Seven Segment Display
module sevensegment(clk,bcd,seven);

input [3:0] bcd;

input clk;
output reg [6:0] seven;

always @(posedge clk)

begin
case (bcd)
4'b0000 : begin seven = 7'b1111110; end
4'b0001 : begin seven = 7'b0110000; end
4'b0010 : begin seven = 7'b1101101; end
4'b0011 : begin seven = 7'b1111001; end
4'b0100 : begin seven = 7'b0110011; end
4'b0101 : begin seven = 7'b1011011; end
4'b0110 : begin seven = 7'b1011111; end
4'b0111 : begin seven = 7'b1110000; end
 4'b1000 : begin seven = 7'b1111111; end
4'b1001 : begin seven = 7'b1110011; end
default : begin seven = 7'b0000000; end
endcase
end
endmodule

24.ALU
module alu(input [7:0] A,B,input [3:0] alusel,output [7:0] out,output carry);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign out = ALU_Result;
assign tmp = {1'b0,A} + {1'b0,B};
assign carry = tmp[8];
always @(*)
begin
case(alusel)
 4'b0000: ALU_Result = A + B ;
4'b0001: ALU_Result = A - B ;
4'b0010: ALU_Result = A * B;
4'b0011: ALU_Result = A/B;
4'b0100: ALU_Result = A<<1;
4'b0101: ALU_Result = A>>1;
4'b0110: ALU_Result = {A[6:0],A[7]};
4'b0111: ALU_Result = {A[0],A[7:1]};
4'b1000: ALU_Result = A & B;
4'b1001: ALU_Result = A | B;
4'b1010: ALU_Result = A ^ B;
4'b1011: ALU_Result = ~(A | B);
4'b1100: ALU_Result = ~(A & B);
4'b1101: ALU_Result = ~(A ^ B);
4'b1110: ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end

endmodule
module alu_tb;
reg [7:0]A_t,B_t;
reg [3:0]alusel_t;
wire [7:0]out_t;
wire carry_t;
alu a1(.A(A_t), .B(B_t), .alusel(alusel_t), .out(out_t), .carry(carry_t));
initial
begin
A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0000;
#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0001;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0010;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0011;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0100;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0101;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0110;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b0111;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1000;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1001;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1010;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1011;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1100;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1101;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1110;

#100;A_t=8'b01101010;
B_t=8'b00111011;
alusel_t=4'b1111;
#100;
$finish;
end
endmodule
25.1:4 DEMUX using Behavioral Modeling
module demux4b (output reg [3:0] Y, input [1:0] A, input din);
always @(Y, A) begin
case (A)
2'b00 : begin Y[0] = din; Y[3:1] = 0; end
2'b01 : begin Y[1] = din; Y[0] = 0; end
2'b10 : begin Y[2] = din; Y[1:0] = 0; end
2'b11 : begin Y[3] = din; Y[2:0] = 0; end
endcase
end
endmodule

module demux4b_tb;
reg [1:0]A_t;
reg din_t;
wire [3:0]Y_t;
demux4b d22(.Y(Y_t), .A(A_t), .din(din_t));
initial
begin
A_t=2'b00;din_t=1'b1;
#50 A_t=2'b01;din_t=1'b1;
#50 A_t=2'b10;din_t=1'b1;
#50 A_t=2'b11;din_t=1'b1;
#50;
$finish;
end
endmodule

26.D-Flipflop
module flipd(d,clk,q);
input wire d;
input wire clk;
output reg q;
always @(posedge clk)
begin
q <= d;
end
endmodule

module flipd_tb;
reg d_t,clk_t;
wire q_t;
flipd dd1(d_t,clk_t,q_t);
initial begin
clk_t=0;
forever #10 clk_t = ~clk_t;
end
initial begin
d_t <=0;
#50
d_t <=1;
#50
d_t <=0;
#50;
$finish;
end
endmodule
27.D- Flip Flop with Asynchronous Reset
module dffasynres(clk,d,reset,q);
input clk,d,reset;
output q;
reg q;
always@(posedge clk or posedge reset)
begin
if(reset)
q<=0;
else
q<=d;
end
endmodule

module dffsynrest_tb;
reg clk_t,d_t,reset_t;
wire q_t;
dffasynres ww(clk_t,d_t,reset_t,q_t);
initial begin
clk_t=0;
forever#10 clk_t=~clk_t;
end
initial begin
d_t<=0;reset_t=0;
#50 d_t<=0;reset_t=1;
#50 d_t<=1;reset_t=0;
#50 d_t<=1;reset_t=1;
#50;
$finish;
end
endmodule
28.D- Flip Flop with Asynchronous Preset
module dffasynpres(clk,d,preset,q);
input clk,d,preset;
output q;
reg q;
always@(posedge clk or negedge preset)
begin
if(preset==0)
q<=1;
else
q<=d;
end
endmodule
module dffasynprest_tb;
reg clk_t,d_t,preset_t;
wire q_t;
dffasynpres ww(clk_t,d_t,preset_t,q_t);
initial begin
clk_t=0;
forever#10 clk_t=~clk_t;
end
initial begin
d_t<=0;preset_t=0;
#50 d_t<=0;preset_t=1;
#50 d_t<=1;preset_t=0;
#50 d_t<=1;preset_t=1;
#50;
$finish;
end
endmodule

29.D- Flip Flop with Asynchronous Reset and Preset

module dffasynrsnpres(clk,d,preset,reset,q);
input clk,d,preset,reset;
output q;
reg q;
always@(posedge clk or negedge preset or posedge reset)
begin
if(preset==0)
q<=1;
else if(reset)
q<=0;
else
q<=d;
end
endmodule
module dffasynrsnpres_tb;
reg clk_t,d_t,preset_t,reset_t;
wire q_t;
dffasynrsnpres ww(clk_t,d_t,preset_t,reset_t,q_t);
initial begin
clk_t=0;
forever#10 clk_t=~clk_t;
end
initial begin
d_t<=0;preset_t=0;reset_t=1;
#50 d_t<=0;preset_t=1;reset_t=1;
#50 d_t<=0;preset_t=0;reset_t=1;
#50 d_t<=0;preset_t=1;reset_t=0;
#50 d_t<=1;preset_t=1;reset_t=1;
#50 d_t<=1;preset_t=0;reset_t=0;
#50 d_t<=1;preset_t=1;reset_t=0;
#50 d_t<=1;preset_t=0;reset_t=1;
#50;
$finish;
end
endmodule
30.D-Latch with Data and Enable

module dlatch(data,en,q);
input data,en;
output q;
reg q;
always @ (en or data)
if(en)
begin
q<=data;
end
endmodule
module dlatch_tb;
reg data_t,en_t;
wire q_t;
dlatch uu(data_t,en_t,q_t);
initial
begin
en_t=1;data_t=0;
#50 en_t=0;data_t=0;
#50 en_t=0;data_t=1;
#50 en_t=1;data_t=1;
#50;
$finish;
end
endmodule

31.4Bit Up Counter
module upcounter(clk,rst,out);
input clk;
input rst;
output reg[3:0] out;
always @(posedge clk)
begin
if(rst==0)
out<=0;
else
out<=out+1;
end
endmodule
module upcount_tb;
reg clk_t,rst_t;
wire [3:0]out_t;
upcounter gg(clk_t,rst_t,out_t);
always #10 clk_t=~clk_t;
initial
begin
clk_t<=0;
rst_t<=0;
#50 rst_t<=1;
#50 rst_t<=1;
#50 rst_t<=1;
#50 rst_t<=1;
#50;
$finish;
end
endmodule
32.4Bit Up- Down Counter
module updown(out,up_down,clk,rst);
output [3:0] out;

input up_down,clk,rst;
reg [3:0] out;
always @(posedge clk)
if (rst==0)
begin
out <=4'b0000;
end
else if (up_down)
begin
out<=out+1;
end
else
begin
out<=out-1;
end
endmodule
module updown_tb;
wire [3:0] out_t;

reg up_down_t,clk_t,rst_t;
updown hh(out_t,up_down_t,clk_t,rst_t);

always #10 clk_t=~clk_t;

initial
begin
clk_t<=0;
rst_t<=0;
up_down_t=0;
#50 rst_t<=1;up_down_t=0;
#50 rst_t<=1;up_down_t=0;
#50 rst_t<=1;up_down_t=0;
#50 rst_t<=1;up_down_t=1;
#50 rst_t<=1;up_down_t=1;
#50 rst_t<=1;up_down_t=1;
#50 rst_t<=1;up_down_t=1;
#50;
$finish;
end
endmodule

33.4-Bit Ring Counter

module ring(clk,rst,out);
input clk,rst;
output [3:0]out;
reg [3:0]temp;
always @(posedge clk,rst)
begin
if (rst==1'b1)
begin
temp=4'b0001;
end
else if(clk==1'b1)
begin
temp = {temp[2:0],temp[3]};
end
end
assign out=temp;
endmodule
module ring_tb;
reg clk_t,rst_t;
wire [3:0]out_t;
ring rr(clk_t,rst_t,out_t);
initial clk_t=0;
always
#10 clk_t=~clk_t;
initial begin
rst_t=1;
#50
rst_t=0;
#50;
$finish;
end
endmodule
34.Johnson Counter
module johnson(clk,rst,out);
input clk,rst;
output [3:0]out;
reg [3:0]temp;
always @(posedge clk or rst)
begin
if(rst==1'b1)
begin
temp =4'b0000;
end
else if(clk==1'b1)
begin
temp={temp[2:0],~temp[3]};
end
end
assign out=temp;
endmodule
module johnson_tb;
reg clk_t,rst_t;
wire [3:0]out_t;
johnson uu(clk_t,rst_t,out_t);
initial clk_t=0;
always
#10 clk_t=~clk_t;
initial begin
rst_t=1;
#50
rst_t=0;
#50;
$finish;
end
endmodule
35.n-Bit Shift Register
module nbit #(parameter bit=4)(d,clk,en,lr,rst,out);
input d,clk,en,lr,rst;
output reg [bit-1:0]out;
always @(posedge clk)
if(rst==0)
out<=0;
else
begin
if(en)
case(lr)
0:out<={out[bit-2:0],d};
1:out<={d,out[bit-1:1]};
endcase
else
out<=out;
end
endmodule
module nbit_tb;
parameter bit_t=4;
reg d_t,clk_t,en_t,lr_t,rst_t;
wire [bit_t-1:0]out_t;
nbit hhh(d_t,clk_t,en_t,lr_t,rst_t,out_t);
always #10 clk_t=~clk_t;
initial begin
clk_t<=0;
en_t<=0;
lr_t<=0;
rst_t<=0;
d_t<=1'b1;
#50; rst_t<=1;en_t<=1;
#100; lr_t<=1;
#100;lr_t<=0;d_t=1'b0;
#100;
$finish;
end
endmodule

36.Siso,Piso,Pipo,Sipo