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Real-time image histogram equalization using FPGA

Article  in  Proceedings of SPIE - The International Society for Optical Engineering · August 1998
DOI: 10.1117/12.319719

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 Real-time Image Histogram Equalization Using FPGA
LI Xiying1 NT Guoqiang CUT Yanmei PU Tian ZHONG Yanli
Beijing Institute of Technology
Dept ofElectro-Optical Enneerin& Beijint 100081 China

ABSTRACT
A new hardware hnp1ementa1ion of histogram equalization by means ofField Programmable Gate Array (FPGA) is presentI. Histogram
equalization is an effective means ofimage enhancemea Its Real-time processing requires a great deal ofmemory and very high processing
s_. The kjc cell natureofXC4000 làmily's FPGA is nest suitable forpfomiing aI-thne pixel-level image pmcessing operations such as
1stogram equalization A core is constmctedto completethe Fñstogram statistics and histogram equalizatioa As aresult the chip makes ciiuiits
aixi system nre effetive than ev and it takes very short time to compide the calailation and generate the look-up table (LUT). The
equalizingtechnique is described and p1ementationresu1tsusingaXiIinx XC4OIO FPGAare presented.

Keywonls: Iniageenhancement, Histom equalization, FiedPmgrammab1e Gate Anay (FPGA).

1. INTRODUCTION
Histogram modification is one ofthe most wmmon mdhods usedto enhance imageby scaling image gray. A simple arxl effeiive way ofit is
histogram eualizañon, which can increase iforniation by compressingthe gray levels that have few pixels, aed exteixlingthe gray levels
that have more pixels The processing speed must be very fast in real-time pmcessing systeim Sofiware processing is not fast enc and
hardware processing is necessary

Somecircuits for equalizing bistomuse micropmcessortowmulate histogramand cakthte look-uptable 1LUT). The hardwam of histogm
statistics3 usually consists ofRAM full adda aklress regjster and clock controll c. The LUT is usually stored in two additional RAMs or a
double poIt RAM to rewiite or slxw. The separate arcuit is also used for read/write controL So the cñuit is very large and complex and the
microprocessor doesn't mn quickly. The separate circuit thcrses processmg time aix! makes much instability. Ifthe system intendsto cany out
uthp1Dcessing fimctions the speed can't metheneed ofreal-lime processing.

Inorderto implement real-time processing twt ways should be taken account of One isusing VLSI cirouit, which can greatly decreasethe data
teansmitsingtime from IC to IC and avokithe instability ofthe process. The oth is using ASIC to implement histogram mOdificatiOn (&ich as
lstogram iualization). The funthons of these two ys can be realized by using Field Programmable Gate Aimy FPGA). FPGA can
implement tFfunctions constitutedby different ICs (TFL 74 families orCMOS 4000 families) . Sothecimit canbe simplified. The Xilinx
XC4000E$amily combines architectural veiaüIity on-chip Sekct-RAM memory with edge-iriggered and dual-poit modes, vy high speed,
and aixindant routing resources. Its clock rate can reach more than 100 MHz, and the delay bween internal configurable logic block (CLB) is
less than iOns so that FPGA can implement high speed calculation Hardware design canbe flexible and convenient as software.

In the present pap an overview of the ciiuut of image histogram equalization is first described. Then, the circuit fbi cumulating and taking
histogram statistics is desaibed, and the implementation of histogram equalization based on FPGA is presented and finally, for a 256 multiplied
by 256 pixels image, simulationresoltsofhistogram equalization inaXllinx XC4O1OE G191-4 device are given

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 2. SYSTEM DESCRIPTION
A block diagram of implementation of histogram equalization is shown in Fig I The inpit analog signal ofblack-white image is liit quantized
to a precision of 8 bits by a conventional linear quantizer One frame has 256 multiplied by 256 pixels aix! thae are 256 gray levels. Then the
histogram of one frame is ccxnited, and the cumulative histogram is calculaterl The LUT whose data length is 8 bits can also be obtained by
using the data of memoiized frame as addresses. Finally, the equalized data are c*lput through WT and converted to analog o1pit signal.
more pixels image, such as 512x512 pixels image, can also be processed by this way.

Figure 1: Overview ofanFPGA implementation of histogram equalization

2.1.Llistogram Modifkation(Cniy Scale Modificalion)

The histogram of an image is probability dislribution of each gray level. Foradigital image, the discrete expression of probability is:

p(k)=-, k=O,1,•••,L—1 (I)

wleL meansthetotal numberofgiay levels;p(lc) isthe probability ofthe kthgtay level flkisthe rvmber ofpixels ofthe lab gray level, n is the
sum ofpixelsofan image.

Histogram rrodification(Gmy scale nxxlification)is a simple aix! effectivewayto changethe dynamic range cr connstofan image. Inthis way,
thegray scaleofinpit imageis changedtotheother differentgray scale foroutpit image. 11 expressionofchange isg=T(f), wherefisthe input
gray value, OfL-1, aix!gisthe output gray value, OgM4, VAIICMIS thetal mimberoftransfonned graylevels. A curve, atable or a
formula can express ii CaIOJIatingaIXI nalyzingtheltistogramofinput image can getthe suitabletiunsibim equation.

WhentF are a seiiesofimages required to process, we conk! choose a required histogram ofoutput image in advance, then seek the transform
between input and output images. At fi'* we calculate th& cumulative histogram c(f) and cg) according to the histogramp9) of the input
images and the histogramp(g) ofther red output images reeively:
f
c(f)=p(k)=c(f—l)+p(f) (2)
c(g)= Ph(k). c(g — l)÷ p(g)
I
Then, we choice one ofgibreachfin ordthat cjg) is closet to c(f), and the equationg=T() is achieved The quanmy of calculation is little, but
the effect is satisfied.

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 Flistogramequalization intendsto make that every gray level ofoutt image has approximately equal number ofpixels. The image processed
by t1s way looksc1ea Equalized histogram or balanced 1stogram means that the 1stogram ofoutput image isp/g)=nM The cuniulañve
histogmm is c=1fg=gitM Atthattime, the capacity ofinfornialion and entropyofimage will bethe 1agest.

The discrete equationofhistogram equalization is

o;f;;L-1 (3)

f
wfxe k cumulative number ofpixels whose gray value is between zo and/f For atypical image of256x256x8bit. equation (3)

canbe\Mittenas

256—1
g= 256x256 ''k (4)

which canbe simplified as

if
g=j-nk (5)

I
To simplifythe following calculation, we 9JbstienkforJ4) ashistogram, and substitite k forc(9 astheaiinulalivehistograiu

2.2. Impkmcntalion ofCumulative Histogram

As we mennoned above, the wmulative histogram is requeed to g the gray (histogram)transformation equation in gray scale modification
Consideiing the characteiislic arxl usage ofitistogram, we first count histogram and then cumulate it. Finally, histogram uaIization can be
achieved.

2.2.1. Impiementalion ofilistogram Statistics

The block diagram ofhistoam statistics is shown in Fig 2. To an imag ch memoiyunit must be 16 bits long ifwe cid p&tioilar case
that all pixels are concenüated in one gray leveL Theie are 256 gray levels, and a 256 multiplied by 16 bit memory aimy MA) is need to be
configured to storethe numba ofpixeis ofeach gray level. The gray value is the address ofMA After a datum ofpixel is injxii the datum of
relevant address unit is reado added 1 and saved in a 16-bit regist REG1 and REG2 aretwo 8-bit registers saving gray values ofthe next two
pixels. The "&" gute and the block "decision" judge wlxither next two data is equal or rxt If they are equal, the datum in the register
continuously adds 1; else, the datum is wiitten back in MA After a frame, the data in MA are the statistic histogram. They can be used to
calculate the cumulative histogram or to process ither transformation The units of MA are cleaned when the next frame synchronous signal
amves, and staslic is restaited.

The Xllinx XC4000E family devices are the first programmable logic devices with edge-triggered (synchronous) and dual-poit RAM accessible
to the user Depending onthe selected mode, a singte CLB can be configured as 16x2, 32x1, or 16x1 bit anay. We use 128 CLBsto configure a

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 256x16 bitMA A 16-bit adda-(fiill orparallel)ocaipies 8 to 16CLBs. An 8-bit registuocoipies4ClBs, and a 16kregQocaipies 8W3s.
When CLB is ud asRAM, address read/write cycle time address sup lime and oths are all less than l5ns. When CLB is used as adder or
acaimulatoi; one calculating paiod is less than 10 us. And t1 dod cycle ofdelay time ofev&y logic combination is less than 10 ns. For a
256x256 pixels image, the sample points are 256 per line, and the sample cycle time is 200 ns p pixel, so it is enough to finish statistic
caIcuIation Butthe time c*d between address aiil data read/wñte signals must be scheduled carefully. Whenthe system processes evety pbd
on pipdine, it is easi-to hiiplement statistic ofpixdsofa frame.

Fgwe 2: Schematic diagramfor gng statistic histograim

Figure 3: Schematicdiagramtog ainiulative histogramand XtLUT

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 2.22. ffistognim CUmUbiliOnand s Reakzidion
Histogram cumulation is the sequent calQilation based on the histogram astic. Its block diagm is shown m Fig 3. The address gtor
brings about address from OOh to fib, conesponding to the gray levels from 0 to 255. Begjnning from 0 unit the datum is output from MA to a
16-bk parallel add aixi the reiIt is saved ma 16-bit registei The datum ofthenext address is input intothe adder whathe next pilse is arnved,
and the last result is also inpt into the adder These two data are added there and the new cumulative result is outTxlt. All cumulative results are
saved in cumulative histogram memoly which is an external RAM An address generatoruses less than 16 CLBs. The ck)ck rate is 50MHz.

2.2.3. Histognun Equalkzation and Output of LUT

Equation (5) meansthat equalized histogem equals the result of the cumulative histogram divided by To omputer, division of a datum by 2
means being shifted one bit iight and a shill register can miplement it In fact, the advanced 8 bits ofthe cumulative histogram isthe gray value of
equalizatioa Saving them in an extemal memory can get the LUT. The length of each unit is 8 bits. The address is edginal gray value, and the
unit memorizes the transformed gray value.

Figure 4: Block diagram of system

2.3. Realizalion of Histogram Equakzation on FFGA

The block diagram of histogram equalizationbased on aFPGAis shown in Fig. 4, wherethe biggest pane isthe circuit integrated in aFPGA

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 The 8-bit digital data is saved in a buffer as the address of mt MA and the a)ntent of flame memory The ciiuiit lbr ging histogram
statistics is the sldow block described in Fig 2 When the even field hidden signal arrives, the data in MA are read out to caiailaic cumulative
histogram and output to build [liT When the next odd field synchronous signal anives, MA, all add and nster.s are cleaned New
calculation begins. The new data are utlea from LUT which addresses are the gray values of onginal uriage Thc equalized image is then output
Frame memory uses Flip-flops

3. SIMULATION

2000 --—-..-- ,

1500

1000

L 500

100

(a) Original Image (b) FIistotam of Origin Image

2000

300
(c) Equalized Image (d) Histogram of Equalized Image

Figure 5. Simulation ofHistogram Equalization.

Figure 5 (c) is the resiilt of equalizing the histogram of the original image shown in Figure 5 (a). Tbeir histograms are shown in Figure 5 (b) and
(d), recty The effect is vy obvious. Output images are delayed in a flame time and no flame is lost, if we don't wish anydelay fbi output
images, we can use the first LU1 as the next image's LU1 and meantime the flame memory can be tak off Only the first frame is kst, but

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 others are opt almostwithout dday. Thisway vill not influencetheprocesshg quality ausetheirstfnme andthe nextuaially have similar
histograni Ifwe pmcess oth gray iransform related to cumulative histogram, we could only reconstruct the part except for the aimulalion
block

4. ACKNOWLEDGMENTS
The authocs gratefully acknowledgetI support from NatiOnaiHigh Th. R&DPnects ofChina They would liketo thank Prof Zhoc Liwei
forvaluable guidmforthispape The authors also gratefully acknowledgethe suppoit fitmDt WangYiforthe expimea

5. REFERENCES
1. W. K Pratt, Digital lnige Pmcessiig, Wiley, New York, 1991.
2. Li Dexiong, DigiInxzge Pmass71rg, Publishing House of Bepng 1n eofTechnokgy, Beijing, 1990.
3. Histrcün c7m11 r-thwurofimzgepricescing Oio-EIectmnicEngineenng, v 19, n 2.
4. Fukukshima, Tadisbi,A &uwyofInePtrice&cngISlsoiiajxvi,Proc hit ConfPatternRecognit, v2, Proceiings of
the 10th Intationa1 Confence onPatternRecognmon, Ailantic City NJ, USA, 1990, IEEE.
5. XC4()OOEFPGA Fa —TethnicalThulaliwk, Xilirix mc, San Jose, 1995.
6. Meng Xlanyuan, Teth dC iea,iJ&mirnrSenes, Publishing House ofElectitñcs indusUy Beijing, 1995.

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